Abstract: A PCI bridge device includes an arbiter that uses state information comprised of knowledge of the bus protocol and a history of recent transactions to predict the type of transaction a requestor will issue. The prediction is then used as a basis to mask or allow bus requests from the requester. The arbiter does not grant access to devices that will predictably issue transactions that do not result in the transfer of data. This approach can decrease time wasted by devices attempting unsuccessful transactions and can provide a commensurate increase in bus utilization. The overall effect is an increase in average bus bandwidth and a decrease in average data transfer latencies.

Abstract: Methods and apparatus provide for: assigning each of a plurality of requesters to a respective one of a plurality of requester groups; receiving tokens from a plurality of resources, where each token is an exchange medium for permitting one of the requesters having the token to access an associated one of the resources for a period of time; receiving requests for the tokens from one or more of the requesters; allocating the tokens to at least one of the respective requester groups and the requesters thereof based on token allocation criteria; and dynamically re-assigning one or more of the requesters among the requester groups based on feedback information concerning at least some prior token allocations.

Abstract: A bus arbitration method for arbitrating a bus in a computer capable of executing a plurality of tasks by a plurality of devices connected to the bus is provided and includes: acquiring a task information at a timing, the information containing a priority of each of the tasks and a usage rate of each of the devices for executing each of the tasks; producing an information of a bus use condition of each of the devices on the basis of the priority and the usage rate so that that the bus is preferentially assigned to a device necessary to execute a task having high priority; and arbitrating the bus between the devices according to the information of the bus use condition.

Abstract: A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

Abstract: The present invention discloses re-configurable data transmission ports with data-integrity transaction controlling unit in a computerized computer and the method for performing the same. The controlling unit further includes a port-configuration detecting mechanism and a buffer-configuration subunit. The port-configuration detecting mechanism can inspect configuration status of all of the first ports on variance of data transmission bandwidths, e.g. “merge” or “spilt” status. The buffer-configuration subunit upon different configuration status of each first port configures each retry buffer. When a specific first port is configured on “merge” status, the buffer-configuration subunit can follows up to configure the retry buffer owned by the specific first port and the retry buffers owned but disused by the other first ports to constitute a buffer group with merging of storing spaces of said configured retry buffers.

Abstract: There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.

Abstract: Modular information handling systems supported in a modular chassis, such as blade information handling systems, have power allocation managed by dynamic and automated prioritization of power application to each modular information handling systems. A priority list of modular information handling systems is generated and updated by analysis of priority factors discovered from the modular information handling systems, such as with periodic polling of the modular information handling systems or detection of predetermined events at the information handling systems.

Abstract: A method, a system and a computer programmable product have been provided for arbitrating bus cycles among a plurality of device nodes. Requests for bus grant are received from the device nodes. Each request includes values of one or more arbitration parameters. The requests grouped at a first stage, with two requests in each group. A comparison is performed in each group, based on the values of the one or more parameters. Further, winners from each comparison are forwarded to a next stage. Subsequently, comparisons are performed over one or more stages to select a winner of the bus grant.

Abstract: A bus arbiter that ensures high priority transfers complete and allows high-priority data transfers with specific latency requirements, such as 802.11 requirements, to be prioritized above data transfers with lower latency requirements. As an example, the arbiter closely manages all transactions and guarantees sufficient latencies by pre-empting lower-priority data transfers with higher priority data transfers. All devices on the bus are configured with a latency timer setting of zero or a non-zero value which guarantees required data transfer latencies are met which means that any device will terminate bus-master transfers quickly upon the bus grant signal being de-asserted. To ensure a transfer completes, bus grant for the priority transfer is asserted until entire data transfer completion is imminent, enabling transfers, such as high priority transfers, to complete uninterrupted.

Abstract: A method for controlling bi-directional data transfers in an electronic circuit is provided. The method involves when a first of at least two data signals is activated as an originating data signal prior to a second of the at least two data signals: allowing only a device associated with the first of the at least two data signals to be a signal source, and causing a device associated with the second of the at least two data signals to enter a receive state as a signal sink. The method further involves passing at least one bit of data from the signal source to the signal sink.

Abstract: A communication system according to an embodiment of the invention includes: a plurality of communication nodes; and a common bus connected with the plurality of communication nodes, wherein the plurality of communication nodes individually checks a use state of the bus to allow/disallow transmission, and at least one of the plurality of communication nodes includes: a storage circuit storing data representing whether or not a frame follows a first frame sent to the bus; and a control circuit determining, when outputting a second frame after the completion of transmission of the first frame, whether or not to output the second frame to the bus with reference to the data stored in the storage circuit.

Abstract: A method for arbitrating access to a resource shared by several electronic elements. Each element is allocated a first counting value and a first penalty, the first counting value is decremented in synchronization with a clock signal, and is incremented by a value equal to the first penalty every time the element is selected for an access cycle. When several elements are simultaneously waiting to access the shared resource, an element is selected to access the resource if its first counting value is lower than or equal to a determined threshold, and is lower than the first counting values of the other elements having sent an access request.

Abstract: A method for arbitration grants access to an ultra high priority device if the ultra high priority device requests access. This access is limited to a selectable number of accesses. Thereafter the ultra high priority device is masked from requesting access for a selectable interval of time during which access may be granted to other devices. The number of assess and the interval of masking are preferably controlled by memory mapped data registers loaded into dedicated counters.

Abstract: A bus arbitration algorithm precisely controls the relative bus channel bandwidth allocated to each master device by considering the direction of, and/or the bus channel bandwidth consumed by, a bus transaction. At least one weighting register is associated with each master device; in one embodiment, one weighting register per bus channel. The register is periodically loaded with a proportionate share of the available bus bandwidth. Upon being granted a bus transaction on a bus channel, the corresponding weighting register is decremented by an amount that reflects the bus channel bandwidth consumed by the transaction, measured in amount of data transferred or number of bus data transfer cycles required to complete the transaction. In the case of equal initial allocation of relative bandwidth share, master devices that consume bus channel bandwidth will have relatively low priority; master devices that do not consume bus channel bandwidth retain relatively high priority.

Abstract: Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bus arbitration logic uses a request vector and an arbitration vector to determine a grant vector. The grant vector indicates what primary component should be allowed bus access.

Abstract: A mechanism is provided for balancing I/O among available paths connected to a device. The mechanism partitions paths so a device can use all or only a subset of available paths to a device, depending on the load of I/O for other devices that are sharing the paths. The partitioning of paths is dynamic, readjusting as I/O loads change for the devices.

Abstract: A priority register is provided for each of a multiple processor cores of a chip multiprocessor, where the priority register stores values that are used to bias resources available to the multiple processor cores. Even though such multiple processor cores have their own local resources, they must compete for shared resources. These shared resources may be stored on the chip or off the chip. The priority register biases the arbitration process that arbitrates access to or ongoing use of the shared resources based on the values stored in the priority registers. The way it accomplishes such biasing is by tagging operations issued from the multiple processor cores with the priority values, and then comparing the values within each arbiter of the shared resources.

Abstract: A method for arbitration among a plurality of requesting devices for a shared resource in which one device is an ultra high priority device grants access to one requesting device at a time. The ultra high priority device is granted access if it requests access interrupting access by another device. The ultra high priority device is limited to a selectable number of accesses and thereafter is masked for a selectable interval. This interval permits access may by other devices. Each of the other devices is also limited to a selectable number of accesses followed by re-arbitration. The other devices can have a normal priority or a time out priority if a request hasn't been granted in a selectable amount of time.

Abstract: In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

Abstract: A programmable logic device, in accordance with an embodiment of the present invention, may comprise a bus and a plurality of programmable masters configurable to interface the bus. A first portion of a memory may include configuration data operable to configure masters of the plurality, while a second portion of the memory may include access patterns to control when the different masters of the plurality may access the bus. An injection rate controller may control when a given master is to send data on the bus based on the access pattern associated with the master. A master controller may be operable to write the access patterns for the masters to the second portion of the configuration memory.

Abstract: Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and allows the requests corresponding to a bank receiving the largest number of pending requests priorities; and write request information generated by masters is stored in a predetermined buffer to be output as additional master request information, and provides the corresponding master with an opportunity to generate new request information.

Abstract: A computing system includes one or more buses, a plurality of bus agents, and a chip set. The plurality of bus agents are capable of accessing at least one of the buses. The chipset arbitrates access to a bus for at least two of the bus agents such that utilization of the bus for each agent is changeable.

Abstract: In a bus system, in accordance with reservations of transfers of isochronous blocks of data and with requests by the node devices for transfers of ones of the isochronous blocks of data and regular blocks of data, a bus manager generates a schedule of the operating rate of a bus channel, the frequency of assignment of the bus channel, and the size of a continuously transferred piece of data on the bus channel for each of the blocks of data, so that the piece of data is transferred at the operating rate of the bus channel as low as possible in each transfer cycle.

Abstract: An adaptive weighted arbitration algorithm that is user configurable is discussed. The arbitration logic and algorithm considers past arbitration history events and is dynamic to allow for losing bidders to increase their probability of being selected to access the resource based on an accumulator value and a weight value.

Abstract: In a first aspect, a first method of scheduling a command to be issued on a bus is provided. The first method includes the steps of (1) associating an address and priority with each of a plurality of commands to be issued on the bus, wherein the priority associated with each command is based on the address associated with the command; (2) updating the priority associated with each command after a predetermined time period; and (3) from the plurality of commands, selecting a command to be issued on the bus based on the address and updated priority associated with the command to be issued. Numerous other aspects are provided.

Abstract: The information processing device comprises first and second master circuits and an arbiter for arbitrating access rights to a bus to which the master circuits are connected. The arbiter has storage units retaining information representing priorities of the access rights, and an arbitration control logical unit for arbitrating the access rights of the master circuits based on the information. When the priority of the first master circuit is higher than the priority of the second master circuit and there is no access request from the first master circuit but there is an access request from the second master circuit, the arbitration control logical unit permits access of the second master circuit, and the storage units lower the priority of the second master circuit without changing the priority of the first master circuit.

Abstract: An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of the functional blocks via high level primitives. Each agent generates in response a critical rank vector comprising at least first and second components. An arbitrator receives the critical rank vectors generated by rival the agents and applies a maximum or minimum extracting mechanism to at least one of the two components of the critical rank vectors to uniquely identify the block accessing the resource. Thus, functional blocks can be separated from arbitration control, the agents implementing the arbitration control and being solely responsible for it.

Abstract: In one embodiment, a system for providing both wireline and wireless connections to a wireline interface includes a first wireline interface, a second wireline interface, a wireless interface, and a switch coupled to the first wireline interface, the second wireline interface, and the wireless interface. The switch can selectively couple the first wireline interface to the second wireline interface to allow communication between the first and second wireline interfaces. The switch can further selectively couple the first wireline interface to the wireless interface to allow communication between the first wireline interface and the wireless interface.

Abstract: According to an aspect of the invention, there is provided a data transfer control device that carries out data transfer in a data transfer system, in which plural bus masters are connected to a system bus and the data transfer between the bus masters is arbitrated by bus arbitration of each of the bus masters, between the bus masters, the data transfer control device including: an execution cycle monitoring section that monitors an access state for the system bus at the bus master when plural bus masters simultaneously request a use right with respect to the system bus; and a function execution order changing control section that changes an execution order of plural functions included in the bus master to be monitored, based on the access state monitored by the execution cycle monitoring section.

Abstract: A system and method for arbitrating for access to a resource group between agents according to a respective programmable weight for each agent. For each agent, a programmable mapping module selectively couples a respective arbitration handshake signal of the agent to one or more arbitration ports, and the number of the coupled arbitration ports for the agent is the respective programmable weight. A selection module selects one of the arbitration ports in response to a priority ranking of the arbitration ports, and access to the resource group is granted to the agent that has the respective arbitration handshake signal that is selectively coupled by the programmable mapping module to the selected arbitration port. A ranking module provides the priority ranking of the arbitration ports and updates the priority ranking in response to the selection module selecting the selected arbitration port.

Abstract: A method, system and computer program product for creating and dynamically selecting an arbiter design within a data processing system on the basis of command history is disclosed. The method includes selecting a first arbiter for current use in arbitrating between requestors for a resource. During operation of said data processing system, an arbiter selection unit detects requests for the resource and selects a second arbiter in response to the detected requests for the resource.

Abstract: The invention provides a system and method for memory bus assignment for a plurality of functional devices. According to a preferred embodiment, the invention provides a system comprising a plurality of functional devices accessing a memory bus wherein the memory bus allows access by one of the functional devices for one cycle of period of time, a plurality of request agents corresponding to the functional devices, a control register respectively storing access priority grades for the request agents, a plurality of counter timers respectively loading the access priority grades; and a bus elector coupled with the counter timers wherein the bus elector respectively compares the loaded access priority grades and elects one out of the request agents according to the compared access priority grades. The memory bus accordingly allows access by one of the functional devices corresponding to the elected request agent for one cycle of period of time.

Abstract: A bus arbitration system may include a plurality of masters and a bus arbiter. Each of the plurality of masters may include a buffer and/or a buffer level sensor to generate a control signal based on a length of a data queue in the buffer and a critical value of the length. The bus arbiter may arbitrate bus occupation between the plurality of masters according to original priorities, and may selectively modify the original priorities of a first master and a second master of the plurality of masters based on bus resource utilization. Therefore, a real-time bus environment may be reflected in arbitrating bus occupation.

Abstract: A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An additional agent may monitor the symmetric arbitration of the symmetric agents, and at a given stage of the symmetric arbitration assert a priority agent bus request. The priority agent bus request may be shared with another priority agent. This may permit the additional agent to access the bus in a fair manner that behaves as though it were an additional symmetric agent in the system.

Abstract: Arbitration for a communications channel can be provided by scheduling a grant for future access to one of a plurality of requestors to a communications channel shared by the plurality of requestors based on an indication of which of the plurality of requestors is granted access to the communications channel during a current access.

Abstract: A method and apparatus of deprioritizing a high priority client. An isochronous data stream request is generally referred to as a “high priority” client. These high priority requests are sensitive to time, such that a certain amount of data must be retrieved within a certain amount of time. The fetching of this data will cause increased latencies on lower priority clients making requests for data. A method and apparatus for deprioritizing a high priority client is needed to improve the efficiency in handling data traffic requests from both high priority and lower priority clients.

Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Abstract: A two-stage arbiter system comprises a first-stage arbiter to grant a request to one of a plurality of requestors in accordance with a first arbitration scheme and a second-stage arbiter to grant one of the remaining requests in accordance with a second arbitration scheme. The first arbitration scheme may be a fast arbitration scheme such as a fixed-priority scheme, and the second arbitration scheme may be a rotating priority-based arbitration scheme or a least-recently-granted arbitration scheme. The first-stage arbiter may operate in a first pipelined stage, and the second-stage arbiter may operate in a second pipelined stage. Two-stage arbitration may help improve access of lower-priority requestors in a pipelined system. In one embodiment, a rotating-priority arbitrator includes a pseudo-random number generator to generate an amount for rotating priorities prior to arbitration. The rotating-priority arbiter may use either a counter or linear-feedback shift register to rotate priorities of requests.

Abstract: A bus arbitration system employs counters respectively provided for an encoding section and an decoding section that are started when there is a request signal from the respective encoding section and decoding section. The counter values are outputted to respective comparators that compare the counter values with predetermined values and the results of the comparisons are fed to an arbitration controller. The arbitration controller in turn determines priority rankings for the encoding section and the decoding section based on the signals inputted from the comparators and outputs an acknowledgement signal to the module that has the highest priority.

Abstract: Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.

Abstract: A system and method wherein a bus arbiter grants access to a bus to bus-coupled clients in order to provide access to a memory resource shared by the clients in response to “address retry” conditions induced by such clients. The bus arbiter provides access to the bus in response to whether one of the requesting clients experienced an “address retry” condition during its previous bus access. If such an address retry condition was experienced during its previous bus access, the bus arbiter grants such one of the requesting clients access to the bus at the earliest opportunity. Otherwise, the bus arbiter provides bus access to the requesting one, or ones, of the clients based on criteria independent of “address retry” conditions being induced on the bus.

Abstract: A system (100) having a plurality of bus masters (111–113) coupled to an arbiter (150) is disclosed. An arbiter (150) is coupled to a first storage location (151) and a second storage location (152), where the first and second storage locations store bus master parking information for a system bus (141). The arbiter (150) receives a parking context indicator (131) that is used to select one of the first and second storage locations (151, 152) to provide bus master parking information to the arbiter (150).

Abstract: A resource allocation arbitration system. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for resources. Each indicator enables indication of a condition in which the request stored in each storage device is almost empty. Furthermore, the mask bits enable preemption of one request by another request.

Abstract: A method for arbitrating a bus grant among a plurality of master devices for access to a shared bus is disclosed. The method includes the steps of starting to accumulatively count time in response to a data transfer request signal outputted by one of the master devices for requesting a data transfer, and re-estimating a bus-utility condition for the one of the master devices to access to the shared bus when a preset threshold value of time is counted up. In addition, an arbiter for a bus grant among a plurality of master devices for access to a shared bus is disclosed. The arbiter is characterized by including a plurality of timer devices in communication with the plurality of master devices, respectively.

Abstract: A bus arbitration apparatus includes a storage, a priority order determiner, and an arbitrator. The storage stores a plurality of selection signals for specifying a priority order against a number N of requests. The priority order determiner causes the storage to output one of the plurality of selection signals in a predetermined sequence in response to a demand for arbitration. The arbitrator performs an arbitration operation based on the priority order against the number N of requests specified by one of the plurality of selection signals which is output from the storage.

Abstract: A system and method for providing a desired degree of fairness of access to data transfer resources by a plurality of command-initiating bus agents. A bus arbiter allocates general ownership of the bus to one of a plurality of bus agents, and a fairness module imposes a desired degree of fairness to the data transfer resources by mandating data transfer resource access to bus agents whose commands have been subjected to a retry response. The degree of fairness is controllable, in order to appropriately balance the desired throughput and data transfer resource allocation for a particular application.

Abstract: In a programmable fixed priority and round-robin arbiter and a bus control method of the same, the arbiter includes, an HPRIF rotating unit, a request-reordering unit, a request-selecting unit, and a grant-reordering unit. In the fixed priority mode or the round-robin mode, the HPRIF rotating unit rotates priority information related to bus masters stored in a predetermined register in a predetermined direction to give the highest priority to a bus master in response to pointer information and outputs changed priority information. When a request signal is received from the bus masters, the request-reordering unit reorders requested priorities of the bus masters to be in accordance with the changed priority information and outputs a request-reordering signal. The request-selecting unit outputs a bus master-selecting signal according to priorities in response to the request-reordering signal.

Abstract: A method for granting access to a bus is disclosed where a fair arbitration is modified to account for varying conditions. Each bus master (BM) is assigned a Grant Balance Factor value (hereafter GBF) that corresponds to a desired bandwidth from the bus. Arbitration gives priority BMs with a GBF greater than zero in a stratified protocol where requesting BMs with the same highest priority are granted access first. The GBF of a BM is decremented each time an access is granted. Requesting BMs with a GBF equal to zero are fairly arbitrated when there are no requesting BMs with GBFs greater than zero wherein they receive equal access using a frozen arbiter status. The bus access time may be partitioned into bus intervals (BIs) each comprising N clock cycles. BIs and GBFs may be modified to guarantee balanced access over multiple BIs in response to error conditions or interrupts.

Abstract: Various approaches grant access to a shared resource. An arbitration circuit includes request shapers that each receive a request from one of the requestors and assign a respective predetermined priority level and age to each of the requests. An arbiter core receives the requests and grants access to the shared resource to each of the requestors corresponding to the requests. The arbiter core includes a mask circuit that includes a plurality of mask registers each corresponding to a respective one of the priority levels. The age of a respective one of the requests increases when the corresponding one of the requestors is not granted access to the shared resource. The priority level of a respective one of the requests increases according to the age of the respective one of the requests.

Abstract: A method and apparatus for arbitrating between a plurality of masters for use of a common bus. Arbitration is preferably performed based on an urgency and a predetermined priority of a master requesting use of the common bus, wherein a lower priority master requesting urgent use of the common bus can be granted authority to use the common bus over a master having a higher priority.