Abstract: Methods and apparatuses are provided for alignment of hardware and software Vsync signals through filtering out delayed timestamp signals in a hardware timestamp signal used to generate the software Vsync. The alignment may occur when a display client is operating in a video mode but not a command mode. A compositor or processing unit may receive a hardware Vsync signal from a display using a video mode, generate a hardware timestamp signal based on the hardware Vsync signal, determine a delay for a pulse in the hardware timestamp signal based on a delay for a set of previous frames, determine whether the delay for the pulse is over a threshold, and control rendering and transmission of a frame to the display based on the delay for the pulse being over the threshold. Thus, accurate Vsync signal synchronization may occur.

Abstract: A communication control device for a user station. The communication control device controls a communication of the user station with at least one other user station of the bus system, and generates a transmission signal for transmission onto a bus and/or receives a signal from the bus. The communication control device generates the transmission signal according to a frame in which bits having a predetermined temporal length are provided. The communication control device generates the transmission signal so that its bits may be transmitted bus as a dominant state or a recessive state, so that the recessive state is overwritable by the dominant state. The communication control device shortens in the transmission signal at least one bit, which is to be transmitted as the dominant state, by a predetermined value in comparison to a bit that is to be transmitted onto the bus as the recessive state.

Abstract: A transceiver includes a driver stage and a transient-triggered ring suppression circuit. The driver stage has a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal. The transient-triggered ring suppression circuit is coupled to the first and second transistors. The transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state. Further, while the transceiver is in the recessive state, the transient-triggered ring suppression circuit is configured to attenuate ringing on at least one of the first or second bus terminals.

Abstract: A method, a computing device, and a non-transitory machine-readable medium for performing a multipath selection based on a determined quality of service for the paths. An example method includes a host computing device periodically polling a storage system for path information including an indication of a recommended storage controller. The host computing device periodically determines a quality of service information corresponding to a plurality of paths between the host computing device and a storage volume of the storage system, where at least one of the plurality of paths including the recommended storage controller. The host computing device identifies a fault corresponding to a path of the plurality of paths that routes I/O from the host computing device to the storage volume. The host computing device re-routes the I/O from the path to a different path of the plurality of paths, where the different path is selected for the re-routing based on the quality of service information and the path information.

Abstract: A Controller Area Network, CAN, device, (400) is described that includes: a CAN transmitter (430) connected to two CAN bus terminals (401, 402) of the CAN device (400); a receiver circuit (450) operably coupled to the two CAN bus terminals (401, 402) of the CAN device (400); and a controller (432) connected to the CAN transmitter (430). The controller (432) is configured to: determine whether the CAN device (400) is operating as a transmitter node or a receiver node; detect a transition of the CAN device (400) from a dominant state to a recessive state; and in response to detecting both a transition of the CAN device (400) from the dominant state to the recessive state, and the determination of whether the CAN device (400) is operating as a transmitter node or a receiver node, control an output impedance of the CAN transmitter (430) to be within an impedance value range whilst a differential driver voltage on a CAN bus (104, 304, 404) connected to the CAN device (400) decreases to a predefined voltage.

Abstract: In an embodiment, a computing node includes a computing circuit, a comparing circuit, and an indicator circuit. The computing circuit is configured to generate a first redundant message that corresponds to, and that is independent of, a source message propagating over a network during at least one time period. The comparing circuit is configured to compare information content of one or more corresponding portions of the source message and the first redundant message during each of the at least one time period to generate a comparison result. And the indicator circuit is configured to indicate whether the source message is valid or invalid in response to the comparison result. For example, such computing node can determine the validity of a redundant result with reduced processing overhead, reduced message delay, and reduced message latency as compared to existing computer nodes.

Abstract: Entropy agnostic data encoding includes: receiving, by an encoder, input data including a bit string; generating a plurality of candidate codewords, including encoding the input data bit string with a plurality of binary vectors, wherein the plurality of binary vectors includes a set of deterministic biased binary vectors and a set of random binary vectors; selecting, in dependence upon a predefined criteria, one of the plurality of candidate codewords; and transmitting the selected candidate codeword to a decoder.

Abstract: Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. The controller may implement a hierarchical scheme comprising first-level arbitration(s) between submission queues of each of a plurality of input/output virtualization (IOV) functions, and a second-level arbitration between the respective IOV functions. Alternatively, or in addition, the controller may implement a flat arbitration scheme, which may comprise selecting submission queue(s) from one or more groups, each group comprising submission queues of each of the plurality of IOV functions. In some embodiments, the controller implements a credit-based arbitration scheme. The arbitration scheme(s) may be modified in accordance with command statistics and/or current resource availability.

Abstract: Techniques and mechanisms provide a flexible mapping for physical functions and virtual functions in an environment including virtual machines.

Abstract: A method of performing multiple data bus inversion (DBI) and a memory device performing the method are provided. The multiple DBI includes first through third DBI operations, wherein the first DBI operation determines whether to perform data inversion on a first data inversion group in which M×N data bits of a M×N data bit structure are grouped and performs the data inversion on the first data inversion group, the second DBI operation determines whether to perform data inversion on second data inversion groups formed by grouping M data bits from among the M×N data bits and performs the data inversion on the second data inversion groups, and the third DBI operation determines whether to perform data inversion on third data inversion groups formed by grouping N data bits from among the M×N data bits and performs the data inversion on the third data inversion groups.

Abstract: A processor including computation groups, each computation group including computation cores, the processor being capable of simultaneously implementing a plurality of applications, each application being implemented by a computation core and possibly requiring a read-mode or write-mode access to an external memory connected to the processor. At least one core, called dedicated core, of at least one computation group is dedicated to management of the external memory, the management making it possible to temporally and spatially organize read-mode and write-mode accesses to the external memory of each application requiring a read or a write in the external memory implemented by the processor.

Abstract: A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus. A module is configured to send a message over the communication bus.

Abstract: Systems and methods are described for verifying functionality of a computing device. A set of rules are sent to a computing device identifying a device driver. Data is received from the one device that is indicative of collected driver data of the computing device. The data is collected by a driver verifier function executing on the computing device. The driver verifier function is configured to capture information associated with the identified device driver identified by the set of rules. The received data is parsed to categorize the data with previously collected driver data of other computing devices. The data is categorized based on attributes of the collected driver data. The categorized data is provided for analysis of the driver health on the computing device.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: An improved transmission system that utilizes a shared buffer accessible by multiple threads, processes, or other discrete systems of different producing speeds is disclosed which limits transmission bottlenecks which occur when producers write data at different speeds. The system reserves portions of the shared buffer for each of the different producers, and allows the producers to write to the shared buffer asynchronously—even if the shared buffer is read from serially. This allows a fast producer to write its data to the shared buffer without needing to wait “in line” for slower producers.

Abstract: A data storage device includes first and second controllers that independently and simultaneously process data from a recording medium. The first and second controllers each have respective first and second buffer managers coupled to respective first and second buffer memories. The first and second buffer managers are coupled to each other via an inter-controller data bus. The first controller is configured to receive a contiguous memory request for a block data transfer client of the first controller. A first part of the request is fulfilled from the first buffer memory via the first buffer manager, and a second part of the request is fulfilled from the second buffer memory via the second buffer manager communicating with the first buffer manager via the inter-controller data bus.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: An apparatus includes an arbiter and a plurality of arithmetic processors, each including an arithmetic circuit and a measuring circuit. The arithmetic circuit executes an arithmetic process, and the measuring circuit measures a progress level indicating a progress of the arithmetic process executed by the arithmetic circuit. Upon receiving access requests to an external device from first arithmetic processors included in the plurality of arithmetic processors, the arbiter arbitrates the access requests, based on a result of comparing the progress levels measured by the measuring circuits of the first arithmetic processors.

Abstract: A CAN FD frame comprises one or more portions provided at a normal bit rate that includes an end-of-frame field consisting of a succession of at least seven recessive bits. A method for detecting the end-of-frame of a CAN FD frame in an input bit stream entails providing a recessive bit count; defining a stretched bit transmission time longer than the bit transmission time associated with the high data rate; stretching the bit transmission time of each dominant bit succeeding a recessive bit in the input bit stream to the stretched bit transmission time to generate a conditioned input bit stream; sampling the conditioned input bit stream at a bit counter rate to generate a sampled bit stream; resetting the recessive bit count in response to each dominant bit in the sampled bit stream; and incrementing the recessive bit count in response to each recessive bit in the sampled bit stream.

Abstract: An integrated circuit may include a memory controller that interfaces with memory that operates using a memory clock signal having repeating memory clock cycles. The memory controller may include controller circuitry that receives memory access requests and generates corresponding memory commands using a controller clock signal having repeating controller clock cycles. The controller circuitry may partition each controller clock cycle into time slots that are associated with respective memory clock cycles. Each generated memory command may require a corresponding number of memory clock cycles to fulfill using the memory. The controller circuitry may assign a time slot to each memory command while preventing conflicts with previously issued memory commands.

Abstract: A processor uses a token scheme to govern the maximum number of memory access requests each of a set of processor cores can have pending at a northbridge of the processor. To implement the scheme, the northbridge issues a minimum number of tokens to each of the processor cores and keeps a number of tokens in reserve. In response to determining that a given processor core is generating a high level of memory access activity the northbridge issues some of the reserve tokens to the processor core. The processor core returns the reserve tokens to the northbridge in response to determining that it is not likely to continue to generate the high number of memory access requests, so that the reserve tokens are available to issue to another processor core.

Abstract: A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus. A module is configured to send a message over the communication bus.

Abstract: A storage apparatus includes a processor. The processor calculates an upper limit of an input/output processing amount, which is determined based on priority levels set to a plurality of storage devices, for each storage device. The processor schedules an execution sequence of processes relating to input/output requests received from information processing apparatuses based on processing amounts relating to the input/output requests and the upper limits. The processor executes the processes relating to the input/output requests in the scheduled execution sequence. The processor is configured to determine, for each storage device, whether or not a processing amount of the storage device exceeds a processing bandwidth of the each storage device for a first predetermined time. The processor changes the upper limit for each storage device in a predetermined bandwidth accommodation unit in a case where the processing amount for each storage device is determined to exceed the processing bandwidth.

Abstract: An apparatus and method for effectively implementing a wireless television system may include a communications processor and a transmitter device that combine at least one of a local-area network interface, a wide-area network interface, and one or more television data interfaces for effectively performing a wireless network transmission process. A transmitted stream from the wireless television system may be received via wireless network processing for viewing local-area network data, wide-area network data (such as Internet data), or television data by flexibly utilizing various electronic devices such as a notepad personal computer, a personal digital assistant (PDA), or a handheld TV remote control device.

Abstract: A technique configures data storage equipment to (i) allow host I/O operations to start on storage devices while a credit tally is less than a predefined credit quota and (ii) block host I/O operations from starting on the storage devices while the tally is greater than the quota. The technique further involves, while a rebuild procedure is not being performed on the storage devices, (i) allocating host I/O credits at equal weight to the tally upon starting host I/O operations and (ii) de-allocating the credits at equal weight from the tally upon completion of the operations. The technique further involves, while the rebuild procedure is being performed on the storage devices, (i) allocating host I/O credits at greater than equal weight to the tally upon starting host I/O operations and (ii) de-allocating the credits at greater than equal weight from the tally upon completion of the operations.

Abstract: In a method for exchanging data in messages between users of a CAN bus system, the users have their own time bases; a first user functioning as timer transmits a reference message having a specifiable identifier via the bus, which includes a first time information with regard to the time base of the first user; the at least second user, using its time base forms its own second time information as a function of the first time information of the first user in such a way that, from the deviation of the first and the second time information a correction value is ascertained, so that from the first time information of the first user as the timer, the global time for the bus system is yielded.

Abstract: In an embodiment, a processor may include a completion time determination circuit. The completion time determination circuit may be configured to receive one or more source operands of a vector memory operation used to produce the addresses of the vector elements accessed by the vector memory operation. The completion time determination circuit may be configured to determine a completion time for the vector memory operation (e.g. based on a number of TLB accesses, a number of cache accesses, and/or other aspects of the vector memory operation). The completion time determination circuit may provide the completion time to an issue circuit, which may use the completion time to schedule operations dependent on the vector memory operation, if any.

Abstract: According to one aspect of the present disclosure a method and technique for managing memory access is disclosed. The method includes setting a memory databus utilization threshold for each of a plurality of processors of a data processing system to maintain memory databus utilization of the data processing system at or below a system threshold. The method also includes monitoring memory databus utilization for the plurality of processors and, in response to determining that memory databus utilization for at least one of the processors is below its threshold, reallocating at least a portion of unused databus utilization from the at least one processor to at least one of the other processors.

Abstract: A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed.

Abstract: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal, generating a first mode register setting signal, delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal, receiving a data signal in synchronization with the second mode register setting signal, and writing the mode signal to the mode register only if the received data signal has a first logic level.

Abstract: A First Come First Server (FCFS) arbiter that receives a request to utilize a shared resource from a plurality of devices and in response generates a grant value indicating if the request is granted. The FCFS arbiter includes a circuit and a storage device. The circuit receives a first request and a grant enable during a first clock cycle and outputs a grant value. The grant enable is received from a shared resource. The grant value communicated to the source of the first request. The storage device includes a plurality of request buckets. The first request is stored in a first request bucket when the first request is not granted during the first clock cycle and is moved from the first request bucket to a second request bucket when the first request is not granted during a second clock cycle. A granted request is cleared from all request buckets.

Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.

Abstract: The presence of devices attached to a bus are detected by a controller of a bus transmitting a signal on a channel of the bus, to cause each device to hold the channel to a first logical state for a duration of time that is unique to each device. The device that holds the channel to the first logical state for the longest duration of time is detected. Detected devices remain idle while undetected devices repeat holding the channel to the first logical state for the duration of time, until detected. All devices are detected when the channel returns to a second logical state.

Abstract: According to an embodiment, a circuit for using a shared memory is provided, which has a plurality of function circuits, a bus, an arbitrator, and a communication measuring device. Each of a plurality of the function circuits performs a prescribed calculation. The bus communicates an input/output signal of each of the function circuits. The arbitrator assigns a use right of the bus to each of the function circuits. The communication measuring device measures a communication time of each of the function circuits, determines whether or not the measured communication time is within a range of a reference communication time set for each of the function circuits, and stores this determination result in a determination result storage device accessible from outside.

Abstract: Systems and methods for encoding a slot table for a communications controller of a communications network are described. In one embodiment, a method for encoding a slot table for a communications controller of a communications network includes classifying branches of the communications network that are connected to the communications controller into at least one group, where each of the at least one group includes multiple branches, and generating a slot table entry for a time slot for accessing the communications network through the communications controller based on the at least one group. Other embodiments are also described.

Abstract: An integrated circuit includes a trace subsystem that provides timestamps for events occurring in a trace source that does not natively support time stamping trace data. A timestamp inserter is coupled to such a trace source. The timestamp inserter generates a modified trace data stream by arranging a reference or references with the trace information from the trace source on a trace bus. A trace destination receives the modified trace data stream including the reference(s). In some embodiments, a timestamp inserter receives a timestamp request and stores a reference in a buffer. Upon later receipt of trace information associated with the request, the timestamp inserter inserts the reference, a current reference and the received trace information into the trace data stream.

Abstract: Systems and methods are described for arbitrating access of a communication bus. In one embodiment, a method includes performing steps on one or more processors. The steps include: receiving an access request from a device of the communication bus; evaluating a bus schedule to determine an importance of the device based on the access request; and selectively granting access of the communication bus to the device based on the importance of the device.

Abstract: A star coupler has the ability to distinguish signals arriving via connections according to the time slot in which they arrive and to forward these signals to at least one other connection on the basis of the connection via which the signals arrive and on the basis of the time slot. An assignment in which the star coupler once treats the bus system as a single bus system and virtually divides the bus system into two subsystems in another time slot is possible in particular.

Abstract: A multimode communication integrated circuit comprising baseband processing circuitry with a shared radio interface. Various aspects of the present invention may comprise a processor module adapted to perform various processing (e.g., baseband processing) in support of multimode communications. A first radio module may be communicatively coupled to the processor module through a common communication interface. A second radio module may also be communicatively coupled to the processor module through the common communication interface. The common communication interface may, for example, be adapted to communicate information over a communication bus that is shared between the processor module and a plurality of radio modules (e.g., the first and second radio modules).

Abstract: Central bus guardians (CBGs) and methods for operating a CBG are described. In one embodiment, a method for operating a CBG includes performing race arbitration among the buses connected to the CBG to select a winner bus for a time slot, and selectively forwarding data received at the CBG from the winner bus to a destination bus in the time slot based on whether the winner bus or the destination bus has a connection to an external network with respect to the application network and whether a communications device connected to the winner bus or the destination bus performs a critical function. Other embodiments are also described.

Abstract: A motor vehicle has a FlexRay bus. Values for operating parameters are stipulated for the FlexRay bus. The value for at least one selected operating parameter is obtained from an optimization method in which, on the basis of prescribed messages to be transmitted via the FlexRay, a plurality of values for the at least one selected operating parameter have an allocation—associated with these values—of slots to the prescribed messages provided for them according to a predetermined rule, and a predetermined sequence of the allocation is rated according to a predetermined criterion.

Abstract: A data transfer device controls data transfer performed through a bus capable of separately processing a request and a response. The data transfer device include a plurality of access control units that produce a data transfer process according to the request; and an arbitration unit that performs arbitration between the requests issued by the plurality of access control units so as to determine a request to be accepted among those requests. The arbitration unit sets an arbitration prohibited period in which the arbitration is prohibited for a designated period and accepts only the request issued by a designated access control unit among the plurality of access control units during the arbitration prohibited period.

Abstract: A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus. A module is configured to send a message over the communication bus.

Abstract: A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level.

Abstract: Structures and methods herein insert one or more parallel “recessive nulling” driver impedances across a controller area network (CAN) bus starting at the time of a dominant-to-recessive data bit transition and extending for a selected recessive nulling time period. Doing so increases a rate of decay of a CAN bus dominant-to-recessive differential signal waveform, permits a shortened recessive bit time period, and allows for increased CAN bus bandwidth. Various modes of operation are applicable to various CAN bus node topologies. Recessive nulling may be applied to only the beginning portion of a recessive bit following a dominant bit (“LRN mode”) or to the entire recessive bit time (“HRN mode”). And, some embodiments may apply LRN operations to some recessive CAN frame bits and HRN operations to others.

Abstract: A SAS expander includes a receiver module, a timer module and an arbitration module. The receiver module is to receive initiator requests which include initiator wait time values and specify requested targets. The timer module has timers to generate total wait time values representing length or time the initiators having been waiting for the specified requested targets. The timers are to be initialized with wait time values comprising the initiator request wait time values and user-defined wait time values. The arbitration module is to select an initiator request having the highest total wait time value from among the initiator requests requesting the same targets.

Abstract: Certain aspects of an apparatus and method for interconnection may include an interconnection section, a request processing section and a response processing section. The interconnection section may be configured to transfer a request from a master interface bus to a slave interface bus and to transfer a response from the slave interface bus to the master interface bus. A slot number within the request specifies a time slot during which the interconnection section may be permitted to transfer the response to the master interface bus. The request commands the processing section to load the slot number into a management table. The response commands the response processing section to read out the slot number from the management table.

Abstract: In a node communicably coupled to alternative nodes through a bus, a transmitting unit receives first designation information from an alternative node. When the first designation information designates the node, the transmitting unit successively transmits, on the bus, the first designation information and data. When a request of an active communication occurs in the node, a request unit determines whether to receive a former part of the first identification information indicative of start timing of an active communication mode on the bus. When determining to receive the former part of the first identification information, the request unit transmits, on the bus, collision information at a timing that allows the collision information to collide with a latter part of the first identification information, resulting in rewrite of the first identification information based on bus arbitration, and transmits second designation information meeting the request of the active communication.

Abstract: A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus. A module is configured to send a message over the communication bus.

Abstract: Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to cause the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.