Abstract: A method and a communication system for exchanging data between at least two users interconnected over a bus system are described. The data is contained in messages which are transmitted by the users over the bus system. To improve data exchange among users so that in the normal case, there is a high probability that it will be possible to transmit messages with a low latency, while on the other hand, in the worst case, a finite maximum latency can be guaranteed, the data be transmitted in an event-oriented method over the bus system as long as a preselectable latency period elapsing between a transmission request by a user and the actual transmission operation of the user can be guaranteed for each message to be transmitted as a function of the utilization of capacity of the bus system, and otherwise the data is transmitted over the bus system by a deterministic method.

Abstract: The present invention relates to a method for arbitrating requests from masters to grant access to shared resources, wherein each master has an individual weight. The method comprises the steps of assigning time slots to the masters depending on the weights of the masters, mapping the current time slot index (32) to a reordering index (30), receiving a plurality of requests from N masters, reordering the requests into a request vector (14) depending on the reordering index (30), searching for predetermined logical values in the request vector (14), generating a grant vector (18) according to the index of the found logical values in the request vector (14), inversely reordering the grant vector (18) into an output grant vector (22) depending on the reordering index (30), and calculating a new time slot index (32) on the basis of the current time slot index (30) and the grant vector (18). Further the present invention relates to a system for performing the method.

Abstract: A highly-reliable storage system and data input/output control method, which can ensure priority data input/output performance, is provided.

Abstract: In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

Abstract: A computing system includes one or more buses, a plurality of bus agents, and a chip set. The plurality of bus agents are capable of accessing at least one of the buses. The chipset arbitrates access to a bus for at least two of the bus agents such that utilization of the bus for each agent is changeable.

Abstract: System and method for reacting to an expected impact involving a vehicle including an anticipatory sensor system for determining that an impact involving the vehicle is about to occur prior to the impact and an impact responsive system coupled to the sensor system and actuated after its determination of the expected impact. The sensor system includes wave receivers spaced apart from one another, each receiving waves generated by, modified by, or reflected from a common object exterior of the vehicle. The impact responsive system attempts to reduce the potential harm resulting from the impact and can be a protection apparatus which protects a vehicular occupant or a pedestrian, such as one including an airbag and an inflator for inflating the airbag.

Abstract: There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to establish an isochronous channel between a first device and a second device, establishing the isochronous channel between the first device and the second device, and generating an isochronous transaction across the isochronous channel between the first device and the second device, wherein the isochronous transaction is a message type transaction.

Abstract: A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existing between a network device, e.g., an HDLC controller, working in conjunction with the host processor, receives data, including any preselected address fields. The network device includes a plurality of ports. Each port includes a FIFO receive memory for receiving at least a first portion of a frame. The first portion of the frame includes data having the preselected address fields. A direct memory access unit transfers a burst of data from the FIFO receive memory to the shared system memory. A communications processor selects the amount of data to be transferred from the FIFO receive memory based on the desired address fields to be analyzed by the host processor.

Abstract: A method is provided for transmitting messages, for example, in a telecommunications network, in which a first message service and a second message service are available. Dedicated messages of the first message service are sent using messages of the second message service. An exemplary method may permit an optimized transmission scheme to be maintained for the dedicated messages of the first message service.

Abstract: A system and method for guaranteeing transactional fairness among multiple requesters contending for a common resource in a cache-coherent multiprocessor system is described. Batch processing is used to control servicing of multiple requests made by multiple requesters (such as processors) of a common resource in a cache-coherent multiprocessor system. Specifically, identification numbers are assigned to requests as they are received from the multiple requesters. The identification numbers are then used in conjunction with batch processing to prioritize and guarantee servicing of the requests.

Abstract: A system for distributed processing of multimedia contents includes a plurality of microprocessor devices associated with one or more communication networks. Each device includes one or more components able to process said multimedia contents according to the requirements of one or more applications forwarded through at least one of the devices comprising a MultiMedia Framework for managing processing of multimedia contents. The MultiMedia Framework includes an application-programming interface. At least one of the devices includes one or more agent modules which can operate according to a service-discovery protocol for publishing on the communication network in a manner accessible to the application-programming interface, to components supported locally by one or more of the devices and to components supported by devices arranged remotely on the communication network.

Abstract: A method and a device for exchanging data in messages between at least two stations connected via a bus system, the messages containing the data being transmitted by the stations over the bus system and the messages being controlled over time by a first station in such a manner that the first station repeatedly transmits a reference message over the bus at least one specifiable time interval and the time interval is divided into time windows of specifiable length, the messages being transmitted in the time windows, a reference message and the subsequent time windows until the next reference message being combined into a first cycle, and the first station interrupting the transmission at the end of a first cycle due to a stop request, in particular, a message of the at least second station.

Abstract: Method and apparatus for controlling access to memory circuitry is described. In one example, access to the memory circuitry is controlled among a plurality of bus interfaces of a data processing system. A plurality of ports is respectively coupled to said plurality of bus interfaces. Arbitration logic is configured for communication with the plurality of ports. The arbitration logic arbitrates access to the memory circuitry among the plurality of bus interfaces on a time shared basis.

Abstract: A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight to each of the processors in a second tier. The bus arbiter may sequentially grant bus access to the one or more processors during an initial portion of a bus interval based on the assigned second tier weights, and grant bus access to any one of the processors during the initial portion of the bus interval in response to a request from said any one of the processors having a first tier weight. When multiple processors are requesting access to the bus, the bus arbiter may grant bus access to the requesting processor with the highest weight in the highest tier.

Abstract: A bus arbitration system and method allocates total bus bandwidth between latency sensitive and latency insensitive interfaces by utilizing windows to divide the total bandwidth into latency sensitive and latency insensitive portions. Each interface is initially allocated top-up numbers of latency sensitive and latency insensitive tokens to proportionally allocate bus accesses between the interfaces according to their requirements. For an interface having access to the bus, the number of tokens is decremented for each successful bus transfer.

Abstract: The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first priority level is within its bandwidth allocation, then a request is issued from that channel. If there are no requests in channels at the first priority level that are within the allocation, requests from channels at the second priority level that are within their bandwidth allocation are chosen. If there are no requests of this type, requests from channels at the third priority level or requests from channels at the first and second levels that are outside of their bandwidth allocation are issued. The system may be implemented using rate-based scheduling.

Abstract: A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors where split-isochronous transaction descriptors are supported.

Abstract: According to embodiments of the present invention, a peripheral component interconnect (PCI) standard hot-plug controller (SHPC) includes a command register to store PCI slot operation commands for one or more target PCI slots and a programmable register that may be programmed with one timing parameter value (e.g., Tpccc, Tpece, Tcebe, Tbkrk, etc.) for a signal sequence for execution of one PCI slot operation command and another timing parameter value for a signal sequence for execution of another PCI slot operation command depending on the particular target PCI slot, the particular PCI slot operation command loaded into the command register, and/or the number of times a particular PCI slot operation command has been loaded into the command register, for example.

Abstract: A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each individual request, determine a priority for the request, and transmit the request to a priority appropriate path. A first high priority arbiter receives and arbitrates among highest priority requests in a round robin manner to determine a high priority suggested grant vector. At least one lower priority arbiter receiving and arbitrating among lower priority requests in a round robin manner to determine at least one lower priority suggested grant vector. Grant circuitry passes the high priority suggested grant vector unless said grant circuitry receives a low priority indication, whereby the grant circuitry passes a lower priority grant vector.

Abstract: A system and method for low impact backup. In one embodiment, a method may comprise monitoring utilization of a system resource and a data management process selectively performing I/O operations dependent upon the monitored utilization of the system resource. The data management process may include functionality to backup desired data from a storage medium to a backup medium. In one particular implementation, the I/O operations may be allowed to be performed in response to the utilization of the system resource falling below a predetermined threshold. In another embodiment a method may comprise performing a plurality of I/O operations to complete a data management process executed by an application. The application separates said plurality of I/O operations with intermittent delays to achieve time-slicing of the data management process with respect to one or more other applications.

Abstract: A method and apparatus for position dependent data scheduling for communication of data for different domains along a bus is provided. Having an awareness of the relative position of different domains along a bus, one embodiment of the present disclosure schedules bus operations to allow data from multiple bus operations to be simultaneously present on the bus while preventing interference among the data. The present disclosure is compatible with buses having a termination on one end and those having terminations on both ends. In accordance with one embodiment of the present disclosure, bus operations are scheduled so that first data of a first bus operation involving a first domain are not present at domains involved in a second bus operation at times that would result in interference with second data of the second bus operation.

Abstract: Various methods and systems provide interfaces between legacy data buses such as MIL-STD 1553 buses and wideband data buses such as IEEE 1394 data buses. One technique for interfacing a legacy device to a wideband data bus includes the broad steps of receiving legacy data in a legacy format from the legacy device, acquiring a timeslot on the high-speed data bus for at least a portion of the legacy data, embedding the portion of the legacy data into the timeslot to thereby transmit the portion of the data on the wideband data bus, repeating the acquiring and embedding steps until all of the received data is transmitted on the wideband data bus. The timeslot may be, for example, an immediate timeslot obtained via an interrupt-type request, or an acknowledge-accelerated arbitration requested timeslot occurring during a recurring access window.

Abstract: Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.

Abstract: A data processing system (100) comprises a system bus (120), a plurality of devices (110, 150, 160, 170) coupled to the system bus (120), a bus monitor circuit (140), and a clock generator (130). The plurality of devices (110, 150, 160, 170) includes at least one bus master (110, 150) which is capable of performing accesses on the system bus (120). The bus monitor circuit (140) is coupled to the at least one bus master (110, 150), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (120). The clock generator (130) has an output coupled to at least one of the plurality of devices (110, 150, 160, 170) and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

Abstract: The invention provides quality-of-service (QoS) delivery services over a computer bus having isochronous data transfer capabilities. A transmitting node on the bus transmits a message to an intended recipient indicating a requested bandwidth for a connection. If the intended recipient has sufficient resources, it allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits the data on the allocated channel. If the recipient cannot allocate a channel, it does not respond, and the transmitter thereafter detects a time-out condition and begins transmitting using a “best efforts” scheme (i.e., non-guaranteed time delivery). In a second variation, a receiving node detects that it is receiving large quantities of data from a transmitting node. In response, the receiving node allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel.

Abstract: A method and apparatus are provided in a computing environment for scheduling access to a resource. The method grants access to the resource by a non-real-time request when the non-real-time request can be completed before the latest possible start time at which a first real-time request must start service to timely complete all actual and anticipated real-time requests, otherwise granting the first real real-time request access to the resource.

Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.

Abstract: A robust packet arrival time detector using a power estimate to validate a packet arrival time measurement. A packet arrival time measurement is considered valid when the value of the power estimate signal indicates that a packet is being received. A power estimator comprises a bandpass filter, a Hilbert transform, two squaring devices, an adder, and a lowpass filter.

Abstract: A method for granting access to a bus is disclosed where a fair arbitration is modified to account for varying conditions. Each bus master (BM) is assigned a Grant Balance Factor value (hereafter GBF) that corresponds to a desired bandwidth from the bus. Arbitration gives priority BMs with a GBF greater than zero in a stratified protocol where requesting BMs with the same highest priority are granted access first. The GBF of a BM is decremented each time an access is granted. Requesting BMs with a GBF equal to zero are fairly arbitrated when there are no requesting BMs with GBFs greater than zero wherein they receive equal access using a frozen arbiter status. The bus access time may be partitioned into bus intervals (BIs) each comprising N clock cycles. BIs and GBFs may be modified to guarantee balanced access over multiple BIs in response to error conditions or interrupts.

Abstract: Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a predefined time period.

Abstract: Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.

Abstract: The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a data command ring, coupled to the plurality of APUs. The data command ring is employable to carry indicia of a selection of one of the plurality of APUs to the APUs. The data access ring also has a data address ring, coupled to the plurality of APUs. The data address ring is further employable to carry indicia of a memory location to the selected APU a predetermined number of clock cycles after the data command ring carries the indicia of the selection of one of the plurality of APUs. The data access ring also has a data transfer ring, coupled to the plurality of APUs. The data transfer ring is employable to transfer data to or from the memory location associated with the APU a predetermined number of clock cycles after the data address ring carries the indicia of the memory location to the selected APU.

Abstract: A system prevents disruption of one or more system buses. The system monitors communication on the one or more system buses during an input mode and an output mode and detects changes between the input mode and the output mode. The system determines whether a predetermined time period has elapsed after a change from the input mode to the output mode and changes from the output mode to the input mode when the predetermined time period has elapsed after a change from the input mode to the output mode.

Abstract: In a computer system, which makes an error detectable in case plural PCI target devices respond in one PCI cycle and the PCI protocol has become illicit, a processor 1 is connected over a PCI bus 10 to plural PCI devices a 100 to d 130, each of which activates corresponding target operating signal a 20 to d 50 respectively when operating as a PCI target device. The PCI bus monitor circuit 200 monitors the target address of a command executed on the PCI bus 10 and the target operating signals a 20 to d 50 from the plural PCI devices a 100 to d 130. If plural PCI target devices have responded for one PCI cycle, the PCI bus monitor circuit 200 sends an error report signal 210 to the processor unit 1.

Abstract: A bus system has a bus, a number of units which can be connected to one another via the bus, and a bus controller. The units request the bus controller for bus access when they require a connection to one or more other units, and the bus controller decides which unit will be allocated to the bus. The bus system is distinguished in that at least some of the units which can request bus access are allocated values which indicate how long and/or how frequently the relevant unit can be allocated the bus or has been allocated the bus, and in that these values are used to decide whether a unit which is requesting bus access is allocated the bus, or whether a unit which requires bus access is requesting the bus at all.

Abstract: A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus arbiter has programmable rankings for assigning priorities to requests from blocks that are masters for either one of the both buses. Software and methods are also provided for assigning the priorities. The requests are analyzed with respect to which of the buses they require, and then priorities are assigned to maximize bus utilization, with increased speed for a system on a chip. In addition, a multi-jurisdictional multi-channel direct memory access block can be a master block for the system bus or the external bus.

Abstract: A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

Abstract: An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An IOC memory map register, which is utilized by an input/output chip (IOC), is configured during the window of time using the IOP. In addition, a hide indicator is configured to indicate the IOC should be hidden. In this manner, data is communicated between the IOP and the IOC using the IOC memory map register. In one aspect, the hide indicator can be configured, before the window of time, to indicate the IOC should be hidden. In addition, the hide indicator can be configured during the window of time to indicate the IOC should be exposed.

Abstract: In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

Abstract: A method for testing a transmission system is disclosed. The method comprises receiving a time division multiplexed (TDM) stream on an input of the transmission system. The method also comprises inserting test data in one or more of the plurality unused fields of the TDM stream. Additionally, the method comprises transferring the TDM stream along a plurality of components of the transmission system and comparing the test data against the transferred test data.

Abstract: A single shared processing path is used as contexts are switched during processing. Each unique context is processed using a corresponding unique pipeline. If a pipeline that is executing under one context stalls, processing is switched in the shared processing path to another pipeline that is executing under second context. New pipelines are enabled for execution by borrowing a clock cycle from the currently executing pipeline. In some cases contexts are assigned various relative priority levels. In one case a context switching microprocessor is used in a communication engine portion of a system-on-a-chip communication system.

Abstract: A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the second bus agent. The method includes monitoring the use of the bus by the first bus agent during the window and the regulation durations of the windows are selectively regulated based on the use.

Abstract: An arbiter (7) is provided for a QMS having multiple queue users (5A to 5D), each having real time requirements for mastership of a bus (31). The arbiter (7) is arranged so that the amount of time that each queue user (5A to 5D) can gain bus access is a percentage of the total bus time.

Abstract: A host channel adapter configured for outputting packets according to InfiniBand™ protocol includes a queue pair attributes table having queue pair entries configured for specifying attributes of the respective queue pairs. Each queue pair entry includes a timestamp field for storing a time value. Upon teardown of a queue pair, a management agent stores a timestamp value, according to a prescribed time resolution interval, within the timestamp field and sets a corresponding wait state bit. The queue pair attributes table is accessed each prescribed time resolution interval for identification of idle queue pairs having passed a minimum idle interval at least equal to the prescribed time resolution interval. If an identified idle queue pair has a corresponding timestamp value indicating passing of the minimum time idle interval, the corresponding wait state bit is reset enabling the queue pair to be reused.

Abstract: A method and apparatus for position dependent data scheduling for communication of data for different domains along a bus is provided. Having an awareness of the relative position of different domains along a bus, one embodiment of the invention schedules bus operations to allow data from multiple bus operations to be simultaneously present on the bus while preventing interference among the data. The invention is compatible with buses having a termination on one end and those having terminations on both ends. In accordance with one embodiment of the invention, bus operations are scheduled so that first data of a first bus operation involving a first domain are not present at domains involved in a second bus operation at times that would result in interference with second data of the second bus operation.

Abstract: A system comprises a plurality of memory controllers connected to a memory bus. Each memory controller is able to generate memory requests on the memory bus according to a predetermined priority scheme. One priority scheme is a time slot priority scheme, and another priority scheme is a request-select priority scheme. The plurality of memory controllers are able to monitor memory requests generated by another memory controller in performing memory-related actions, such as memory requests (read or write), read-modify-write transaction, and cache coherency actions. In one arrangement, the memory bus is a Rambus channel.

Abstract: A method and device for the exchange of data in messages between at least two users which are connected by a bus system and have separate time bases, the messages containing the data being transmitted by the users via the bus system; and a first user, in a function as timer, controls the messages as a function of time in such a way that it repeatedly transmits a reference message, which contains time information regarding the time base of the first user, via the bus at a specifiable time interval; the at least second user forms its own time information, using its time base, as a function of the time information of the first user; a correction value is ascertained from the two pieces of time information; and the second user adapts its time information and/or its time base as a function of the correction value.

Abstract: A signal communication device for use within a computer includes a set of optical fibers configured to form an optical computer bus between a set of computer sub-system elements of a computer. A set of input optical connector cards are connected to the set of optical fibers. Each of the input optical connector cards includes a transmitting dynamic bandwidth allocator responsive to an optical bus clock signal operating at a multiple of a computer system clock signal such that a set of bus time slots are available for each computer system clock signal cycle. The transmitting dynamic bandwidth allocator allows a light signal to be applied to the optical computer bus during a dynamically assigned bus time slot. In this way, the optical computer bus bandwidth can be dynamically allocated to different computer sub-system elements during a single computer system clock signal cycle.

Abstract: The invention provides quality-of-service (QoS) delivery services over a computer bus having isochronous data transfer capabilities. A transmitting node on the bus transmits a message to an intended recipient indicating a requested bandwidth for a connection. If the intended recipient has sufficient resources, it allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits the data on the allocated channel. If the recipient cannot allocate a channel, it does not respond, and the transmitter thereafter detects a time-out condition and begins transmitting using a “best efforts” scheme (i.e., non-guaranteed time delivery). In a second variation, a receiving node detects that it is receiving large quantities of data from a transmitting node. In response, the receiving node allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel.

Abstract: In a method and system for transferring data between a plurality of bus devices, a bus interface unit includes a first bus device interface (FBDI), a second bus device interface (SBDI), and an arbitration circuit. Each of the FBDI and SBDI includes a corresponding incoming and outgoing request bus for receiving and transmitting request packets from a corresponding one of the plurality of bus devices. Similarly, each of the EBDI and SBDI also includes a corresponding incoming and outgoing data bus for receiving and transmitting data packets from the corresponding one of the plurality of bus devices. The arbitration circuit is capable of determining priority level associated with corresponding request packets received from the FBDI and the SBDI respectively.