Abstract: Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.

Abstract: A semiconductor device is configured so that two or more master devices access a slave device via a bus. The semiconductor device includes: a priority generation circuit that generates a priority based on a transfer amount between a specific master device and a specific slave device; and an arbitration circuit that performs an arbitration based on the priority when competition of the accesses occurs.

Abstract: Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, a function of the plurality of functions receives input/output (I/O) operations from a host computing system. The processing device further selects a first function of the plurality of functions to service and assigns a first operation weight to a first I/O operation type of I/O operations received at the first function and a second operation weight to a second I/O operation type of I/O operations received at the first function. The processing device also selects, for execution, a first number of operations of the first I/O operation type of the I/O operations received at the first function according to the first operation weight and a second number of operations of the second I/O operation type of the I/O operations received at the first function according to the second operation weight.

Abstract: A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and a circuit coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element.

Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, wherein a function of the plurality of function receives input/output (I/O) operations from a host computing system. The processing device further determines a quality of service level of each function of the plurality of functions, and assigns to each function of the plurality of functions a corresponding function weight based on a corresponding quality of service level. The processing device also selects, for execution, a subset of the I/O operations, the subset comprising a number of I/O operations received at each function of the plurality of functions, wherein the number of I/O operations is determined according to the corresponding function weight of each function. The processing logic then executes the subset of I/O operations at the memory device.

Abstract: A method and communication system has been developed to increase the number of messages sent over a bandwidth limited channel and/or under noisy conditions by using a variable message length encoding and decoding scheme. With this technique, the messages having a higher probability of being sent are shorter as compared to the messages that are less likely to be sent under the current conditions. With this technique, a higher number of transactions per unit of time can be communicated and/or executed over a given bandwidth limited channel. When the transmitted message is received, the receiver does not know the message length, but the receiver deduces the length by using information from various error detection and correction techniques, such as forward error correction (FEC) and cyclic redundancy check (CRC) techniques.

Abstract: A robotic surgical system is disclosed having a ring network for communicating information between a controller and nodes of one or more robotic arms. A communications protocol is described by which synchronous and asynchronous information can be communicated to and from the nodes of the robotic arms. Also disclosed are various aspects of a physical layer that can be used with the network.

Abstract: A method for image processing, an electronic device, and a non-transitory storage medium are disclosed. The method includes obtaining an image captured by the camera and performing edge identification on the image; determining a filtering kernel for a filtering processing on the image according to a result of the edge identification; performing the filtering processing on the image based on the filtering kernel to obtain a low-frequency image and a high-frequency image corresponding to the image; and performing an enhancement processing for the high-frequency image and performing image fusion for the low-frequency image and the enhanced high-frequency image to obtain a processed image.

Abstract: Providing self-resetting multi-producer multi-consumer semaphores in distributed processor-based systems is disclosed. In one aspect, a synchronization management circuit provides a semaphore including a counting semaphore value indicator, a current wait count indicator, and a target wait count indicator. When a consumer completes a wait operation, the synchronization management circuit adjusts the value of the current wait count indicator towards the value of the target wait count indicator, and compares the value of the current wait count indicator to the value of the target wait count indicator. If the value of the current wait count indicator has reached the value of the target wait count indicator, the synchronization management circuit infers that all consumers have observed the semaphore, and accordingly resets both the counting semaphore value indicator and the current wait count indicator to an initial wait value to place the semaphore in its initial state for reuse.

Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.

Abstract: An apparatus and method are provided for arbitrating access to a set of resources that are to be accessed in response to requests received at an interface. Arbitration circuitry arbitrates amongst the requests received at the interface in order to select, in each arbitration cycle, at least one next request to be processed. Each request identifies an access operation to be performed in response to the request, the access operation being selected from a group of access operations. Further, each access operation in the group has an associated scheduling pattern identifying timing of access to the resources in the set when performing that access operation. In response to a given request being selected by the arbitration circuitry, access control circuitry controls access to the set of resources in accordance with the associated scheduling pattern for the access operation identified by that request.

Abstract: A qualifying system receives a channel activity record from one of a plurality of different external systems, over one of a plurality of different communication channels. It accesses qualification rules to determine whether the channel activity record is to be transformed into one or more target entities in a computing system. If so, a conversion engine accesses user-configurable mappings and conversion rules to identify conversion actions that are to be taken in order to transform the channel activity record into one or more target entities. The conversion engine performs a data transformation on the channel activity record to transform it into the identified one or more target entities.

Abstract: An apparatus includes an interface configured to obtain data associated with multiple cables coupled to or forming a part of a redundant token bus control network. The apparatus also includes a traffic detector configured to determine whether valid data traffic is being received over the cables from the redundant token bus control network based on the data. The apparatus further includes at least one processing device configured to determine whether one or more of the cables has experienced a network fault or a return from a network fault based on the determination of whether valid data traffic is being received over the cables. The at least one processing device is also configured, in response to determining that one or more of the cables has experienced a network fault or a return from a network fault, to generate a notification that identifies the apparatus and the one or more cables and output the notification.

Abstract: A device includes a connector including first and second portions, each being configured to establish an independent data connection with a portion of first and second connectors in an external device, and a controller. When the first portion is connected with a third portion of the first external connector, and a request to connect with the second portion is received from the second external connector, the controller determines whether or not to accept the request, and transmit an acceptance signal or a rejection signal to the second external connector through the second portion, according to the determination result.

Abstract: A data processing system includes first and second processing nodes and response logic coupled by an interconnect fabric. A first coherence participant in the first processing node is configured to issue a memory access request specifying a target memory block, and a second coherence participant in the second processing node is configured to issue a probe request regarding a memory region tracked in a memory coherence directory. The first coherence participant is configured to, responsive to receiving the probe request after the memory access request and before receiving a systemwide coherence response for the memory access request, detect an address collision between the probe request and the memory access request and, responsive thereto, transmit a speculative coherence response. The response logic is configured to, responsive to the speculative coherence response, provide a systemwide coherence response for the probe request that prevents the probe request from succeeding.

Abstract: Context values used by filters corresponding to different streams are stored in an interleaved manner in a block of contiguous memory locations, e.g., of a buffer, to facilitate coalesced access of data units, e.g., context values, corresponding to different channels to facilitate filtering of multiple streams, e.g., audio streams, in parallel using a graphics processing unit. Context values corresponding to different channels are intentionally grouped together on an interleaved per channel basis in staging memory. This allows context values for multiple different streams to be transferred, e.g., loaded, as a single block e.g., with a context value of each different channel being loaded into a different GPU core. By organizing the context values to facilitate GPU processing, device operation is improved and execution efficiency is achieved as compared to what would be the case if multiple non-contiguous memory locations had to be implemented to load the cores of the GPU.

Abstract: Various aspects of a system and method for controlling client electronic devices in a wireless local ad hoc network are disclosed. The system includes one or more circuits in a server configured to receive a plurality of speaking-slot requests from a plurality of client electronic devices for a presented content. A client electronic device is selected based on an acceptance of a corresponding speaking-slot request. The acceptance of the corresponding speaking-slot request is based on at least an analysis of the one or more image frames of a user associated with the client electronic device and a context of the presented content. At least an audio stream provided by the user is received from the selected client electronic device. The selected client electronic device is controlled based on one or more parameters associated with at least the selected client electronic device.

Abstract: Systems and methods are disclosed method for operating a serial interconnect of a computer system in a time deterministic manner. An exemplary method comprises that a command to be sent over the serial interconnect in a transaction is to be executed at a specific time. A delay period for the command to be sent from a master of the computer system to a slave of the computer system via the serial bus is determined, where the delay period determined based on a length of an arbitration phase of the transaction. The command is then sent to the slave of the computer system via the serial bus after the delay period.

Abstract: Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple processors and a memory connect interface may be configured to provide an interface for the processors to the shared memory. The memory connect interface may include an arbiter for atomic memory operations from the processors. In response to an atomic memory operation, the arbiter may perform an atomic memory operation procedure including setting a busy flag for an address of the atomic memory operation, blocking subsequent memory operations from any of the processors to the address while the busy flag is set, issuing the atomic memory operation to the shared memory, and in response to an acknowledgement of the atomic memory operation from the shared memory, clearing the busy flag and allowing subsequent memory operations from the processors for the address to proceed to the shared memory.

Abstract: Scheduling jobs from an application based on a job concurrency hint. The job concurrency hint providing an indication of the number and/or size of the jobs that can be handled by the job scheduler. The scheduling of the jobs based on the job concurrency hint including selecting the number and/or size of the jobs to pass to the job scheduler for execution by a thread in a core of a processor.

Abstract: When generating a source code executed by a multi-core processor in order to verify performance of a control system, a device generates the source code as an object of execution by the multi-core processor from a control model, performs cooperative simulation, and measures an execution time of a program in the multi-core processor in the cooperative simulation.

Abstract: In one embodiment, a solid state storage drive comprises a plurality of flash memory devices configured to store a plurality of data clusters having a predefined data cluster size, and configured to store a first part of a first data cluster of the plurality of data clusters on a first page of flash memory and a second part of the first data cluster on a second page of flash memory, a partial buffer completion bitmap stored in a memory, wherein each bit in the partial buffer completion bitmap corresponds to a location in a buffer configured to receive data clusters read from the plurality of flash memory devices, and a controller configured to cause a page of data to be read from one of the plurality of flash memory devices, the page of data including either the first part of the first data cluster or the second part of the first data cluster, the controller including a queue buffer manager configured to change the status of a bit in the partial buffer completion bitmap when either the first part of the first

Abstract: A network device can utilize multiple priority arbiters to support different programmable priorities for different virtual routing and forwarding (VRF) subsystems. Each priority arbiter can be logically connected to all the VRF subsystems in the network device. Each priority arbiter can support a set of features corresponding to functional requirements of a VRF subsystem. A particular priority arbiter can be selected from the multiple priority arbiters based on an association of the VRF subsystem to that priority arbiter.

Abstract: An electronic device and method for operation of same are provided. The electronic device includes a display, a memory, and a processor configured to execute a first operating system, a second operating system and an application run on the second operating system. The processor displays an execution screen of the application on the display, compares, in response to an event that occurs on the first operating system, a priority of an event with a priority of the application, and maintains the execution screen of the application running on the second operating system if the priority of the application is higher than the priority of the event.

Abstract: A method for registering software systems in data-sharing sessions is provided. A set of data-sharing session definitions are stored in storage of a computer system, each of said data-sharing session definitions identifying a set of software system types permitted to participate in data-sharing sessions governed by the data-sharing session definition. A participant registration request is received from a first software system. A priority value is determined, via the computer system for the participant registration request, for each of a first subset of the data-sharing session definitions. The first software system is registered in one of the data-sharing sessions governed by one of the data-sharing session definitions selected at least partially based on the priority values.

Abstract: A method for managing inbound user traffic to a reservation system. The method includes receiving messages from one or more users and determining, by one or more computer processors, at least one of the one or more users is not a preferred user, based on the messages received. The method further includes sending the messages from the at least one user to a limiting component, wherein the limiting component slows the messages from the at least one of the one or more users to the reservation system.

Abstract: Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple processors and a memory connect interface may be configured to provide an interface for the processors to the shared memory. The memory connect interface may include an arbiter for atomic memory operations from the processors. In response to an atomic memory operation, the arbiter may perform an atomic memory operation procedure including setting a busy flag for an address of the atomic memory operation, blocking subsequent memory operations from any of the processors to the address while the busy flag is set, issuing the atomic memory operation to the shared memory, and in response to an acknowledgement of the atomic memory operation from the shared memory, clearing the busy flag and allowing subsequent memory operations from the processors for the address to proceed to the shared memory.

Abstract: An apparatus includes a processor and a guest operating system. In response to receiving a request to create a task, the guest operating system requests a hypervisor to create a virtual processor to execute the requested task. The virtual processor is schedulable on the processor.

Abstract: A method for processing ternary content-addressable memory (TCAM) data. The method may include transmitting a search query to a TCAM device. The TCAM device may store a plurality of TCAM entries. The method may further include obtaining a first matched entry and a second matched entry from the plurality of TCAM entries. The method may further include obtaining, from software precedence data, a first precedence value for the first matched entry and a second precedence value for the second matched entry. The method may further include comparing, using a priority criterion, the first precedence value for the first matched entry with the second precedence value for the second matched entry to select a resultant entry. The priority criterion may determine a precedence order that a computing device uses the plurality of TCAM entries. The method may further include processing, using the computing device, the resultant entry.

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

Abstract: Systems and methods for transmitting inter-processor interrupt messages by privileged virtual machine functions. An example method may comprise: mapping, by a hypervisor being executed by a processing device of a host computer system, a plurality of interrupt controller registers of the host computer system into a memory address space of a virtual machine being executed by the host computer system; mapping, into the memory address space of the virtual machine, a task mapping data structure comprising a plurality of records, each record associating a task with a processor of the host computer system; and mapping, into the memory address space of the virtual machine, a notification code module to be invoked by the virtual machine for writing a notification message into an interrupt controller register associated with a processor identified using the task mapping data structure.

Abstract: A memory system may include: a controller suitable for checking a priority information on a plurality of input commands, storing the input commands having a high priority information as a first command in a first command storage unit, and storing the input commands having a low priority information as a second command in a second command storage unit, and one or more memory device suitable for operating in response to the input commands stored in the first or second command storage units.

Abstract: Described are techniques user to determine expected service levels. A first set of one or more data portions are selected from one or more devices forming a first device set. The first set of data portions are stored on physical storage of a physical device set of one or more physical devices having an unknown service level expectation. I/O operations directed to the first set of data portions are received and serviced for a time period. First information is collected that characterizes performance of the physical device set during the time period. In accordance with the first information and using an adaptive learning technique, a first service level expectation for servicing I/Os directed to the physical device set is determined.

Abstract: A method of controlling access by a master to a peripheral includes receiving an interrupt priority level from an interrupt controller associated with the peripheral, comparing the interrupt priority level with respective a pre-established interrupt access level to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. Further, a circuitry is described including a master, a peripheral, and an access control circuitry including an interrupt controller associated with the peripheral. The access control circuitry is arranged to perform a method of controlling access by the master to the peripheral.

Abstract: In some examples, a method includes assigning, to each respective task queue of a plurality of task queues, a respective priority ratio based at least in part on a number of tasks in the respective task queue. The method further includes assigning, by a processor of a plurality of processors, respective tasks from the respective task queues to at least one processor of the plurality of processors in an order based at least in part on the respective priority ratio, wherein the respective priority ratio defines a relative frequency with which tasks from the respective task queue are assigned to the at leak one processor.

Abstract: Controlling access to at least one memory location by a transaction is provided in a multi-processor transactional execution environment. Included is: tracking execution progress of a transaction, the execution progress being a metric of work performed for the transaction which includes at least one of instructions processed or cycles elapsed; based on encountering a conflict with another process for a memory location, comparing execution process of the transaction and execution progress of the other process; and deciding whether to continue the transaction based on the comparing. For instance, based on the execution progress of the transaction being greater than the execution progress of the other process, the transaction is continued, and based on the execution progress of the transaction being less that the execution progress of the other process, then the transaction is aborted.

Abstract: Controlling access to at least one memory location by a transaction is provided in a multi-processor transactional execution environment. Included is: tracking execution progress of a transaction, the execution progress being a metric of work performed for the transaction which includes at least one of instructions processed or cycles elapsed; based on encountering a conflict with another process for a memory location, comparing execution process of the transaction and execution progress of the other process; and deciding whether to continue the transaction based on the comparing. For instance, based on the execution progress of the transaction being greater than the execution progress of the other process, the transaction is continued, and based on the execution progress of the transaction being less that the execution progress of the other process, then the transaction is aborted.

Abstract: In one embodiment, input-output (I/O) scheduling system detects and resolves priority inversions by expediting previously dispatched requests to an I/O subsystem. In response to detecting the priority inversion, the system can transmit a command to expedite completion of the blocking I/O request. The pending request can be located within the I/O subsystem and expedited to reduce the pendency period of the request.

Abstract: Methods and apparatus for control access to memory in dual-processor. In particular, there are disclosed methods and apparatus for use where a single memory is shared for instructions for the processors and a data store to reduce conflicts between access requirements.

Abstract: Disclosed herein are system, method, and computer program product embodiments for managing non-uniform memory access (NUMA) in a database management system. An embodiment operates by receiving a request to load data from a disk into an in-memory database. An optimal one of the plurality of nodes onto which to load the data from the disk based on a system state is determined. It is determined whether the optimal node has sufficient free local memory in a free list to store the data. If the optimal node does not have sufficient free list memory, a memory allocation is requested from an operating system. An address of the memory storing the data is provided.

Abstract: A method and system is provided to manage and track changes in enterprise architectures. The invention provides a hierarchical visual management tool to manage and update relational information within an enterprise in a controlled fashion. The relationship may be maintained in a database and displayed via graphical user interface. Enterprise assets are categorized into such categories as goals, customer values or requirements, capabilities, resources, and the like. A hierarchy is constructed so that relationships between these various categories are identified and captured using the invention. Weights may be assigned to each element of the categories so that any proposed change to an enterprise architecture may be viewed so that a value can be ascertained and compared between other values of other proposed changes. In this manner, tracking and management of evolutionary changes to an architecture may be accomplished using relational information.

Abstract: The present invention provides a search method used to search for the reading order of a plurality of recording groups when the plurality of recording groups written on tape are continuously read by a tape drive which manages data on tape in recording units having a fixed data length for each recording. This search method includes the steps of: receiving information on a plurality of tape groups to be read; and sorting the plurality of recording groups to be read so the reading time is shortened. In the sorting step, the time required to sort the plurality of reading groups is reduced by combining two or more recording groups into a single object to be sorted in the sorting step when at least two or more contiguous recording groups have been assigned to the same region or are assigned across adjacent regions among the plurality of regions.

Abstract: An apparatus for data processing in a heterogeneous multi-processor environment are provided. The apparatus including an analysis unit configured to analyze 1) operations to be run in connection with data processing and 2) types and a number of processors available for the data processing, a partition unit configured to dynamically partition data into a plurality of data regions having different sizes based on the analyzed operations and operation-specific processor priority information, which is stored in advance of running the operations, and a scheduling unit configured to perform scheduling by allocating operations to be run in the data regions between the available processors.

Abstract: A method includes for each processed interrupt: identifying an interrupt associated with a first interrupt number; determining that the interrupt is designated as a special interrupt, the special interrupt being an interrupt to be translated to a different interrupt number only if the hardware processor is in user mode; determining a current execution mode for the hardware processor; for each interrupt in operating system mode, delivering the interrupt as the first interrupt number; and for each interrupt in user mode: translating the first interrupt number to a second interrupt number; and delivering the interrupt as the second interrupt number, wherein the current execution mode is determined to be an operating system mode for at least one of the interrupts, and the current execution mode is determined to be a user mode for at least an additional one of the interrupts.

Abstract: Systems and methods for applying a fine-grained QoS logic are provided. The system may include a memory controller, the memory controller configured to receive memory access requests from a plurality of masters via a bus fabric. The memory controller determines the priority class of each of the plurality of masters, and further determines the amount of memory data bus bandwidth consumed by each master on the memory data bus. Based on the priority class assigned to each of the masters and the amount of memory data bus bandwidth consumed by each master, the memory controller applies a fine-grained QoS logic to compute a schedule for the memory requests. Based on this schedule, the memory controller converts the memory requests to memory commands, sends the memory commands to a memory device via a memory command bus, and receives a response from the memory device via a memory data bus.

Abstract: Methods for providing non-volatile solid-state mass storage media with different service levels for different types of data associated with different applications. The method includes partitioning the non-volatile solid-state mass storage media into at least first and second volumes, individually assigning different service levels to the first and second volumes based on a type of data to be stored in the first and second volumes and based on the first and second volumes having different data retention requirements and/or data reliability requirements, and then performing service maintenance on data stored within at least the first volume according to the service level of the first volume.

Abstract: Disclosed are various embodiments that facilitate automatically bridging the semantic gap in machine introspection. It may be determined that a program executed by a first virtual machine is requested to introspect a second virtual machine. A system call execution context of the program may be determined in response to determining that the program is requested to introspect the second virtual machine. Redirectable data in a memory of the second virtual machine may be identified based at least in part on the system call execution context of the program. The program may be configured to access the redirectable data. In various embodiments, the program may be able to modify the redirectable data, thereby facilitating configuration, reconfiguration, and recovery operations to be performed on the second virtual machine from within the first virtual machine.

Abstract: A computation device according to the present invention includes: a first data storage unit that stores operation target data; an operation processing unit that executes an operation by using data; a data permutation unit that selects indicated data among the operation target data stored in the first data storage unit and data operated by the operation processing unit, provides predetermined delay for data received a delay indication among the indicated data based on a parameter, does not delay data not received a delay indication, executes permutation of indicated data based on a parameter, and outputs data operated in the operation processing unit and operation result data of the operation processing unit; and second data storage unit that stores the operation result data output by the data permutation unit.

Abstract: This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.