Abstract: The present disclosure describes systems and methods for preemptive masking and unmasking of non-secure processor interrupts. At least some embodiments provide a system that includes a processor capable of operating in a non-secure mode, and preemption logic coupled to the processor (the preemption logic capable of asserting an interrupt signal to the processor). If the processor is operating in the non-secure mode, the preemption logic preemptively inhibits a non-secure assertion of the interrupt signal in response to a mask event. If the processor is operating in the non-secure mode, the preemption logic preemptively enables the non-secure assertion of the interrupt signal in response to an unmask event.

Abstract: In a method for communication between a master node and a plurality of slave nodes connected by a bus therebetween, a first interrupt request is asserted by one of the plurality of slave nodes via a primary interrupt line. The plurality of slave nodes are electrically connected by the primary interrupt line. A unique delay time for requesting an interrupt is associated with each of the plurality of slave nodes. A second interrupt request is asserted by the one of the plurality of slave nodes via a secondary interrupt line electrically connecting the plurality of slave nodes. The second interrupt request is asserted in response to successfully asserting the first interrupt request and after the unique delay time associated with the one of the plurality of slave nodes. A message is then transmitted from the one of the plurality of slave nodes to the master node via the bus.

Abstract: A method and a system for automatically diagnosing disability of computer peripheral devices are provided. In the method, a set of interrupt configuration data relevant to a disabled PCI peripheral device, including relevant setting values of a hardware IRQ routing, is input and compared with a PCI IRQ routing table pre-stored in a boot control unit. Then, whether errors exist in the current setting values of the relevant control parameters and flags of all the relevant control units are automatically checked. If an incorrect setting value is found, a corresponding diagnosis result message is displayed for informing the user to make a modification. Therefore, users can know the reasons that cause the computer peripheral device to operate abnormally and make the modification quickly and effectively.

Abstract: Method and system for managing interrupts originating from multiple sources is provided. The method includes assigning interrupt sources to a group; notifying an adapter of interrupt groups; identifying each interrupt group; writing a first interrupt to an interrupt module, where the interrupt occurs from a first source of the multiple sources; monitoring for a second interrupt; suspending the second interrupt until the first interrupt is processed, if the second interrupt is requested from the first source; and processing the second interrupt, if the second interrupt occurs from a source other than the first source.

Abstract: A method and system of bringing processors to the same computational point. At least some of the illustrative embodiments are computer systems comprising a first processor executing a program, a second processor executing a duplicate copy of the program (but at different computational points in the program), and a shared main memory coupled to the first and second processors. When the processors each receive duplicate copies of an interrupt request, the processors are configured to bring their respective programs to the same computational points prior to servicing the interrupt request.

Abstract: An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and extended prefix and an extended prefix tag. The extended prefix specifies that interrupt processing be suppressed until execution of the extended instruction is completed, where the extended instruction prescribes an operation to be performed according to an existing instruction set. The extended prefix tag is an otherwise architecturally specified opcode within an existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and completes execution of the corresponding micro instructions prior to processing a pending interrupt.

Abstract: Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

Abstract: An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface, a second PCI interface, a PCI bridge serving as a bridge between the first PCI interface and the second PCI interface, and a control circuit for controlling an interrupt signal. The PCI bridge recognizes a message signal interrupt issued from the first PCI interface to the second PCI interface and transfers the message signal interrupt to the control circuit, and the control circuit is provided with an interrupt conversion unit for converting the message signal interrupt into an interrupt signal and outputting it via a signal line.

Abstract: An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed by OS1, a second area storing a reset handler containing instructions for returning to OS2 and for branching to OS2, and a switching unit that switches connection/disconnection of the first area with outside; a table storing unit storing information showing the reset handler's position; a CPU having a program counter and executing an instruction at a position indicated by positional information in the program counter; and a management unit that, when instructed to switch from OS1 to OS2 while the apparatus is operating with OS1, instructs the switching unit to disconnect the first area and the CPU to reset. When instructed to reset itself, the CPU initializes its state and sets the reset handler positional information into the program counter.

Abstract: A method for communicating with a processor event facility is provided. The method makes use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: Methods, systems, and computer program products are provided for scheduling threads in a multiprocessor computer. Embodiments include selecting a thread in a ready queue to be dispatched to a processor and determining whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, embodiments typically include selecting a processor, setting a current processor priority register of the selected processor to least favored, and dispatching the thread from the ready queue to the selected processor. In some embodiments, setting the current processor priority register of the selected processor to least favored is carried out by storing a value associated with the highest interrupt priority in the current processor priority register.

Abstract: The setting of interruption initiatives is directly initiated by external adapters. An adapter external to the processors at which the initiative is to be made pending sends a request directly to a system controller coupled to the adapter and the processors. The system controller then broadcasts a command to the processors instructing the processors to set the interruption initiative.

Abstract: In a device that can execute multiple media applications, but only one at a time, a media server coordinates among applications, but neither the media server nor the individual applications maintain rules regarding all of the different applications. Each connection used by an application is assigned a priority and communicates that priority to the media server when the connection is established. When an application requests to begin playback, the request is granted if no other application is playing, or if another application is playing on a connection having a priority at most equal to that of the connection used by the requesting application, but is denied if the connection already in use has a higher priority. Resumption of an application that was interrupted by another application on a connection with higher priority is determined by the interrupted application after the interruption ends, based on information communicated by the media server.

Abstract: The subject disclosure pertains to a multi-tasking interference system. A gatekeeper receives primary and secondary inputs, and a quantifier ascertains attention values associated with primary inputs and interruption values associated with secondary inputs. Attention values are ascertained based on attributes associated with primary inputs such as type or genre of media presentation, temporal location within media presentation, or a likelihood of impending commercials. Based on a comparison between attention values and interruption values the gatekeeper determines whether, when, and how to interrupt the primary input with the secondary input and accordingly thereafter interrupts the primary input with the secondary input based on the foregoing assessment.

Abstract: A computer system which significantly improves responsiveness to a sleep request includes: a processor device switching between an execution mode and a suspension mode; and an access controlling unit accessing a functional block in response to a command request received from the processor device, wherein, in response to a sleep request signal received from the external device, the processor device responds with a sleep response signal and asserts a suspension notification signal indicating a switch to the suspension mode, and the access controlling unit: masks an input of a further command request after receiving the command request from the processor device, in the case where the processor device has outputted the command request when the access controlling unit receives the suspension notification signal; masks an input of a command request in the case where the processor device has not outputted the command request; and removes the mask when the suspension notification signal is negated.

Abstract: In virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system and has direct access to a hardware device coupled to the virtualized computer system via a communication interface, a computer-implemented method of handling interrupts from the hardware device to the guest operating system includes: (a) receiving a physical interrupt from the hardware device on a shared interrupt line of an interrupt controller; (b) masking the shared interrupt line of the interrupt controller; (c) generating a virtual interrupt corresponding to the physical interrupt to the guest operating system; and (d) the guest operating system executing an interrupt service routine.

Abstract: To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor P1 of the unit processors P0 to P3 comprises an purge inhibit flag 106 for causing the unit processor P1 to enter a lock state where the purge of the task is being inhibited, a hardware semaphore unit 13 for inhibiting other unit processors from accessing a predetermined region in memory accessed by the unit processor P1 after the unit processor P1 is brought into the lock state, and an interrupt control unit 11 for inhibiting the interrupt processor from performing the interrupt handling during the execution of exclusive control.

Abstract: Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

Abstract: The present invention relates to a method, system 1 and/or software 16 for handling interruptions. Upon interruption, a user can place an indicator 60 on their screen. The applications are removed from view. Upon ending the interruption, the applications are redisplayed with a recall indicator 130. During the interruption, information relating to common tasks can be displayed 81.

Abstract: One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt mask value is written to the TPR. In addition, the interrupt mask value is also written into a shadow copy of the TPR. The shadow copy is written each time that the TPR is written. Another embodiment disclosed relates to a method of reducing a latency to read a TPR of an IPF type microprocessor. When a command is received to read an interrupt mask value from the TPR, the interrupt mask value is read from the shadow copy at a memory location, instead of from the task priority register itself.

Abstract: In response to a selected analog applied to the input terminal of an analog-to-digital converter, the digitized output signal is stored in a buffer/register. In making a comparison with a predetermined value, a second buffer/register stores either a preselected value or a second digitized signal. A comparator is coupled to the first and the second buffer/register to provide the result of a comparison. In this manner, the central processing unit is not involved in the comparison testing procedure.

Abstract: A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may, for example, be indicated by a signal from, for example, a slot timer, a state machine may schedule the function that will be permitted to interrupt a processor. Only the scheduled function may interrupt the processor during the slot. Time dependent functions that may be waiting to be processed may have to wait until the start of a next slot. Background functions that are too large to be processed within the time available in a slot may, for example, be divided into segments, each of such segments capable of being processed within the time available in a slot.

Abstract: The setting of interruption initiatives is directly initiated by external adapters. An adapter external to the processors at which the initiative is to be made pending sends a request directly to a system controller coupled to the adapter and the processors. The system controller then broadcasts a command to the processors instructing the processors to set the interruption initiative.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: An interrupt control circuit includes: a section that generates an interrupt signal for requesting an interrupt in response to occurrence of a plurality of interrupt causes; a section that generates an interrupt vector signal for indicating a storing destination of an interrupt processing program corresponding any of the plurality of interrupt causes; a section that outputs the interrupt signal and the interrupt vector signal to an interrupt process executing circuit; and a section that controls the interrupt signal and an output value of the interrupt vector signal in sync with an interrupt acceptance signal input from the interrupt process executing circuit, the interrupt acceptance signal representing a condition in which an interrupt process is acceptable.

Abstract: A device control apparatus includes a processor that operates according to software, a storage unit that stores privileged software which manages an interrupt to the processor from a device included in the device control apparatus, an OS storage unit that stores an Operation System for calling the privileged software from the storage unit when an interrupt from the device is detected during an execution of the software, a detecting unit that detects an interrupt to the Operation System from the device while the Operation System is operating on the processor, a judging unit that judges whether the Operation System has called the privileged software from the storage unit in a first predetermined time from detection of the interrupt to the Operation System from the device, and a resetting unit that resets the processor when the judging unit judges that the Operation System has not called the privileged software from the storage unit.

Abstract: Methods and arrangements for managing interrupts in a processing system are disclosed. The method can determine an indication of an interrupt request from a peripheral entity, identify the peripheral entity associated with the indication, count occurrences of the indications; and flag the peripheral entity in response to the counted occurrences. When the counted occurrences reach a predetermined number in the predetermined time interval, interrupts from the peripheral entity can be ignored or the entity can be identified as having possible operational problems.

Abstract: A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to the read-only portion of system memory. Upon receipt of an interrupt, each disabled logical processor branches to the hard coded interrupt service routine. The interrupt service routine can be written to read only memory because the context, current instruction, and return state of the disabled logical processor are known, and the disabled logical processor will not need to write to system memory during the execution of the interrupt service routine. Following the handling of the interrupt by another logical processor of the computer system, each disabled logical processor returns to the halt state.

Abstract: Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.

Abstract: Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

Abstract: A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with devices on a second bus and a memory to store data. A processor receives an interrupt signal from an expansion device on the expansion bus and generates an indicator of completion. The processor then inserts the indicator into a transaction queue after the set of data.

Abstract: A method for scheduling a plurality of virtual machines includes: determining a resource requirement (Xi) for each virtual machine (VM); determining an interrupt period (Yi) for each VM; and scheduling the plurality of VMs based, at least in part, on each respective Xi and Yi.

Abstract: A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU, wherein the return signal is a signal transmitted by a system chip in response to a triggering command transmitted to the system chip by the CPU. The blocking method includes detecting whether the CPU has transmitted the triggering command to the system chip, and detecting whether the system management interrupt signal is transmitted to the CPU. When the CPU has transmitted the triggering command to the system chip, and subsequently the system management interrupt signal has been transmitted to the CPU, it is judged that the system management interrupt signal is used to extract the values in registers of a computer system. Thereby the return signal transmitted to the CPU is blocked.

Abstract: A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.

Abstract: An interrupt controller is provided for processing interrupt requests in a system having a plurality of data processing units operable to service those interrupt requests, each interrupt request having an associated priority level. The interrupt controller comprises request logic operable to receive an indication of unserviced interrupt requests, to apply predetermined criteria to determine which of said plurality of data processing units are candidate data processing units for servicing at least one of said unserviced interrupt requests, and to issue a request signal to each said candidate data processing unit. Priority encoding logic is operable to determine a highest priority unserviced interrupt request based on the associated priority levels of the unserviced interrupt requests.

Abstract: There is provided an information processing apparatus in which a CPU and an audio processing unit are coupled by a bus. The audio processing unit includes a ring buffer that temporarily retains audio data, and performs an input/output process of the audio data. An interrupt signal generator generates a buffer empty signal, when the audio data is output from a buffer in the ring buffer and the buffer is empty, decimates the buffer empty signal in accordance with a sampling frequency of audio, and then feeds the interrupt signal that survives the decimation to the CPU. The CPU, upon receiving the buffer empty signal, issues a DMA transfer instruction for writing the audio data into the empty buffer in the ring buffer.

Abstract: Embodiments of the present invention provide techniques for protecting critical sections of code being executed in a lightweight kernel environment suited for use on a compute node of a parallel computing system. These techniques avoid the overhead associated with a full kernel mode implementation of a network layer, while also allowing network interrupts to be processed without corrupting shared memory state. In one embodiment, a system call may be used to disable interrupts upon entry to a routine configured to process an event associated with the interrupt.

Abstract: A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an interrupt. If one of the co-processors generated an interrupt, the ISR schedules the DPC for execution and disables sending of further interrupts from all of the co-processors. The DPC services pending interrupts from any of co-processors, then re-enables sending of interrupts from the co-processors.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated by a first plurality of interrupt sources, and a daisy chain interface operable to receive a daisy chain interrupt request output by a further interrupt controller based on a second plurality of interrupt requests generated by a second plurality of interrupt sources. The daisy chain interface includes a priority input operable to receive a daisy chain priority signal indicating a priority associated with the daisy chain interrupt request. Prioritization logic is operable to receive the daisy chain priority signal and to apply predetermined prioritisation criteria to determine the highest priority interrupt request selected from the daisy chain interrupt request and the interrupt request generated by the first plurality of interrupt sources.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: Method, system, apparatus and computer program product for interrupt scheduling in processing communication. In one embodiment the method includes: a sending computer program and a receiving computer program, coupling at least one registered signal identifier and a corresponding registered signal function with said receiving computer program; sending a communication including a request signal identifier by said sending computer program to said receiving computer program; receiving said communication sent at (B) by said receiving computer program; and performing said corresponding registered signal function without context switching of said receiving computer program if said request signal identifier received is coupled with said registered signal identifier. A system, router, computer program and computer program product are also disclosed.

Abstract: A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.

Abstract: Interrupt controlling circuit by which only a desired one(s) of plural interrupts may readily be masked. An interrupt factor controlling module 105 is provided for each interrupt. An interrupt group setting register 154 holds a group number of an interrupt signal INT entered to the interrupt factor controlling module 105. An interrupt group mask register 103 holds, for each group, information as to whether or not an interrupt belonging to a group in question is to be masked. In case an interrupt has occurred and the group of the group number of the interrupt, as held by the interrupt group setting register 154, is specified by the interrupt group mask register 103 as being to be masked, the interrupt mask circuit 152 masks the interrupt.

Abstract: An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver. In an embodiment, a non-volatile cache may be implemented by creating a device option read only memory (ROM), or modifying the associated computer basic input-output system (BIOS) to trap software interrupts associated with disk and other media access requests. Associated addresses, such as logical block addresses, can be stored in a log for data that is modified. The resulting log can be stored in a non-volatile medium, including the cache itself. If the available log space is not large enough to record all write activity prior to loading operating system drivers, a flag may be set to indicate the overrun condition.

Abstract: A technique for implementing a data processor to determine if an exception has been thrown. Specifically, the technique may be used in an interpretive environment where a table known as a bytecode (upcode) dispatch table is used. The dispatch table contains addresses for code that implements each bytecode. When the interpreter executes normally, these addresses point to the basic target machine code for executing each bytecode. However, when an Asynchrounously Interrupted Exception (AIE) is thrown, then the dispatch table is repopulated so that all byte codes point to routines that can handle the exception. These may point to a routine, such as an athrow, that has been extended to handle the special case of the AIE. Alternatively, the rewritten table can point to a routine that is specifically written to handle the firing of an AIE. The table contents are restored to their prior state once the exception handling is complete.

Abstract: According to an embodiment of the present invention, an interrupt control circuit that controls a plurality of interrupt requests for interrupt handling executed by a processor, includes: an interrupt control module unit as a detecting unit determining whether or not there is an interrupt request masked with interrupt handling executed by a processor during the interrupt handling; and an interrupt control circuit including a priority mask flag indicating whether or not there is the interrupt request. With such configuration, it is possible to simply determine whether or not there is another masked interrupt request.

Abstract: An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

Abstract: A system and method is provided to deliver messages to processors operating in a multi-processing environment. In a multi-processor environment, interrupts are managed by storing events in a queue that correspond to a particular support processor. A main processor decodes an interrupt and determines which support processor generated the interrupt. The main processor then determines whether a kernel or an application should process the interrupt. Interrupts such as page faults, segment faults, and alignment errors are handled by the kernel, while “informational” signals, such as stop and signal requests, halt requests, mailbox requests, and DMC tag complete requests are handled by the application. In addition, multiple identical events are maintained, and event data may be included in the interrupt using the invention described herein.

Abstract: An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.