Interrupt Prioritizing Patents (Class 710/264)
  • Patent number: 9965414
    Abstract: Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: May 8, 2018
    Assignee: INTEL CORPORATION
    Inventors: Karthikeyan Avudaiyappan, Aleksey Gorelov
  • Patent number: 9946668
    Abstract: In one embodiment, a method of implementing interrupt prioritization and preemption in a modeling environment is provided. The method may include obtaining a model including interrupt-generating components in the modeling environment, obtaining information describing interrupts in the model, and using the information describing the interrupts in the model to automatically generate code for prioritizing the interrupts in the modeling environment.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 17, 2018
    Assignee: The MathWorks, Inc.
    Inventors: Zijad Galijasevic, Antonin Ancelle, Murat Belge
  • Patent number: 9754240
    Abstract: One embodiment of the present invention provides a system for assisting a user in recovering from a task interruption. During operation, the system records the user's activity while the user is performing a task, and detects an interruption to the task. Upon the detection of the interruption, the system transfers to a storage the recorded user activities during a predetermined time period before the interruption. The system presents a visual representation of the recorded activities to the user, thereby assisting the user in recovering from the task interruption.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: September 5, 2017
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: James M. A. Begole, Oliver Brdiczka, Norman Makato Su
  • Patent number: 9678564
    Abstract: An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 13, 2017
    Assignee: NXP B.V.
    Inventors: Hamed Fatemi, Ajay Kapoor, Jose de Jesus Pineda de Gyvez, Juan Diego Echeverri Escobar
  • Patent number: 9678902
    Abstract: A concurrent flag set (changed from a first state to a second state) when generating a plurality of event signals at the same time from one circuit module that operates synchronously is prepared. When it is determined that the concurrent event signals are generated with reference to the concurrent flag, processing corresponding to the concurrent event signals is executed in order of priority, or requests for ordering or starting the processing are issued in order of priority.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: June 13, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Kenichi Nakashima
  • Patent number: 9678901
    Abstract: A technique for handling interrupts includes receiving an event notification message (ENM) that specifies an event target number (ETN) and a number of bits to ignore (NBI). The ETN identifies a specific virtual processor thread (VPT) and the NBI identifies the number of lower-order bits of the specific VPT to ignore when determining a group of VPTs that may be potentially interrupted. In response to two or more VPTs within the group of VPTs being dispatched and operating on an associated physical processor, whether multiple of the two or more VPTs do not have a pending interrupt is determined. In response to determining that multiple of the two or more VPTs do not have a pending interrupt, one of the two or more VPTs is selected to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more VPTs.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Florian A. Auernhammer, Stuart Z. Jacobs, Wade B. Ouren
  • Patent number: 9646719
    Abstract: A memory device includes first and second memory cell arrays, a first controller, and a second controller. The first controller controls the first memory cell array through first word line signals and first bit line signals to execute an operation corresponding to a command signal based on an address signal and a data signal. The second controller includes first and second mode registers. The second controller writes sampled values of the address signal and the command signal to the second memory cell array through access signals to form a log in response to stored values of the first and second mode registers or reads stored values of the second memory cell array as the data signal through the access signals.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kwang-Hyun Kim
  • Patent number: 9619231
    Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: April 11, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Michael I. Catherwood, Bryan Kris, David Mickey, Joseph Kanellopoulos
  • Patent number: 9575912
    Abstract: A service request interrupt router having Interrupt Control Units (ICUs); and an arbitration unit configured to be shared by the ICUs to arbitrate among Service Request Nodes (SRNs) that have respective service request interrupt signals and that are mapped to the ICUs, to determine for each of the ICUs which of the SRNs has a highest priority.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Frank Hellwig, Simon Cottam, Krishnapriya Chakiat Ramamoorthy
  • Patent number: 9542188
    Abstract: Provided is a hardware debugging apparatus and method for a software-pipelined program. The hardware debugging apparatus and method overcome a currency problem caused during hardware debugging in the software-pipelined program by guarding certain execution blocks and restarting the processing of the software-pipelined program.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 10, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Jun Shim, Yeon-Gon Cho
  • Patent number: 9460033
    Abstract: A method and a system embodying the method for interrupt collecting an reporting, comprising: storing for each of at least one interrupt a status indicator, an enable status, and an interrupt delivery information in a first structure; storing for each of the at least one interrupt at least an indicator of one or more entities to execute an interrupt handler routine in a second structure; and reporting one of the at least one interrupt to the one or more entities to execute an interrupt handler routine designated in accordance with the status indicator, the enable status, the interrupt delivery information, and the at least one indicator, is disclosed.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: October 4, 2016
    Assignee: Cavium, Inc.
    Inventors: Wilson Parkhurst Snyder, II, Lei Tian
  • Patent number: 9443109
    Abstract: A method of processing secure services is provided. The method is applied to a processing unit of a computing device to control the processing unit to process multiple secure services. The computing device includes a storage unit. The method includes: controlling a core of the processing unit to perform following steps in a secure mode: accessing the storage unit to obtain a first command that includes first secure service information, processing a first secure service associated with the first secure service information according to the first command, and accessing the storage unit to obtain a second command that includes second secure service information. During a period from a time point that the core accesses the storage unit to obtain the first to a time point that the core accesses the second command, the core is controlled to stay in the secure mode.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: September 13, 2016
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Chien-Hsing Huang, Hsin-Hsiung Tseng
  • Patent number: 9436739
    Abstract: Techniques for scheduling query execution are provided. In one embodiment, a computer system can receive a query to be executed and can assign a priority to the query. The computer system can further divide the query into a plurality of sub-queries and can assign a sub-priority to each sub-query, where the sub-priority is based on a resource consumption metric of the query. The computer system can then select, from a plurality of sub-query pools, a sub-query pool that includes sub-queries of queries that have the same priority as the query, and can add the plurality of sub-queries to the selected sub-query pool.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: September 6, 2016
    Assignee: VMware, Inc.
    Inventors: Zhenmin Li, Chengdu Huang, Jay A. Patel
  • Patent number: 9378048
    Abstract: Embodiments include receiving, at a microcontroller of a chip, a request to execute a first task having a first priority. Embodiments further include determining that a second task having a second priority is currently executing. Embodiments further include determining that the first priority is higher than the second priority. Embodiments further include determining whether a value in a register indicates that the second task can be interrupted. If it is determined that the second task can be interrupted, embodiments further include triggering execution of the second task. If it is determined that the second task cannot be interrupted, embodiments further include waiting for lapse of a time period since receipt of the request to execute the first task, and interrupting the second task upon detecting lapse of the time period, or detecting, prior to the lapse of the time period, that the second task can be interrupted.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bishop Brock, Tilman Gloekler, Andreas Koenig, Cedric Lichtenau, Preetham M. Lobo
  • Patent number: 9367498
    Abstract: A resource request arbitration device is connected with each of a plurality of masters, and arbitrates transfer requests issued by the masters. The resource request arbitration device includes a plurality of counters each indicating a slack time of a transfer request issued by a master corresponding to the counter, and compares counter values stored in the counters by a tournament method, and specifies a master that has issued a transfer request having the highest priority. The resource request arbitration device grants access permission to the specified master to permit the specified master to use a slave.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: June 14, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroshi Amano, Daisuke Iwahashi
  • Patent number: 9329880
    Abstract: Methods, systems and computer program products for fast interrupt register access in hypervisors are provided. A computer-implemented method may include maintaining a counter associated with a register to track set interrupt vectors in a virtual machine, updating the counter in response to an interrupt event in the virtual machine, and examining the counter to determine when an interrupt vector is set.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: May 3, 2016
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Ronen Hod
  • Patent number: 9292365
    Abstract: A computer system comprises a processor (106) configured to respond to events from a plurality of sources, and a prioritisation module (104) implemented in hardware and configured to prioritise the events for the processor. The prioritisation module comprises one or more decision modules (108) comprising multiple, prioritised inputs (110) configured to receive respective event flags relating to events from respective sources. The decision module stores a source identifier of the source corresponding to the highest priority asserted event flag. The processor can read the stored source identifier to identify the source of an event to which the processor is to respond. In this way, the decision as to which event a processor should respond to next is offloaded from the processor and implemented in hardware in the prioritisation module. This can reduce the workload of the processor and thereby result in a more efficient computer system.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 22, 2016
    Assignee: Imagination Technologies Limited
    Inventors: David William Knox, Adrian John Anderson
  • Patent number: 9235510
    Abstract: A computer includes a memory and a processor connected to the memory. The processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes to allow kernel mode access to user space virtual addresses for enhanced kernel mode memory capacity.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: January 12, 2016
    Assignee: MIPS Technologies, Inc.
    Inventors: Sanjay Patel, Chris Dearman, Ranganathan Sudhakar
  • Patent number: 9176770
    Abstract: Generally, this disclosure describes systems (and methods) for moderating interrupts in a virtualization environment. An overflow interrupt interval is defined. The overflow interrupt interval is used for triggering activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventors: YaoZu Dong, Yunhong Jiang, Kun Tian
  • Patent number: 9158569
    Abstract: A method includes loading a driver component on a hypervisor of a computing system including a Graphics Processing Unit (GPU) without hardware support for virtual interrupt delivery, and loading an instance of the driver component on each of a number of VMs consolidated on a computing platform of the computing system. The method also includes allocating a memory page associated with work completion by the each of the number of VMs thereto through a driver stack executing on the hypervisor, and sharing the memory page with the driver component executing on the hypervisor. Further, the method includes delivering, through the hypervisor, an interrupt from the GPU to an appropriate VM based on inspecting the memory page associated with the work completion by the each of the number of VMs.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: October 13, 2015
    Assignee: NVIDIA Corporation
    Inventors: Surath Raj Mitra, Neo Jia, Kirti Wankhede
  • Patent number: 9092307
    Abstract: Systems, methods, and other embodiments associated with adaptively determining a preventive maintenance schedule based on historical system operation are described. The prognostic parameter values are continuously partitioned into a number of operating states based on observed maintenance costs associated with the prognostic parameter values. The operating states range from absolutely healthy, one or more degrees of degradation, to fully degraded. A system cost function is used as the discriminant function. The system cost function is an expected maintenance cost when a given preventive maintenance (PM) schedule is adopted. The system cost function calculates the expected cost based on the observed cost of operation in each of the operating states and a probability of the computing system being in each of the operating states as determined by the PM schedule. The PM schedule that minimizes the cost function is determined to be the optimal PM schedule.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: July 28, 2015
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Yuri Langer, Aleksey Urmanov, Anton Bougaev
  • Patent number: 9032174
    Abstract: A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventor: Naoki Nishiguchi
  • Publication number: 20150127866
    Abstract: Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: Qualcomm Incorporated
    Inventors: Thomas ZENG, Samar Asbe, Azzedine Touzni
  • Publication number: 20150106543
    Abstract: In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal.
    Type: Application
    Filed: December 17, 2014
    Publication date: April 16, 2015
    Inventors: Stephan Schoenfeldt, Sergio Rossi, Fabio Parodi, Juergen Helmschmidt
  • Patent number: 8997099
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Publication number: 20150081943
    Abstract: Performing a checkpoint includes determining a checkpoint boundary of the checkpoint for a virtual machine, wherein the virtual machine has a first virtual processor, determining a scheduled hypervisor interrupt for the first virtual processor, and adjusting, by operation of one or more computer processors, the scheduled hypervisor interrupt to before or substantially at the checkpoint boundary.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: International Business Machines Corporation
    Inventor: David A. Larson
  • Publication number: 20150074310
    Abstract: Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode, the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode.
    Type: Application
    Filed: November 17, 2014
    Publication date: March 12, 2015
    Applicant: Marvell World Trade Ltd.
    Inventors: Timor KARDASHOV, Maxim Kovalenko, Arie Elias, Guy Ray
  • Patent number: 8943251
    Abstract: In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: January 27, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Stephan Schoenfeldt, Sergio Rossi, Fabio Parodi, Juergen Helmschmidt
  • Patent number: 8938737
    Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Andrew V. Anderson, Erik C. Cota-Robles
  • Patent number: 8924615
    Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 30, 2014
    Assignee: ARM Limited
    Inventors: Richard Roy Grisenthwaite, Anthony Jebson, Andrew Christopher Rose, Matthew Lucien Evans
  • Patent number: 8914566
    Abstract: A process for managing interrupts, which may be performed using electronic circuitry, includes: receiving interrupts bound for a processing device, where the interrupts are received from hardware devices that are configured to communicate with the processing device; generating data containing information corresponding to the interrupts; and sending the data to the processing device.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 16, 2014
    Assignee: Teradyne, Inc.
    Inventors: David Vandervalk, Lloyd K. Frick
  • Publication number: 20140359186
    Abstract: In accordance with an embodiment, a method of operating a processor includes operating in a first operating mode that prohibits access to a protected memory area, receiving a priority interrupt (PI) signal, operating in a second operating mode in response to receiving the PI signal, and executing a first routine by asserting a semi-privileged interrupt (SPI). Access to the protected memory area is permitted in the second operating mode, and the first routine operates in the second operating mode and is interruptible by the PI signal.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Inventors: Juergen Helmschmidt, Fabio Parodi, Stephan Schoenfeldt, Sergio Rossi
  • Publication number: 20140359185
    Abstract: An information handling system is provided. The information handling system includes an information handling device having one or more processors in communication with a network interface card. The network interface card includes one or more interfaces for receiving frames the information handling device is coupled to an external network device. The device also includes a memory that is in communication with the one or more processors and stores a classification matrix. The classification matrix is used to generate a current interrupt throttling rate from a plurality of candidate interrupt throttling rates that are applied to the received frames according to at least two properties of each frame of the received frames. A method for providing adaptive interrupt coalescing is also provided.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: Dell Products L.P.
    Inventors: Vinay Sawal, Vivek Dharmadhikari, Swaminathan Sundararaman
  • Patent number: 8856416
    Abstract: Numerous embodiments of a method and apparatus for processing latency sensitive electronic data with interrupt moderation are disclosed.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: October 7, 2014
    Assignee: Intel Corporation
    Inventors: Linden Minnick, Patrick L. Connor
  • Publication number: 20140281088
    Abstract: A method of scheduling and controlling asynchronous tasks to provide deterministic behavior in time-partitioned operating systems, such as an ARINC 653 partitioned operating environment. The asynchronous tasks are allocated CPU time in a deterministic but dynamically decreasing manner. In one embodiment, the asynchronous tasks may occur in any order within a major time frame (that is, their sequencing is not statically deterministic); however, the dynamic time allotment prevents any task from overrunning its allotment and prevents any task from interfering with other tasks (whether synchronous or asynchronous).
    Type: Application
    Filed: February 26, 2014
    Publication date: September 18, 2014
    Applicant: DornerWorks, Ltd.
    Inventors: Steven H. VanderLeest, Nathan C. Studer
  • Patent number: 8838912
    Abstract: A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 16, 2014
    Assignee: Broadcom Corporation
    Inventor: Christopher Gronlund
  • Patent number: 8832700
    Abstract: A central manager receives tick subscription requests from subscribers, including a requested period and an allowable variance. The manager selects a group period for a group of requests, based on requested period(s) and allowable variance(s). In some cases, the group period is not a divisor of every requested period but nonetheless provides at least one tick within the allowable variance of each requested period. Ticks may be issued by invoking a callback function. Ticks may be issued in a priority order based on the subscriber's category, e.g., whether it is a user-interface process. An application platform may send a tick subscription request on behalf of an application process, e.g., a mobile device platform may submit subscription requests for processes which execute on a mobile computing device. Tick subscription requests may be sent during application execution, e.g., while the application's user interface is being built or modified.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: September 9, 2014
    Assignee: Microsoft Corporation
    Inventors: Nimesh Amin, Alan Chun Tung Liu
  • Publication number: 20140237150
    Abstract: An electronic computer includes a processor that executes a thread and an interrupt handler, and monitors load of the processor; and an interrupt controller that is configured to determine a notification timing for an interrupt request to call the interrupt handler, the notification timing being determined based on the load and an effect of execution of the interrupt handler on user performance of the thread under execution by the processor; and notify the processor of the interrupt request, based on the notification timing. When the load is higher than a threshold, the interrupt controller sets the notification timing for an interrupt request that does not affect the user performance, to be later than the notification timing for an interrupt request that affects the user performance. Based on notification of the interrupt request, the processor calls and executes the interrupt handler that corresponds to the interrupt request.
    Type: Application
    Filed: April 30, 2014
    Publication date: August 21, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Koji KURIHARA, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Toshiya OTOMO
  • Patent number: 8813077
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Steven Bennett, Andrew Anderson, Gilbert Neiger, Scott Rodgers, Richard Uhlig, Lawrence Smith, III, Barry Huntley
  • Patent number: 8793423
    Abstract: Methods and apparatuses are provided for servicing an interrupt in a computer system. The method includes a device driver receiving an interrupt request. The device driver is responsive to the interrupt request to store interrupt data in a portion of the memory. The interrupt data includes identification of at least one processor of the plurality of processors capable of servicing the interrupt request; priority of the interrupt request; a thread context; and an address for instructions to service the interrupt request. The device driver then instructs the peripheral device to issue a memory write to the plurality of processors so that each may determine if it can use the thread context and the instructions to service the interrupt. A computer system is provided with the hardware needed to perform the method.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: July 29, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Xiao Gang Zheng
  • Publication number: 20140201412
    Abstract: A concurrent flag set (changed from a first state to a second state) when generating a plurality of event signals at the same time from one circuit module that operates synchronously is prepared. When it is determined that the concurrent event signals are generated with reference to the concurrent flag, processing corresponding to the concurrent event signals is executed in order of priority, or requests for ordering or starting the processing are issued in order of priority.
    Type: Application
    Filed: November 1, 2013
    Publication date: July 17, 2014
    Applicant: Renesas Electronics corporation
    Inventor: Kenichi Nakashima
  • Publication number: 20140181344
    Abstract: A controller for controlling interrupt processing in a multiple-interrupt system is provided. The controller includes multiple watchdog timers (WDTs), each provided for each of interrupt priorities. The controller includes interrupt priority selectors, each of which receives each interrupt request signal and outputs an activation signal to a corresponding WDT according to the priority of the interrupt request signal. The controller includes an interrupt processing circuit, which when a WDT has timed out, outputs, to a processor, an interrupt request signal having a priority one or more levels higher than the priority corresponding to the WDT. When multiple causes of interrupt are assigned to one of the interrupt priorities, the interrupt processing circuit gives priority to an interrupt request signal caused by the timeout of a WDT lower in priority level than the interrupt priority to detect that an abnormal operation has occurred in interrupt processing having the lower level priority.
    Type: Application
    Filed: July 25, 2012
    Publication date: June 26, 2014
    Applicant: International Business Machines Corporation
    Inventor: Toshiyuki Shiratori
  • Patent number: 8751717
    Abstract: An interrupt control apparatus and interrupt control method reduce situations in which the output of interrupt information is suspended and thus reduce stress caused in a user, without missing the appropriate output timing for interrupt information having a high priority level. A priority level setting unit raises the value of a priority level for an interrupt voice message during a period in which the interrupt voice message is being outputted, and a voice output control unit, when interrupts from two or more overlapping interrupt voice messages occurs, carries out control in accordance with priority levels set for each of the two or more interrupt voice messages so that the interrupt voice message having the higher priority level value is preferentially outputted.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: June 10, 2014
    Assignee: Alpine Electronics, Inc.
    Inventor: Takashi Miyake
  • Publication number: 20140143465
    Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.
    Type: Application
    Filed: February 20, 2013
    Publication date: May 22, 2014
    Applicant: International Business Machines Corporation
    Inventors: Bruce G. Mealey, Greg R. Mewhinney, Mysore S. Srinivas, Suresh E. Warrier
  • Patent number: 8732371
    Abstract: An application process operates at a privilege level lower than that of the kernel code of the operating system in which the process executes. When the application process requires performance of an operating system service for which the process lacks sufficient privileges to perform directly, rather than repeatedly requesting the service by issuing separate software interrupts, the process instead accumulates the data corresponding to the different service requests in a data container block and defers performance of the service. Whenever the process needs to complete the service, rather than deferring its performance, the process issues a single software interrupt that causes the kernel to use the accumulated data in the data container block to perform each of the N accumulated service requests. This reduces the number of interrupts that must be handled from N to one, thereby greatly reducing the overhead imposed by interrupt handling.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: May 20, 2014
    Assignee: Facebook, Inc.
    Inventor: Mateusz Berezecki
  • Publication number: 20140108690
    Abstract: The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: Wind River Systems, Inc.
    Inventors: Andrew GAIARSA, Maarten Koning, Felix Burton
  • Publication number: 20140047149
    Abstract: A method and circuit for a data processing system (20) provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers (27-29) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Inventors: Bryan D. Marietta, Gary L. Whisenhunt, Kumar K. Gala, David B. Kramer
  • Publication number: 20140047150
    Abstract: A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Inventors: Bryan D. Marietta, Gary L. Whisenhunt, Kumar K. Gala, David B. Kramer
  • Patent number: 8612659
    Abstract: Hardware interrupts are routed to one of multiple processors of a virtualized computer system based on priority values assigned to the codes being executed by the processors. Each processor dynamically updates a priority value associated with code being executed thereby, and when a hardware interrupt is generated, the hardware interrupt is routed to the processor that is executing a code with the lowest priority value to handle the hardware interrupt. As a result, routing of the interrupts can be biased away from processors that are executing high priority tasks or where context switch might be computationally expensive.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 17, 2013
    Assignee: VMware, Inc.
    Inventors: Benjamin C. Serebrin, Raviprasad Mummidi
  • Patent number: 8612661
    Abstract: An interrupt-notification control unit that receives interrupt requests from a plurality of interrupt dispatchers and sends the received interrupt requests together to a processor, where the interrupt-notification control unit determines a correlation among the interrupt requests to control a time to send the interrupt requests together to the processor.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: December 17, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takashi Shimada