Abstract: The technology disclosed herein enables an operating system kernel to schedule and perform load balancing of latency-sensitive tasks on processors that are otherwise excluded from a scope of load balancing performed by the kernel scheduler. An example method may include identifying, in an operating system of a computing device, one or more first tasks and one or more second tasks, where the second tasks are characterized by one or more latency constraints, identifying a first set of processors that are available for load balancing by a kernel scheduler of the operating system, scheduling execution of the first tasks on the first set of processors, identifying a second set of processors that are excluded from a scope of load balancing performed by the kernel scheduler, and scheduling execution of the second tasks on the second set of processors.

Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

Abstract: An updatable, single fault impervious integrated control and monitoring system (ICMS) for airfield avionics comprising at least a pair of I/O Processors connected in parallel by two separate networks to each of a) a plurality of workstations, preferably including a Master Workstation, and b) one or more Equipment I/O Interface backplanes; said one or more Equipment I/O Interface backplanes comprising one or more programmable Equipment I/O Interface circuit card plugged therein and being structured to be programmed to bidirectionally translate at least one of a plurality of signal types required for control and monitoring of avionic equipment and convert said at least one of a plurality of signal types to and from a common signal type usable by the I/O Processors. Methods of making and using the updatable, single fault impervious ICMS are also described.

Abstract: A computer system includes a processor and a persistent data storage. The persistent data storage includes flash-like storage media that includes multiple contiguous memory blocks. Each of the contiguous memory blocks includes multiple contiguous memory pages. Multiple file systems executable by the processor manage file data and the file system structure of files stored in the persistent data storage. A core executable by the processor provides a common internal model and software routines that provide common functionality to each of the file systems. Some of the file systems are executable to reconstruct the one or more file systems using a plurality of transaction records that may be executed a plurality of times and always render the same effect.

Abstract: A method includes defining a set of context types; defining a set of source types, each comprising context types; defining, for each source type, and for each context type included in the events from data sources having the source type, a context definition comprising a set of fields, in events from the data sources, that are associated with the context type; receiving a query comprising a first field value and a time period; retrieving a plurality of events that include the first field value and the time period; for each retrieved event, and for each context definition defined for a source type and a context type of a data source from which the retrieved event originated, determining field values of fields in the set of fields of the context definition; aggregating, for each context type, determined field values from the events; and generating an output.

Abstract: A method includes defining a set of context types; defining a set of source types, each comprising context types; defining, for each source type, and for each context type included in the events from data sources having the source type, a context definition comprising a set of fields, in events from the data sources, that are associated with the context type; receiving a query comprising a first field value and a time period; retrieving a plurality of events that include the first field value and the time period; for each retrieved event, and for each context definition defined for a source type and a context type of a data source from which the retrieved event originated, determining field values of fields in the set of fields of the context definition; aggregating, for each context type, determined field values from the events; and generating an output.

Abstract: This invention detects deviations from design without hindering the real-time nature of interrupt processing, and assists in analyzing the impact of faults caused by unintentional interrupt processing, with the goal of curbing erroneous detection. In order to resolve this problem, this vehicle control device comprises; a deviation determination unit 129 which determines if execution timing of an execution body has deviated from design settings, and transitions to a monitoring state; and a run-time verification unit 130 which verifies the impact of deviation at timing which differs from that of the interrupt processing.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Abstract: An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One of the processors receives from a bus attachment device an interrupt signal issued by a bus connected module. A logical processor ID resulting from a translation of an interrupt target ID provided with the interrupt signal is used to address the receiving processor directly. The receiving processor checks whether interrupt target ID identifies the receiving processor as a target processor of the interrupt signal. If the receiving processor is not the target processor, the interrupt signal is forwarded for handling by the guest operating system using broadcasting.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: A decoding apparatus has fetch circuitry, decode circuitry, and a decoded instruction cache. The decoded instruction cache comprises a plurality of cache blocks, where each cache block is arranged to store up to P decoded instructions from at least one fetch granule allocated to that cache block. When the corresponding decoded instruction for a required instruction is already stored in the decoded instruction cache, the decoded instruction is output in the stream of decoded instructions. Allocation circuitry is arranged, when a cache block is already allocated for existing decoded instructions from a particular fetch granule, and then additional decoded instructions from that particular fetch granule are subsequently produced by the decode circuitry due to a different path being taken through the fetch granule, to update the already allocated cache block to provide both the existing decoded instructions and the additional decoded instructions.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: A computer-implemented method according to one embodiment includes establishing a predetermined checkpoint and storing a log of duplicate read data in association with the predetermined checkpoint during a running of an application that is processing at least one data set, the duplicate read data including an image of all data retrieved from the at least one data set in response to a plurality of data reads made by the application before the predetermined checkpoint; identifying a first failure of the application; and restarting the application and performing a first replay of the application in response to the first failure.

Abstract: A computer system and a handling method thereof for an interrupt event are provided. The computer system includes an embedded controller, a system memory, and a processing unit. The embedded controller has an internal memory and triggers an interrupt event. The processing unit is coupled to the embedded controller and the system memory, and receives a notification of the interrupt event. In response to the interrupt event, the processing unit reads an event identifier corresponding to the interrupt event at a specific address section in the internal memory or maps the event identifier corresponding to the interrupt event at the specific address section in the internal memory of the embedded controller to the system memory. The processing unit notifies a hardware driver program corresponding to the event identifier. Accordingly, efficiency of handling the interrupt event is effectively enhanced.

Abstract: One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.

Abstract: One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.

Abstract: An interrupt controller, and method of operation of such an interrupt controller, are provided. The interrupt controller has an interrupt source interface for receiving interrupts from one or more interrupt sources, and a plurality of output interfaces, where each output interface is associated with a processing device that can execute an interrupt service routine to process an interrupt request issued to that processing device. The interrupt source interface has transaction generation circuitry to generate, for each received interrupt, an original transaction to represent the interrupt and a duplicate transaction to represent the interrupt. Buffer circuitry then buffers the original transaction and the duplicate transaction for each received interrupt, and selection circuitry is provided for selecting transactions from the buffer circuitry, and for routing each selected transaction for receipt by the output interface identified by an address portion of the selected transaction.

Abstract: A data packet processing method comprises: receiving data packet including a key message; analyzing the key message; determining whether the data packet is a high priority data packet or a normal data packet according to a result of analyzing the first key message of the data packet; and executing an Rx high priority interrupt in response to determining that the data packet is the high priority data packet. The Rx high priority interrupt is to immediately transmit an interrupt signal to interrupt receiving of the data packets.

Abstract: A semiconductor device including a first data terminal, a data output terminal, a control circuitry, first and second communication interfaces, and a bridge circuitry. The bridge circuitry is configured to operate a normal mode and a bridge mode. In the normal mode, the data output terminal is connected to the second communication interface circuitry, and in the bridge mode, the first data terminal is connected to the data output terminal in a bridge mode.

Abstract: The various embodiments of the present invention disclose a method for reducing interrupt latency in embedded systems. According to at least one example embodiment of the inventive concepts, the method for reducing interrupt latency in embedded systems, the method comprises steps of toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt, identifying, by the processor, a Task Control Block (TCB) of a preempted task on receiving the interrupt, enabling, by the processor, the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack, wherein a register set is stored in IRQ stack before processing the received interrupt.

Abstract: An online marketplace system generates an online marketplace for seller-financed transactions. The system includes a plurality of listings of transaction offerings that are available. The transaction offerings are listed by a plurality of users and are from a plurality of different categories of products and services. The transaction offerings include a plurality of transaction terms, including payment and seller-financing terms. A transaction engine facilitates the negotiation of transaction terms between users and the formation of agreement between users. Transaction coins are awarded during the successful performance of a transaction according to the agreed upon transaction terms. A reputation engine generates trust profiles and trust scores for users. The trust profiles and trust scores are used by parties to evaluate the trustworthiness of the other party. A user interface engine generates a user interface that includes listings from users and trust scores of those users.

Abstract: Systems and methods may provide for inserting one or more preemption instructions while compiling a computer program. The one or more preemption instructions being inserted within a preemption window in the computer program reduces the number of live registers at each preemption instruction position. Further, the preemption instruction instructs which registers are to be saved at a particular program position, typically the registers that are live at that program position. The compiled program may be run in an execution unit. A preemption request may be made to the execution unit and executed at a next available preemption instruction in the program being run in the execution unit.

Abstract: An integrated circuit is provided for obtaining interrupt performance metrics. The integrated circuit includes a microprocessor executing an interrupt service routing monitoring framework that includes an interrupt handler and an application programming interface. The interrupt handler executes in response to a trigger condition and obtains timing data that includes at least one sample of a value of a timing logic according to a sampling schedule. The API exposes interrupt configuration functionality for registering the interrupt handler with a supervisory program and for configuring the interrupt handler to obtain the timing data.

Abstract: A processing system is configured to dynamically carry out processes. A method for monitoring the processing system includes steps of determining a number of processes running on the processing system; of determining a maximum expected number of processes; of determining that more processes than expected are running; and of deactivating the processing system.

Abstract: A processing device receives a query comprising a first field value and a time period. The processing device performs a first search of a data store using the first field value to identify a first plurality of events having the time period and a field that comprises the first field value. The processing device determines, for one of the plurality of events, a second field value of a second field that is specified in a first context definition, the second field having an assigned field type. The processing device automatically performs a second search of the data store using the additional field value to identify a second plurality of events having the time period and the additional field value. Information from the first plurality of events and the second plurality of events is aggregated, and a response to the query is generated that comprises the aggregated information.

Abstract: Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.

Abstract: In one embodiment, a method of implementing interrupt prioritization and preemption in a modeling environment is provided. The method may include obtaining a model including interrupt-generating components in the modeling environment, obtaining information describing interrupts in the model, and using the information describing the interrupts in the model to automatically generate code for prioritizing the interrupts in the modeling environment.

Abstract: One embodiment of the present invention provides a system for assisting a user in recovering from a task interruption. During operation, the system records the user's activity while the user is performing a task, and detects an interruption to the task. Upon the detection of the interruption, the system transfers to a storage the recorded user activities during a predetermined time period before the interruption. The system presents a visual representation of the recorded activities to the user, thereby assisting the user in recovering from the task interruption.

Abstract: An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.

Abstract: A technique for handling interrupts includes receiving an event notification message (ENM) that specifies an event target number (ETN) and a number of bits to ignore (NBI). The ETN identifies a specific virtual processor thread (VPT) and the NBI identifies the number of lower-order bits of the specific VPT to ignore when determining a group of VPTs that may be potentially interrupted. In response to two or more VPTs within the group of VPTs being dispatched and operating on an associated physical processor, whether multiple of the two or more VPTs do not have a pending interrupt is determined. In response to determining that multiple of the two or more VPTs do not have a pending interrupt, one of the two or more VPTs is selected to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more VPTs.

Abstract: A concurrent flag set (changed from a first state to a second state) when generating a plurality of event signals at the same time from one circuit module that operates synchronously is prepared. When it is determined that the concurrent event signals are generated with reference to the concurrent flag, processing corresponding to the concurrent event signals is executed in order of priority, or requests for ordering or starting the processing are issued in order of priority.

Abstract: A memory device includes first and second memory cell arrays, a first controller, and a second controller. The first controller controls the first memory cell array through first word line signals and first bit line signals to execute an operation corresponding to a command signal based on an address signal and a data signal. The second controller includes first and second mode registers. The second controller writes sampled values of the address signal and the command signal to the second memory cell array through access signals to form a log in response to stored values of the first and second mode registers or reads stored values of the second memory cell array as the data signal through the access signals.

Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.

Abstract: A service request interrupt router having Interrupt Control Units (ICUs); and an arbitration unit configured to be shared by the ICUs to arbitrate among Service Request Nodes (SRNs) that have respective service request interrupt signals and that are mapped to the ICUs, to determine for each of the ICUs which of the SRNs has a highest priority.

Abstract: Provided is a hardware debugging apparatus and method for a software-pipelined program. The hardware debugging apparatus and method overcome a currency problem caused during hardware debugging in the software-pipelined program by guarding certain execution blocks and restarting the processing of the software-pipelined program.

Abstract: A method and a system embodying the method for interrupt collecting an reporting, comprising: storing for each of at least one interrupt a status indicator, an enable status, and an interrupt delivery information in a first structure; storing for each of the at least one interrupt at least an indicator of one or more entities to execute an interrupt handler routine in a second structure; and reporting one of the at least one interrupt to the one or more entities to execute an interrupt handler routine designated in accordance with the status indicator, the enable status, the interrupt delivery information, and the at least one indicator, is disclosed.

Abstract: A method of processing secure services is provided. The method is applied to a processing unit of a computing device to control the processing unit to process multiple secure services. The computing device includes a storage unit. The method includes: controlling a core of the processing unit to perform following steps in a secure mode: accessing the storage unit to obtain a first command that includes first secure service information, processing a first secure service associated with the first secure service information according to the first command, and accessing the storage unit to obtain a second command that includes second secure service information. During a period from a time point that the core accesses the storage unit to obtain the first to a time point that the core accesses the second command, the core is controlled to stay in the secure mode.

Abstract: Techniques for scheduling query execution are provided. In one embodiment, a computer system can receive a query to be executed and can assign a priority to the query. The computer system can further divide the query into a plurality of sub-queries and can assign a sub-priority to each sub-query, where the sub-priority is based on a resource consumption metric of the query. The computer system can then select, from a plurality of sub-query pools, a sub-query pool that includes sub-queries of queries that have the same priority as the query, and can add the plurality of sub-queries to the selected sub-query pool.

Abstract: Embodiments include receiving, at a microcontroller of a chip, a request to execute a first task having a first priority. Embodiments further include determining that a second task having a second priority is currently executing. Embodiments further include determining that the first priority is higher than the second priority. Embodiments further include determining whether a value in a register indicates that the second task can be interrupted. If it is determined that the second task can be interrupted, embodiments further include triggering execution of the second task. If it is determined that the second task cannot be interrupted, embodiments further include waiting for lapse of a time period since receipt of the request to execute the first task, and interrupting the second task upon detecting lapse of the time period, or detecting, prior to the lapse of the time period, that the second task can be interrupted.

Abstract: A resource request arbitration device is connected with each of a plurality of masters, and arbitrates transfer requests issued by the masters. The resource request arbitration device includes a plurality of counters each indicating a slack time of a transfer request issued by a master corresponding to the counter, and compares counter values stored in the counters by a tournament method, and specifies a master that has issued a transfer request having the highest priority. The resource request arbitration device grants access permission to the specified master to permit the specified master to use a slave.

Abstract: Methods, systems and computer program products for fast interrupt register access in hypervisors are provided. A computer-implemented method may include maintaining a counter associated with a register to track set interrupt vectors in a virtual machine, updating the counter in response to an interrupt event in the virtual machine, and examining the counter to determine when an interrupt vector is set.

Abstract: A computer system comprises a processor (106) configured to respond to events from a plurality of sources, and a prioritisation module (104) implemented in hardware and configured to prioritise the events for the processor. The prioritisation module comprises one or more decision modules (108) comprising multiple, prioritised inputs (110) configured to receive respective event flags relating to events from respective sources. The decision module stores a source identifier of the source corresponding to the highest priority asserted event flag. The processor can read the stored source identifier to identify the source of an event to which the processor is to respond. In this way, the decision as to which event a processor should respond to next is offloaded from the processor and implemented in hardware in the prioritisation module. This can reduce the workload of the processor and thereby result in a more efficient computer system.

Abstract: A computer includes a memory and a processor connected to the memory. The processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes to allow kernel mode access to user space virtual addresses for enhanced kernel mode memory capacity.

Abstract: Generally, this disclosure describes systems (and methods) for moderating interrupts in a virtualization environment. An overflow interrupt interval is defined. The overflow interrupt interval is used for triggering activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A method includes loading a driver component on a hypervisor of a computing system including a Graphics Processing Unit (GPU) without hardware support for virtual interrupt delivery, and loading an instance of the driver component on each of a number of VMs consolidated on a computing platform of the computing system. The method also includes allocating a memory page associated with work completion by the each of the number of VMs thereto through a driver stack executing on the hypervisor, and sharing the memory page with the driver component executing on the hypervisor. Further, the method includes delivering, through the hypervisor, an interrupt from the GPU to an appropriate VM based on inspecting the memory page associated with the work completion by the each of the number of VMs.

Abstract: Systems, methods, and other embodiments associated with adaptively determining a preventive maintenance schedule based on historical system operation are described. The prognostic parameter values are continuously partitioned into a number of operating states based on observed maintenance costs associated with the prognostic parameter values. The operating states range from absolutely healthy, one or more degrees of degradation, to fully degraded. A system cost function is used as the discriminant function. The system cost function is an expected maintenance cost when a given preventive maintenance (PM) schedule is adopted. The system cost function calculates the expected cost based on the observed cost of operation in each of the operating states and a probability of the computing system being in each of the operating states as determined by the PM schedule. The PM schedule that minimizes the cost function is determined to be the optimal PM schedule.

Abstract: A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.

Abstract: Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful.

Abstract: In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.