Abstract: A method for determining connection of an external device to a mobile communication terminal is provided. The method comprises detecting connection of an external device to a mobile communication terminal based on a signal generated by a first operation module of the mobile communication terminal; activating a connection interrupt routine, in response to the signal generated by the first operation module; controlling an active status of a second operation module by way of the first operation module to switch system operations from a first clock speed to a second clock speed; and establishing a signal transfer path between the mobile communication terminal and the external device.

Abstract: In an embodiment, a method is provided. The method of this embodiment provides determining a flow context associated with a receive packet; and if the flow context complies with a dynamic interrupt moderation policy having one or more rules, generating an interrupt to process the receive packet substantially independently of an interrupt generated in accordance with an interrupt coalescing scheme (“coalesced interrupt”). Other embodiments are disclosed and/or claimed.

Abstract: A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least important processor as far as task priority is concerned, it will then select and transfer its interrupt-related responsibilities (i.e., handling the interrupt and determining the next interrupt-handing processor) to the processor which is executing the least important task. The selected processor will then be designated for handling interrupts unless and until it undergoes a task switch and selects a different processor.

Abstract: An interrupt controller is provided for processing interrupt requests in a system having a plurality of data processing units operable to service those interrupt requests, each interrupt request having an associated priority level. The interrupt controller comprises request logic operable to receive an indication of unserviced interrupt requests, to apply predetermined criteria to determine which of said plurality of data processing units are candidate data processing units for servicing at least one of said unserviced interrupt requests, and to issue a request signal to each said candidate data processing unit. Priority encoding logic is operable to determine a highest priority unserviced interrupt request based on the associated priority levels of the unserviced interrupt requests.

Abstract: A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an interrupt. If one of the co-processors generated an interrupt, the ISR schedules the DPC for execution and disables sending of further interrupts from all of the co-processors. The DPC services pending interrupts from any of co-processors, then re-enables sending of interrupts from the co-processors.

Abstract: The present invention relates to handling interrupts in a multiprocessor system. An interrupt controller can receive input from a variety of interrupt sources, such as peripheral components and peripheral interfaces. Interrupts and their associated characteristics are identified. In one example, interrupt characteristics can be compared with characteristics of other interrupts handled by processors in the multiprocessor system. Interrupt characteristics are used to select a processor to run a routine for handling the associated interrupt. Intelligent selection provides efficient and effective distribution of interrupts.

Abstract: An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated by a first plurality of interrupt sources, and a daisy chain interface operable to receive a daisy chain interrupt request output by a further interrupt controller based on a second plurality of interrupt requests generated by a second plurality of interrupt sources. The daisy chain interface includes a priority input operable to receive a daisy chain priority signal indicating a priority associated with the daisy chain interrupt request. Prioritization logic is operable to receive the daisy chain priority signal and to apply predetermined prioritisation criteria to determine the highest priority interrupt request selected from the daisy chain interrupt request and the interrupt request generated by the first plurality of interrupt sources.

Abstract: An interrupt control circuit has a condition storage circuit for storing and outputting a reference time and an error detection circuit for outputting a signal indicating error detection when an interrupt request is not generated within a period from a predetermined time till the reference time elapses.

Abstract: This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card (1) and a host device (2) are connected with each other in accordance with a six-wire-system half-duplex protocol using four-bit parallel signals, a bus state signal, and a clock signal. When the state of the bus state signal is a state of accepting interruption, the memory card (1) sends an interrupt signal (INT) to four-bit parallel buses. Different elements of interruption are allocated to the respective bits of the four-bit parallel signals. That is, the bit at which the INT signal is sent varies depending on the content of interruption.

Abstract: In a multiprocessor system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment. The system and method can reschedule processes to run on the processor on which the assignment is made.

Abstract: Techniques are described herein that can be used to moderate the rate at which interrupts are emitted. A network component includes the capability to issue interrupts in response to receipt of network protocol units designated as regular and high priority or in response to other causes. High priority interrupts may be accumulated. A number of accumulated high priority interrupts may be decremented each time either a regular or high priority interrupt is transferred. Addition to a number of accumulated high priority interrupts may occur at a higher rate than a rate of availability of regular priority interrupts. A counter may be used to make regular priority interrupts available. The counter may be reset each time a high priority interrupt is provided.

Abstract: According to an embodiment of the present invention, an interrupt control circuit that controls a plurality of interrupt requests for interrupt handling executed by a processor, includes: an interrupt control module unit as a detecting unit determining whether or not there is an interrupt request masked with interrupt handling executed by a processor during the interrupt handling; and an interrupt control circuit including a priority mask flag indicating whether or not there is the interrupt request. With such configuration, it is possible to simply determine whether or not there is another masked interrupt request.

Abstract: An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

Abstract: An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.

Abstract: A method of testing the priority levels of the interrupt sources of a microprocessor having a number of interrupt sources which are each operable to execute an interrupt service routine when enabled, each interrupt source having a default priority level and an associated memory, the interrupt sources having a service order in which they are to be serviced, the method comprising the steps of: (a) sorting the interrupt sources in descending service order; (b) determining an array of priority levels to be assigned in a pre-arranged sequence to selections of interrupts in descending service order; (c) incrementing a global counter; (d) assigning the array of priority levels to a selected group of interrupts, the remainder of the interrupts assuming their pre-assigned priority level; (e) enabling all interrupts simultaneously except the interrupt source having the highest priority level so that the interrupt having the second highest priority level executes its interrupt service routine; (f) transferring the value

Abstract: An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.

Abstract: The method and apparatus feature detecting an interrupt service request; storing into an instruction cache interrupt service instructions in response to detecting the interrupt service request; and fetching instructions from the instruction cache into an instruction stream sequence, the instruction stream sequence including mainline program instructions and the interrupt service instructions resulting in allocating core processor bandwidth between the interrupt servicing and mainline program instructions while executing the instruction stream sequence based on an interrupt priority; and processing instructions within the instruction stream sequence including the mainline program instructions and the inserted interrupt servicing instructions. The method and apparatus further feature recycling of executed micro-ops and detecting imminent context switch for interrupt service instruction preparation.

Abstract: In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is configured to initiate the virtual interrupt responsive to the interrupt state. In another embodiment, a method comprises storing an interrupt state describing a virtual interrupt in a storage area allocated to a guest. A processor initiates the virtual interrupt subsequent to initiating execution of the guest, responsive to the interrupt state. In still another embodiment, a computer accessible medium stores a plurality of instructions comprising instructions which, when executed on a processor in response to a physical interrupt: determine a guest into which a virtual interrupt corresponding to the physical interrupt is to be injected; and store an interrupt state describing the virtual interrupt in a storage area allocated to the guest.

Abstract: An interrupt control apparatus comprising an interrupt vector register for holding address information corresponding to interrupt resources of a first type which are managed by an operating system and interrupt resources of a second type which are not managed by the operating system. Regarding an interrupt generated by an interrupt resource of the first type, the interrupt control apparatus in the present invention launches a common interrupt entry function which is subject to a scheduling process common to the interrupt resources of the first type, based on the address information of the interrupt vector register. At the same time, with regard to an interrupt generated by an interrupt resource of the second type, the interrupt control apparatus in the present invention launches an extended interrupt entry function which is not subject to the aforementioned scheduling process, based on the address information held in the interrupt vector register.

Abstract: A method is disclosed. The method includes receiving real-time data at a personal computer implementing a general purpose operating system, generating a real-time event at the personal computer and determining whether the real-time event has a higher priority than a first event being processed at the personal computer. If the real-time event has a higher priority than the first event being processed, the real-time event is processed.

Abstract: A computer system associated with a plurality of interrupt sources that produce interrupt signals may include interrupt signal processing blocks corresponding to the interrupt sources, respectively. Each of the interrupt processing blocks can include: a counter for generating an interrupt count value associated with the number of interrupt signals received from the corresponding interrupt source; a first register for storing the interrupt count value; a logic circuit for to generate an interrupt request signal according to the interrupt count value; and a second register for storing a service routine address associated with the interrupt source.

Abstract: An evaluation chip is disclosed whose interrupt priority order can be changed freely. A plurality of interrupt priority order determining circuits 20-1 to 2-4 perform a logical operation on a plurality of signals S11 to S14 used for interrupt priority order modifying control that are applied from outside and a plurality of interrupt signals S31-1 to S31-4, and output interrupt modifying signals S24-1 to S24-4. A plurality of interrupt modules 30-1 to 30-4 perform a logical AND operation on the plurality of signals S24-1 to S24-4 and a plurality of interrupt request signals S15-1 to S15-4 that are applied from outside, and output the signals S31-1 to S31-4. An address generating circuit 40 encodes the plurality of signals S31-1 to S31-4 and generates interrupt vector addresses 40. A microcomputer core 50 executes interrupt instructions that have been fetched from an external program memory 100, based on the addresses S40.

Abstract: A computer-implemented method for handling pending interrupt vectors of a pending interrupt list is disclosed. The method includes batch-reading the set of pending interrupt vectors into a working list of working interrupt vectors. The method also includes performing interrupt handling of the working interrupt vectors using an interrupt handling arrangement until the working list is empty. The interrupt handling process permits a first incoming interrupt vector that is received by the pending interrupt list after the batch reading to temporarily interrupt the performing interrupt handling of the working interrupt vectors and to be handled on a priority basis by the interrupt handling arrangement if a priority level of the first incoming interrupt vector is higher than a priority level of a first working interrupt vector being currently handled by the interrupt handling arrangement.

Abstract: A system including an event monitor monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to a centralized storage register. The address sequencer also transmits the addresses to the storage register. The event monitor compares new event data for each address with old event data stored by the event monitor. If a difference is detected, the event monitor sends a strobe signal to the storage register, which stores the event data reflecting the difference and the related address data. The strobe signal is also sent to a signaling device, which sends an interrupt signal to cause a microprocessor to read the event and address data from the storage register. Optionally, the signaling device does not send an interrupt signal until a threshold number of strobe signals have been received.

Abstract: A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task is interrupted with an asserted “fast” exception, the processor automatically diverts the exception to the dedicated exception registers using a dedicated vector. The dedicated vector and exception registers may be reserved for high priority, i.e., critical, exceptions. Because the exception registers are automatically activated for fast exceptions, there is no need to determine the priority of the exception. Further, high priority interrupts and high priority operating system calls (traps) may have different dedicated vectors and the set of exception registers may have a portion allocated for servicing interrupts and another portion allocated for servicing operating system calls. With the use of a dedicated vector or dedicated vectors, there is no need for software to decode the fast exception.

Abstract: A method for generating interrupt commands for a microprocessor system includes storing interrupts in a pending interrupts register, and storing priority values associated with the stored interrupts in a plurality of priority registers coupled to the pending interrupts register. A plurality of counters coupled in cascade to the plurality of priority registers are loaded with the stored priority values. The loaded priority values are incremented at predetermined intervals, and are compared for identifying the interrupt having a highest priority. The method further includes identifying a respective interrupt service routine to be executed based upon the interrupt having the highest priority.

Abstract: A digital signal processor operates in conjunction with a scheduler hardware module and a scheduler software module in executing a highest priority runnable event among a plurality of events. The scheduler hardware module communicates an interrupt request signal to the DSP that is indicative of any change in a highest priority runnable event. The scheduler software module is executed by the DSP in response to the interrupt request signal indicating a change in highest priority runnable event. An execution of the scheduler software module by the DSP implements one of a various modes of an interrupt request routine.

Abstract: A processor unit executes a failure detection program for a vehicle. The failure detection program includes a first failure detection process of a high priority level, a second failure detection process of a moderate priority level and a memory manipulation process of a low priority level. Each of the failure detection processes requests memory manipulation by generating an event as the need arises. When the memory manipulation process is activated, it performs the requested memory manipulation in the same order as the memory manipulation is requested so that execution of memory manipulation requested by one of the failure detection processes is not interrupted by execution of memory manipulation requested by the other of the failure detection processes. However, each of the failure detection processes itself can be executed interrupting the execution of memory manipulation process because of its higher priority level.

Abstract: A data processing system nested interrupt controller 24 responsive to priority level values 28, 30 associated with respective interrupt handling programs to control the execution of those interrupt handling programs. The priority level values have a first portion 28 which controls whether or not a pending interrupt handling program will pre-empt an already active interrupt handling program and a second portion 30 which controls which of a plurality of pending interrupt handling programs will be executed next when they share the same value for the first portion of their priority level value.

Abstract: A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

Abstract: An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO adapter. The firmware on the IO adapter may have a global variable that stores counters for PCI function registers. Each counter tracks the number of outstanding IOs of a corresponding PCI function register. The counter is incremented whenever a new IO is received and is decremented upon posting the completed message back to the OS. A timer interrupt is generated periodically so that an ISR may be periodically performed. In the ISR, the maximum value stored of each counter seen since last timer interrupt is analyzed. When the maximum value stored is greater than a predetermined threshold value, the interrupt coalescing is enabled.

Abstract: This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card (1) and a host device (2) are connected with each other in accordance with a six-wire-system half-duplex protocol using four-bit parallel signals, a bus state signal, and a clock signal. When the state of the bus state signal is a state of accepting interruption, the memory card (1) sends an interrupt signal (INT) to four-bit parallel buses. Different elements of interruption are allocated to the respective bits of the four-bit parallel signals. That is, the bit at which the INT signal is sent varies depending on the content of interruption.

Abstract: In an digital video disk player the timely acquisition of specific data types is particularly important during trick mode operation. During trick modes a controller can provide enhanced control capability by employing interrupt requests having priorities that differ from those used during normal play mode operation. A method for controlling a microcontroller in digital disk apparatus having at least two reproducing modes. The method comprises the steps of prioritizing the microcontroller interrupts during a first reproducing mode, and in a second reproducing mode reordering the microcontroller interrupt priorities.

Abstract: Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pending lower-priority interrupts and then resuming polling. The present invention does this by multi-threading SMI source handlers, using an idle thread, and using protocols for software-generated system management interrupts that insure that lower priority interrupts are serviced.

Abstract: A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.

Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Abstract: In a technique for testing processor interrupt logic, interrupts are sent to a microprocessor under test in a random order to test the processor interrupt logic of the microprocessor under test. The processor interrupt logic is considered to have failed the test if the microprocessor under test services a new interrupt having a priority level equal to or lower than a priority level of a previously received interrupt being serviced just prior to the receipt of the new interrupt. Furthermore, pseudo-masked interrupts are included in the interrupts being sent to the microprocessor under test. If a pseudo-masked interrupt is serviced by the microprocessor under test, the processor interrupt logic is considered to have failed the test.

Abstract: An integrated circuit (7A) for multitasking support for processing unit (1A) holds control variables for each task (or activity) to run on its associated processor (1A) and identifies the next task that should run. The circuit (7A) employs level-driven, clock free ripple logic and is configured as a two dimensional array of “tiles”, each tile being composed of simple logic gates and performing a dedicated function. The circuit has particular application to asynchronous multiple processor networks.

Abstract: The invention constitutes a unique hardware zero overhead interrupt and task change mechanism for the reduction or elimination of interrupt latency and task change processing overhead delays in computer architectures. Without loss of time, the system performs complete task state saving and restoration between one cycle and the next without software intervention. For each Central Processing Unit (1) register, the invention uses one or more auxiliary latches (3, 4) wherein one latch (3, 4) is used as the “running” latch and one of the auxiliary latches is attached to task storage memory. The invention swaps connections between alternate “running” registers and auxiliary registers while transferring other tasks to and from task storage memory (2). The invention provides a task linking system to allow the linking of tasks for the mandatory sequential execution of the linked tasks.

Abstract: An integrated circuit (7A) for multitasking support for processing unit (1A) holds control variables for each task (or activity) to run on its associated processor (1A) and identifies the next task that should run. The circuit (7A) employs level-driven, clock free ripple logic and is configured as a two dimensional array of “tiles”, each tile being composed of simple logic gates and performing a dedicated function. The circuit has particular application to asynchronous multiple processor networks.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: A computer-implemented method for monitoring a computer system when the computer system executes a user application using a production operating system (OS) is disclosed. The method includes providing a diagnostic monitor, the diagnostic monitor being configured to be capable of executing even if the OS kernel fails to execute, the diagnostic monitor having a monitor trap arrangement. If a trap is encountered during execution of the user application, the method includes ascertaining using the diagnostic monitor whether the trap is to be handled by the OS kernel or the diagnostic monitor. If the trap is to be handled by the OS kernel, the method includes passing the trap to the OS kernel for handling.

Abstract: One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.

Abstract: A method for the orderly execution of multiple tasks in a data processing system and a circuit for implementing that method include a plurality of task modules which construct bids based upon the order of the task and its priority. The highest priority highest order number tasks are switched to available system execution resources. The system permits the orderly execution of round-robin task sets in an environment of dynamically changing priorities. When a round-robin task set is interrupted, the system is able to return to the round-robin task set after execution of the higher priority task at the exact point the interruption occurred.

Abstract: A interrupt controller includes specialized interfaces and controls for ARM7TDMI-type microcontroller cores. Such sends interrupt vectors and IRQ or FIQ interrupt requests to the processor depending on particular interrupts received. Wherein, THUMB program execution is more economical with program code space, and an interrupt service routine preamble is coded in ARM program code to cause a switch to THUMB program execution. The interrupt service routine preamble is shared amongst all the interrupt service routines to further economize on program code space.

Abstract: An output cycle of a pulse string generated from a pulse generating section (2) is divided by a pulse dividing section (3) and a signal having a cycle which is plural times as great as the cycle of an output pulse is output from the pulse dividing section (3). This signal is input as an interruption request signal to a CPU (1). Consequently, the CPU (1) can execute an interruption processing in a cycle which is plural times as great as the cycle of the output pulse. By the interruption processing, the number of pulses to be output is controlled.

Abstract: A computer-implemented method for diagnosing the performance of a computer system using a diagnostic application. The method includes providing a diagnostic application and providing an operating system (OS) kernel, the diagnostic application being configured to execute under the OS kernel in the computer system, the OS kernel having a kernel trap arrangement. The method also includes providing a diagnostic monitor, the diagnostic monitor being configured to execute cooperatively with the OS kernel, the diagnostic monitor having a monitor trap arrangement. The method additionally includes ascertaining, using the diagnostic monitor, whether a trap encountered during execution of the diagnostic application is to be handled by the OS kernel or the diagnostic monitor. Furthermore, the method includes passing, if the trap is to be handled by the OS kernel, the trap to the OS kernel for handling.

Abstract: Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings and literal symbols, whereby bounds checking need not be performed on each symbol. Because literal symbols and small substrings of symbols form the majority of compressed data, the reduced checking significantly speeds up decoding on average. In one implementation, a fast LZ77 decoder that operates without bounds checking is used in a first phase until the end of the output buffer is neared at which time a second phase standard decoder, which performs bounds checks on each to ensure that the buffer does not overflow, is used. Normally the standard decoder decompresses only a small amount of data relative to the amount of data decompressed with the fast decoder, greatly improving decompression speed while not compromising safety.

Abstract: An information handling system is provided which includes a dynamic interrupt router for balancing interrupt assignments among a plurality of devices requesting interrupt assignments. The system balances interrupt assignments among both fixed devices mounted on the processor board and interrupt assignments to devices situated in expansion slots. When the system is populated with a large number of devices relative to the number of available interrupts, improved interrupt sharing is desirably achieved by causing a device which generates a large number of interrupt requests to share a common interrupt with a device which generates a lower number of interrupts.

Abstract: Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for handling such an interruption, and information regarding the interruption, are stored by the interruption handler in a storage accessible by the operating system. The interruption handler calls the operating system at a predetermined interruption handling point thereof, for the operating system to handle the interruption. The handler then determines whether the operating system handled the interruption according to the recommendation.