Abstract: The invention discloses a method for processing data in a memory for a computer system. The method comprises receiving a first interrupt for triggering a first job, backing up data corresponding to a second interrupt in the memory when a priority degree of the first interrupt is higher than a priority degree of the second interrupt corresponding to a second job currently being executed by the computer system, executing the first job corresponding to the first interrupt, and restoring the data corresponding to the second interrupt to the memory after the first job corresponding to the first interrupt is finished and continue executing the second job corresponding to the second interrupt.

Abstract: Various technologies and techniques are disclosed that provide fast context switching. One embodiment provides a method for a context switch comprising preloading a host virtual machine context in a first portion of a processor, operating a guest virtual machine in a second portion of the processor, writing parameters of the host virtual machine context to a memory location shared by the host virtual machine and the guest virtual machine, and operating the host virtual machine in the processor. In this manner, a fast context switch may be accomplished by preloading the new context in a virtual processor, thus reducing the delay to switch to the new context.

Abstract: An interrupt control apparatus includes: an interrupt request supply unit that supplies interrupt request information; a processing unit that performs interrupt processing based on the interrupt request information supplied by the interrupt request supply unit; and a time measuring unit that is used to measure an elapse of a predefined time period from a time point when the interrupt request supply unit starts to supply the interrupt request information, wherein: even if new interrupt cause information is stored during the time when the time measuring unit is measuring the elapse of the predefined time period, the interrupt request supply unit does not supply interrupt request information based on the new interrupt cause information to the processing unit; and after the elapsed time measured by the time measuring unit reaches the predefined time period, the interrupt request supply unit supplies the interrupt request information to the processing unit.

Abstract: Efficient techniques are described for identifying active interrupt requests to improve performance and reduce power requirements in a processor system. A method to identify active sampled interrupt requests begins with scanning groups of the sampled interrupt requests one group at a time to identify an active interrupt request in any scanned group. A group of interrupt requests is an M/R priority of N sampled interrupt requests, M is the number of priority levels, and R is a resource sharing factor. A group selection circuit is updated to a new group in response to having identified an active interrupt request to improve the latency in processing high priority interrupt requests. Also, groups having active interrupt requests may be identified by early detection or look ahead circuitry. The scanning of groups of interrupt requests may be stopped until the next interrupt request sample point has been reached to reduce power utilization.

Abstract: The present invention provides a data processing system having excellent immediacy of interrupting process. Different interrupt request signals are supplied from a circuit module which can be commonly used by a plurality of central processing units to a plurality of interrupt controllers assigned to central processing units, respectively. In response to the input interrupt request signal, each of the interrupt controllers notifies the corresponding central processing unit of an interrupt. The circuit module selects an interrupt controller for supplying an interrupt request signal from the plural interrupt controllers. For example, the circuit module identifies a central processing unit which instructed a start request and supplies an interrupt request signal to an interrupt controller corresponding to the central processing unit. The burden of the interrupting process of the single central processing unit can be lessened.

Abstract: A balancing process between I/O processor groups of a non-uniform multiprocessor system enables spreading of I/O workload across multiple I/O processor groups on a group base as soon as the I/O processor group with maximum group utilization reaches a certain high limit together with other processor groups being utilized significantly lower. The additional balancing is decreased step by step again when a certain low utilization limit is reached or the workload becomes more evenly balanced between the I/O processor groups. Checking if increase or decrease of the balancing is required is done periodically, but with low frequency to not affect overall performance. The checking and balancing happens asynchronously in predefined intervals. This solves the problem that with an increasing number of I/O processors the handling of initiatives leads to increased cache traffic and contention due to shared data structures, which slows down the I/O workload handling significantly.

Abstract: In a terminal apparatus, the central control section 1-10 judges whether or not a function accompanied with an audio output is in operation when a change in a folding opening/closing state of the terminal apparatus is detected by the folding open/close detecting section 1-6, and changes the priority of the function in operation while maintaining the audio output of the function in operation when the function accompanied with the audio output being in operation is judged. Then, the system controls a reporting method reporting that the interrupt event is generated, based on the priority of an operating state in the terminal apparatus and the priority of the changed interrupt event, when the interrupt event is generated.

Abstract: Systems and methods to manage memory are provided. A particular method may include initiating a memory compression operation. The method may further include initiating a first interrupt configured to affect a first process executing on a processor in response to a first detected memory level. A second initiated interrupt may be configured to affect the first process executing on the processor in response to a second detected memory level, and a third interrupt may be initiated to affect the first process executing on the processor in response to a third detected memory level. At least of the first, the second, and the third detected memory levels are affected by the memory compression operation.

Abstract: A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined based on pre-assigned levels of precedence of the respective master and slave devices. In one application, the invention is used to increase performance of IC devices employing an Advanced eXtensible Interface (AXI).

Abstract: An information processing apparatus connected with an IO device, having a processing unit, a channel device transferring data between the information processing apparatus and the IO device having a activation controller activating the channel device, a storage device having a predetermined area storing a result operation executed by the channel device, an interrupt controller controlling an interrupt required by the channel device to the processing unit, a channel device controller controlling the channel device and a driver writing a request for a first interrupt in the area of the storage device through the channel device and requiring the first interrupt to the processing unit by using the interrupt controller, wherein the processing unit executes driver commands for reading information stored in the area and requesting the first interrupt when the processing unit detects the request for the first interrupt.

Abstract: An application in a data processing system may automatically select when it needs determinism and when it does not. The ability to have the system automatically select when to use each allows optimum system performance while maintaining hard real-time requirements when needed.

Abstract: In an image processing apparatus which allows a plurality of users to reserve jobs, the convenience of each user is further improved while ensuring security of a job to be output by each user. In order to achieve this object, an MFP according to the invention is characterized by including a registration unit (204-1) which registers the use order of the image processing apparatus based on the acceptance order of the user identifier, a notification unit (204-4) which notifies a specific user of permission to use in accordance with the use order, an permission unit (204-2) which permits to execute a job when the user who has received notification instructs to execute a job, wherein when the user who has received notification does not instruct to execute a job for a predetermined period of time, the notification unit (204-4) notifies the next user in accordance with the use order.

Abstract: A system and a method for reducing interrupt latency is described. The system includes a first interrupt source configured to generate a first interrupt, a second interrupt source configured to generate a second interrupt, and a processor. The processor includes a shadow set that stores data used to service the first interrupt. The processor receives the second interrupt and receives a designation of the shadow set to service the second interrupt. The processor determines, based on a dedicated bit, whether the shadow set is used to service the first interrupt upon receiving the second interrupt.

Abstract: A method of managing the software architecture of a radio communication circuit is provided. The software architecture includes a radio communication software stack and at least one client application. The radio communication software stack includes a radio communication interrupt manager and at least one radio communication task. The client application includes at least one client task. The method includes interleaving, within the radio communication software stack, at least one client interrupt manager, included in the client application, and belonging to the group comprising: a first client interrupt manager of execution priority level that is higher than the at least one radio communication task and lower than the radio communication interrupt manager; and a second client interrupt manager of execution priority level that is higher than the at least one radio communication task and higher than the radio communication interrupt manager.

Abstract: A controller capable of inhibiting storage of prescribed information associated with a control operation when the control operation cannot be normally performed, and resuming the storage immediately after the control operation has again become able to be normally performed. The controller includes determining means for determining whether or not the control operation can be normally performed on the basis of a power level of electrical power supplied to the controller, write-inhibiting means for setting a storage area for storing the information to a write-inhibited area in cases where it is determined that the control operation cannot be normally performed, and releasing means for releasing, as an interrupt process higher in priority than any other process, the write inhibited area in cases where it is determined after the setting of the storage area to the write-inhibited area that the control operation can be normally performed.

Abstract: Techniques enable reducing a number of intercepts performed by a hypervisor by reducing a number of End Of Interrupt (EOI) messages sent from a virtual central processing unit (CPU) to a virtual advanced programmable interrupt controller (APIC). The EOI path of the guest operating system running on the virtual CPU is altered to leave a marker indicating that the EOI has occurred. At some later time the hypervisor inspects the marker and lazily updates the virtual APIC state.

Abstract: A method and system to improve the operations of an integrated non-transparent bridge device (NTB) that is coupled to another NTB device or Root Port device. The integrated NTB device has logic to maintain ordering of interrupts to be sent to the remote Root Port or NTB device. The integrated NTB device allocates a contiguous portion of the memory for both the primary Base Address Register 0 associated with the integrated NTB device and the secondary BAR0 associated with the remote NTB device. The integrated NTB device has logic to report the size of the primary BAR0 as the combined size of the primary BAR0 and the size of the secondary BAR0. The integrated NTB device facilitates the dynamic modification of a mapping of each bit of a doorbell register with a respective one of a plurality of interrupt vectors based on a mapping register.

Abstract: The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests. In accordance with an aspect of the invention, there is provided a method for verifying a priority of a winning service request node (SRN) established in an arbitration between a plurality of service request nodes (SRNs) performed by an interrupt controller, the method comprising: storing the priority of the winning SRN in the interrupt controller; encoding the priority of the winning SRN, wherein the encoding allows for error detection; transmitting the encoded priority from the winning SRN to the interrupt controller; and verifying the priority of the winning SRN by comparing the encoded priority transmitted by the winning SRN with the priority of the winning SRN established in the arbitration and stored in the interrupt controller.

Abstract: A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum pending priority value. This conditional avoidance of dispatching is preferably implemented by a virtual priority module within a binary translator in a virtualized computer system and relates to interrupts directed to a virtualized processor by a virtualized local APIC.

Abstract: In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.

Abstract: Techniques enable reducing a number of intercepts performed by a hypervisor by reducing a number of End Of Interrupt (EOI) messages sent from a virtual central processing unit (CPU) to a virtual advanced programmable interrupt controller (APIC). The EOI path of the guest operating system running on the virtual CPU is altered to leave a marker indicating that the EOI has occurred. At some later time the hypervisor inspects the marker and lazily updates the virtual APIC state.

Abstract: A method for handling an interrupt during testing of at least one logic block of a processor includes performing a test on at least one logic block of a processor; during the performing, receiving an interrupt; determining a progress status of the test in response to receiving the interrupt; and determining when the processor responds to an interrupt, wherein the determining when the processor responds to an interrupt is based on the progress of the test.

Abstract: Processor interrupt determination procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable by a computer to determine, based on a performance goal, which of a plurality of processors is to be targeted by a device that is to perform an input/output operation when an interrupt message is discovered that is from the device and that targets the determined processor. The interrupt message is communicated to the device to indicate availability of the determined processor for use by the device. When an interrupt message is discovered that is from the device and that targets an alternative processor near the determined processor when compared with other processors in the plurality of processors, the interrupt message that targets the alternative processor is communicated to the device to indicate availability of the alternative processor for use by the device.

Abstract: Technologies are generally described herein for handling interrupts within a multiprocessor computing system. Upon receiving an interrupt at the multiprocessor computing system, a priority level associated with an interrupt handler for the interrupt can be determined. Current task priority levels can be queried from one or more processors of the multiprocessor computing system. One of the processors can be assigned to execute the interrupt handler in response to the processor having a lowest current task priority level. Interrupt arbitration can schedule and communicate interrupt responses among processor cores in a multiprocessor computing system. Arbitration can query information about current task or thread priorities from a set of processor cores upon receiving an interrupt. The processor core that is currently idle or running the lowest priority task may be selected to service the interrupt.

Abstract: In a terminal apparatus, the central control section 1-10 judges whether or not a function accompanied with an audio output is in operation when a change in a folding opening/closing state of the terminal apparatus is detected by the folding open/close detecting section 1-6, and changes the priority of the function in operation while maintaining the audio output of the function in operation when the function accompanied with the audio output being in operation is judged. Then, the system controls a reporting method reporting that the interrupt event is generated, based on the priority of an operating state in the terminal apparatus and the priority of the changed interrupt event, when the interrupt event is generated.

Abstract: A system and method are provided that involve a host computing machine and an SR IOV storage adapter in which the host machine hosts a virtual machine having a guest operating system (guest) coupled for direct passthrough IOV data path and also hosts a virtualization intermediary; a guest operating system (guest) and a virtualization intermediary exchange information concerning IO completions through a shared memory space; the guest writes information to a shared memory space that is indicative of whether an IO completion queue has reached a fill level since the most recently dispatched interrupt at which it is unsafe to coalesce an interrupt; the virtualization intermediary writes information to the shared memory space that is indicative of the interrupt most recently delivered to the guest; the virtualization intermediary reads the information written by the guest to the shared memory space that is indicative of whether an IO completion queue has reached a fill level since the most recently dispatched inter

Abstract: Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode, the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode.

Abstract: A multi-processor system with a plurality of unit processors includes: a request accepting section for accepting a first request and a second request, wherein the first request is a request to execute a program that can be executed in any of said unit processors and the second request is a request to execute a program that can be executed only in a specified unit processor among said unit processors; and a unit processor allocating section for allocating the first request and the second request accepted by said request accepting section to said unit processors according to priority of the first request and the second request.

Abstract: A storage system including a queue corresponding to each priority level of command and an activation order control part. A command received from a host is accumulated in the queue corresponding to the specified priority. The activation order control part decides the number of activation object commands to be activated among accumulated commands, based on the priority corresponding to the queue. The activation order control part decides the activation order of the activation object commands, based on a activation object command number decided for each queue, so that the average value of logical response time of the activation object command may be shorter at the higher priority. The activation object command is activated in accordance with the decided activation order.

Abstract: A storage system has a single processor that operates in a multitasking operating system environment. An operation time manager adjusts the balance between processing time proportions for interrupt processing and task processing requested of the storage system internally and externally so that those processing time proportions become within respective predetermined ranges.

Abstract: In a terminal apparatus, the central control section 1-10 judges whether or not a function accompanied with an audio output is in operation when a change in a folding opening/closing state of the terminal apparatus is detected by the folding open/close detecting section 1-6, and changes the priority of the function in operation while maintaining the audio output of the function in operation when the function accompanied with the audio output being in operation is judged. Then, the system controls a reporting method reporting that the interrupt event is generated, based on the priority of an operating state in the terminal apparatus and the priority of the changed interrupt event, when the interrupt event is generated.

Abstract: A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

Abstract: A system including an event monitor for monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to a centralized storage register. The address sequencer also transmits the addresses to the storage register. The event monitor compares new event data for each address with old event data stored by the event monitor. If a difference is detected, the event monitor sends a strobe signal to the storage register, which stores the event data reflecting the difference and the related address data. The strobe signal is also sent to a signaling device, which sends an interrupt signal to cause a microprocessor to read the event and address data from the storage register. Optionally, the signaling device does not send an interrupt signal until a threshold number of strobe signals have been received.

Abstract: Briefly, techniques to manage interrupts and swaps of threads operating in critical region. In an embodiment, a thread is to be interrupted during a first critical region with an interrupt routine. The thread may be set to restart at a beginning of the first critical region in response to an indication that the thread is working in a critical region. Other embodiments are also claimed and disclosed.

Abstract: A method of determining request transmission priority subject to request source and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective source and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: A cache managing unit creates a list of elements corresponding to each data block arranged based on a priority of writing data blocks to a magnetic disk apparatus, and when a group of elements corresponding to data blocks to be written to the same magnetic disk apparatus exists, provides a link connecting elements at both ends of the group. A write control unit searches, upon selecting a data block for writing, elements belonging to the list in descending order of priority, and if a link is set at an element corresponding to a data block to be written to a magnetic disk that cannot perform a writing, follows the link to search a subsequent element.

Abstract: A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.

Abstract: When an interrupt event occurs, an interrupt request signal and interrupt data are output from an arbitrary peripheral module to an interrupt control circuit. The interrupt control circuit stores the received interrupt data in a register and performs a priority determination of the interrupt request signal. Subsequently, the interrupt control circuit transfers the determination result as an interrupt request signal via a dedicated wiring and the interrupt data of the register via a dedicated bus to the CPU, respectively. Upon reception of the interrupt request, the CPU reads a corresponding interrupt processing function from a ROM and performs the processing of the interrupt data based on the input interrupt request signal.

Abstract: A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message.

Abstract: A multiprocessor system, which improves processing efficiency of an entire system while concurrently securing appropriate interrupt responsivity according to interrupt priority, includes a plurality of processors each including a register, a plurality of I/O devices, and an interrupt generation device. A multiprocessor system interrupt control method includes: setting, for the register, interrupt permissibility indicating permissibility for an interrupt to be permitted by a corresponding processor; receiving an interrupt request from one of the I/O devices, using the interrupt generation device having a memory which holds the interrupt priority indicating the priority for the interrupt from each I/O device, and notifying the interrupt request from I/O device and the interrupt priority to the plurality of processors; and causing one of the processors that includes the register holding interrupt permissibility lower than the interrupt priority to accept the interrupt request.

Abstract: A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the

Abstract: A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.

Abstract: An interrupt-notification control unit that receives interrupt requests from a plurality of interrupt dispatchers and sends the received interrupt requests together to a processor, where the interrupt-notification control unit determines a correlation among the interrupt requests to control a time to send the interrupt requests together to the processor.

Abstract: A method for configuration of a program with a plurality of configuration variables to operate on a computer system that includes obtaining a plurality of priority semantics for the plurality of configuration variables, wherein the plurality of priority semantics are heterogeneous, assigning a value for each of the plurality of configuration variables based on the plurality of priority semantics, and configuring the program using the value to operate on the computer system.

Abstract: Technologies are described herein for allocating interrupts within a multiprocessor computing system. Information communicated to an interrupt controller module can support allocating interrupt response resources so as to maintain processor affinity for interrupt service routines. This affinity can support caching efficiency by executing a specific interrupt handler on a processor that previously executed that interrupt handler. The caching efficiency may be balanced against the benefits of assigning execution of the interrupt hander to another processor that is currently idle or currently processing a lower priority task.

Abstract: In process control based on partition setting which is a process corresponding to a plurality of operating systems (OSs), a configuration is implemented in which an interrupt request can be processed efficiently. In process control for switching processes which are based on the plurality of OSs, it is configured to set an interrupt processing partition as an interrupt processing execution period corresponding to an interrupt processing request so as to coincide with a pre-set partition switching timing. Further, a processing schedule is set, taking a maximum allowable delay time, a minimum allowable delay time into account. As a result of the present configuration, an increment in the number of partition switching processes can be kept to 1, and thus efficient data processing becomes possible.

Abstract: A method and apparatus is described herein for executing firmware tasks during OS runtime. A thread slices execution time among entries in a control structure, such as process control block (PCB), maintained by an OS kernel. An entry in the control structure includes a reference to a firmware task, such as a system management operation, a BIOS task, and/or and EFI task. Based on that entry, the thread allocates an amount of execution time either directly to the firmware task or to a kernel mode driver to perform the firmware task.

Abstract: A method for making it possible for a virtualization software (VMM) to generally identify a PCI function of an interrupt requester presupposing the existing I/O devices based on the PCI express is provided. An interrupt relay circuit is provided between an I/O device based on the PCI express and a PCI express bridge. The interrupt relay circuit receives and relays an interrupt transaction issued by the I/O device, and records whether there is an interrupt request in an interrupt indicator in association with an interrupt identifier. A VMM 114 uniquely identifies an I/O device of interrupt requester by referring to the interrupt indicator 134.

Abstract: An interrupt control apparatus that controls an interrupt process request caused by a predetermined interrupt factor is disclosed. The interrupt control apparatus includes: an obtaining unit configured to obtain an interrupt process request signal including an interrupt factor identifier associated with at least equal to or more than two interrupt factors; an interrupt process unit configured to execute an interrupt process requested by the interrupt process request signal; and a control unit configured to control the interrupt process unit so as not to execute interrupt processes caused by interrupt factors associated with the interrupt factor identifier until the interrupt process executed by the interrupt process unit ends.