Abstract: A flexible interrupt controller (28) that includes an interrupt force register (120) is presented. Hardware interrupts (102) that are presently asserted by their respective hardware sources are stored in an interrupt source register (110) included in the interrupt controller (28). An independent interrupt force register (120) stores currently pending software interrupts (104) which may be asserted through the execution of software routines by the central processing unit (CPU) (12) within the data processing system (10). In one embodiment, each bit location in the interrupt source register (110) has a corresponding bit location in the interrupt force register (120), and each bit in the interrupt force register (120) is logically OR-ed with the corresponding bit in the interrupt source register (110).

Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debuts monitor mechanism.

Abstract: In one embodiment, a processor is arranged to handle events. The events handled by the processor have an assigned priority. When a first event is serviced, a first priority mask is generated based on the assigned priority of the first event. The priority mask indicates a set of serviceable events and a set of non-serviceable events and may be written to a priority register. When a second event is received, the priority mask is used to determine whether the second event should preempt the first event and be immediately serviced.

Abstract: Methods and apparatus for enabling timeouts with arbitrary resolutions to be implemented are disclosed. According to one aspect of the present invention, a method for enabling a device driver to communicate with a processor in a computing system includes exchanging information between the device driver and a clock system, and exchanging information between the clock system and a cyclic system. Information is also exchanged between the cyclic system and the processor. Although the clock system indirectly exchanges information with the processor, the clock system does not directly exchange information with the processor. In one embodiment, the clock system includes a callout system and a system clock, and exchanging information between the device driver and the clock system includes exchanging information between the system clock and the callout system, and exchanging information between the callout system and the device driver.

Abstract: A system operable to perform scaleable arbitration and prioritization of multiple interrupts. The present invention presents a solution that is theoretically indefinitely scaleable to accommodate any number of interrupt sources. The invention provides for orthogonal scalability of interrupt sources—a feature absolutely non-existent in the prior art. The propagation time of an interrupt within the system is predictable and nearly independent of the number of priority levels or the number of interrupt sources. In addition, the invention presents a novel solution to support multiple interrupt sources having a common priority level. The solution is scaleable in two dimensions, namely, modularity in the number of interrupt sources that can be supported and scaleable in the number of priority levels that can be supported. The solution significantly reduces the deleterious effects of hardware latency in slowing interrupt processing.

Abstract: An integrated control system for a vehicle comprises a plurality of system device control units for controlling system devices in a vehicle, and a manager control unit for providing the system device control units with commands serving as operation directives of the system devices. A particular one of the system device control units has a hierarchical layer. If the predetermined operation should be carried out, the particular system device control unit issues a command to the particular system device as an independent operation directive for driving the particular system device to carry out the predetermined operation independently of an operation directive issued by the manager control unit.

Abstract: A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the microprocessor. The microprocessor has components for responding to interrupt requests by interrupting current processing and performing an interrupt service routine associated with the interrupt request. The interrupt controller receives interrupt requests directed to the microprocessor from the peripheral processing units and for prioritizes the interrupt requests on behalf of the microprocessor. By providing an interrupt controller for prioritizing interrupt requests on behalf of the microprocessor, the microprocessor therefore need not devote significant internal resources to prioritizing the interrupt request signals.

Abstract: An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated by a first plurality of interrupt sources, and a daisy chain interface operable to receive a daisy chain interrupt request output by a further interrupt controller based on a second plurality of interrupt requests generated by a second plurality of interrupt sources. The daisy chain interface includes a priority input operable to receive a daisy chain priority signal indicating a priority associated with the daisy chain interrupt request. Prioritization logic is operable to receive the daisy chain priority signal and to apply predetermined prioritisation criteria to determine the highest priority interrupt request selected from the daisy chain interrupt request and the interrupt request generated by the first plurality of interrupt sources.

Abstract: A method for achieving low overhead for operating system (“OS”) interrupts is described. In a preferred embodiment, when an interrupt occurs, a lightweight interrupt handler is used to acknowledge that the interrupt occurred, prevent the CPU and the OS from fully servicing the interrupt until a designated future time, set a CPU flag indicating that the interrupt has been received, and return from the lightweight interrupt handler. In this manner, the interrupt is partially acknowledged by the CPU and the OS, but the driver that caused the interrupt is still awaiting service. To achieve low latency, a heavyweight (“non-deferrable”) time-based interrupt that flushes all deferred interrupts is scheduled to occur within a specified time. At a later time, when drivers would normally be polled for work, the CPU flag is checked to see if there is interrupt work.

Abstract: A crossbar structure for use in a multi-processor computer system to connect a plurality of processors to at least one shared resource. The crossbar structure comprises for each processor, a storage location for receiving from a respective processor a memory address of a lock control structure associated with the shared resource. When the processor needs to acquire a lock thereto, the crossbar structure, on behalf of the processor, performs memory operations on the lock control structure at the address specified in the storage location in order to acquire the lock on behalf of the processor.

Abstract: An integrated circuit (1) includes a processing device (2), a program interface (4, 5) coupled to the processing device (2), a data interface (6, 7) coupled to the processing device. The program interface (4, 5) includes a first address bus (4) and a first data bus (5) and the data interface (6, 7) includes a second address bus (6) and a second data bus (7). The integrated circuit also includes address and data bus switching devices (18) and a control device (16). The address bus switching device (18) is coupled to the first and second address buses (4, 6) and adapted to be coupled to an external address bus (11) and the data bus switching device (18) is adapted to be coupled to an external data bus (12) and is coupled to the first and second data buses (5, 7). The control device (16) is coupled to the processing device (2), the address bus switching device (18) and the data bus switching device (18).

Abstract: An interrupt signal generating device comprises interrupt detection units (20) each adapted to output a detection signal (DET-1 to DET-n) in response to a respective input signal (IN-1 to IN-n) representing an interrupt event; and an interrupt handler unit (15). The interrupt handler has a plurality of input terminals for receiving the detection signals (DET-1 to DET-n) and a plurality of output terminals for outputting corresponding interrupt signals to a CPU, and signal distribution means (16) connecting said input terminals to said output terminals and establishing a predetermined but changeable assignment between the input and output terminals, wherein each of said input terminals is assigned to one of said outputs terminals such that an interrupt signal (INT-1 to INT-n) is output from this output terminal in response to a detection signal (DET-1 to DET-n) applied to the respective input terminal.

Abstract: A multi-function electronic card has a host interface, a multi-functional controller and a plurality of function devices. Each function device is connected to the host via the host interface by issuing an interrupt request to the multi-functional controller. The multi-functional controller has an interrupt queue and an interrupt status register, each bit of the interrupt status register corresponding to a function device. When a function device issues an interrupt request, an identification number of the function device is stored into the interrupt queue, and only when all the bits in the interrupt status register are zeros, a corresponding bit in the interrupt status register is set as 1 for issuing an interrupt request to the host. When the host has serviced the function device, the interrupt queue is updated and the interrupt status register is cleared.

Abstract: A single microprocessor (22) hard disk drive (10) having a shared buffer memory (40) for storing sector data as well as microprocessor variables and code includes a buffer manager (38) for arbitrating requests from various channels or clients for access to the shared buffer memory. The buffer manager arranges channels including a disk data channel (32, 140), a host interface channel (50, 140), and microprocessor channels (144, 148) into a round-robin circular priority queue, with the disk data channel normally assigned the highest priority for buffer access. A state machine carries out an arbitration cycle by sequentially servicing access requests pending within the queue. The state machine senses (139) a servo interrupt (SVOINT) to elevate the priority of any pending microprocessor access requests to the shared buffer, such that the requests are serviced and cleared rapidly to allow the servo interrupt servicing routine to start sooner.

Abstract: An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

Abstract: An access controller comprising plural access ports in which information associated with access from a CPU is stored for each access, and a bank management unit for managing use states of the plural access ports and informing the CPU of the use states. The CPU writes the information associated with the access on an unused one of the plural access ports on the basis of the use states provided by the bank management unit. Accordingly, the access controller which has a function of not accessing an erroneous address, suppresses the CPU processing load, and does not require a complicated description of firmware can be provided.

Abstract: Improved transmission speed of data between computer systems is achieved by utilizing highest priority interrupts assigned to non-communication devices to control communications. In particular, the normally highest priority timer interrupts are used to poll communication buffers to determine whether data needs to be sent or received with such polling replacing the use of the interrupts typically associated with communication devices.

Abstract: A multistage interrupt controller provides a multistage storage means that processes external interrupt signals, including a plurality of multistage interrupt reception registers that can receive and provide temporary storage for corresponding external interrupt signals, an interrupt priority determining circuit that can receive the external interrupt signals from the multistage interrupt reception registers, determine priorities of the external interrupt signals, and dispose of the external interrupt signals according to the priorities, and a logical operator that inverts signals generated by the corresponding multistage interrupt reception registers and provides a logical feedback signal to the multistage interrupt reception registers.

Abstract: Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer from a host adapter to a processor. The host adapter is coupled to one or more I/O devices over a bus. One or more I/O commands are received for transferring data between the processor and one or more I/O devices. Then, the contention for the bus among the I/O devices is monitored to determine how many devices are arbitrating for the bus.

Abstract: The operation processing apparatus comprises a trap selecting register which stores trap maps for selecting one operating system in which the operation processing apparatus is applied out of a plurality of operating systems, a read/write controller which selects data for selecting the operating system from the trap selecting register, and a trap type encoder which encodes a trap request from an execution unit such as an integer unit, into trap type code, according to the trap maps corresponding to the selection data.

Abstract: An apparatus and method for prioritizing interrupt requests in a RISC processor. By utilizing hardware to prioritize the requests, processor time is reduced. The acknowledge signal from a priority resolve circuit selects the given service routine entry to branch instruction generating circuit. A lower priority service routine can be interrupted by a higher priority request.

Abstract: A system and method for implementing a multi-level interrupt scheme in a computer system is provided. Bus devices and a bus controller may be coupled to a shared bus in a computer system. The bus may include an interrupt line for each bus device coupled to the bus. A bus device may be configured to convey an interrupt using its designated interrupt line. Each bus device may be configured to convey different types of interrupt signals on its interrupt line depending on an interrupt priority level of a given interrupt. The bus controller may be configured to receive interrupt signals from each bus device coupled to the bus and may arbitrate amongst the interrupt signals based on the interrupt priority level of each interrupt signal. The bus controller may grant the interrupt that corresponds to the highest priority level. If multiple interrupts correspond to the same highest priority level in a group of interrupts, then the bus controller may use any suitable arbitration scheme to grant an interrupt.

Abstract: The method and apparatus feature detecting and prioritizing one or more interrupt service requests; inserting interrupt servicing instructions responsive to the interrupt service request into an instruction queue mechanism; and processing the instructions within the instruction queue mechanism including the inserted interrupt servicing instructions. The instruction queue mechanism may include an instruction cache and an instruction fetch unit for fetching instructions from the instruction cache, wherein the processing includes decoding the instructions into micro-opcodes and executing the micro-opcodes in one or more out-of-order execution units. Further features include retiring the executed micro-opcodes including those micro-opcodes representing the inserted interrupt servicing instructions to the instruction cache. Preferably, the criteria for interrupting the core processor include the priority of the interrupts and the capacity of the processor to allocate bandwidth to interrupt servicing.

Abstract: A snapshot arbiter system for servicing multiple interrupt requests for a central processing unit (CPU) in a digital processor system, and for providing interrupts to the CPU corresponding to the interrupt requests. The system includes a synchronizer adapted to synchronize interrupt requests to a clock as they are received, and an interrupt masker adapted to receive a set of indicators identifying interrupt requests to be masked and to output active indicators that are a set of active interrupt request values corresponding to received interrupt requests that are not masked. Also included is a priority encoder block adapted to receive a set of priority values for respective interrupt requests and to provide as an output priority indicators that are a set of codes representing the priority values. A snapshot enable block is included, adapted to store enable indictors that are a set of bits representing currently enabled interrupt requests, and output those bits as enable bits.

Abstract: An interrupt controller may receive a plurality of interrupts from a variety of sources. An interrupt source register may be utilized to determine the interrupt source. A prioritizer may then determine the priority of each interrupt based on the source of the interrupt. The prioritizer then controls which interrupts are forwarded to a vector generator. The vector generator calculates a interrupt service routine vector of the highest priority interrupt for the core processor. As a result, the core processor receives only the highest priority interrupt vector. When the core processor has finished processing the highest priority interrupt, in some embodiments, the next highest priority interrupt vector is then forwarded for handling.

Abstract: A method and apparatus for reducing the disk drive data transfer interrupt service latency penalty is described. The method comprises beginning a data transfer between a disk drive and a host system, issuing an interrupt before the transfer is complete, and then completing the data transfer. This method may be implemented on a computer assembly that includes a processor, an input/output controller, and a scatter/gather list, which is stored in memory, that includes an entry that will cause the input/output controller to generate the interrupt.

Abstract: A method and apparatus for assigning interrupts to devices on a PCI bus in a computer system in which a plurality of address lines are channeled through a multiplexer to a PCI device on the PCI bus. The multiplexer enables the user to dynamically select which address line is routed to the IDSEL pin on the PCI device. According to the PCI specification, the address line connected to the IDSEL pin determines the Device ID for that PCI device. In turn, the Device ID establishes which of the four available interrupt INT# lines are assigned to that PCI device. Thus, the interrupt INT# line assignments can be dynamically controlled. Where desired, the user can force two PCI devices to share an interrupt line, or the user can force the devices to use separate interrupts.

Abstract: An interrupt handler is provided for a real-time control system that prevents interrupts which occur asynchronously with respect to control tasks from upsetting guarantees of timely execution of the control tasks. For interrupts associated with the communication of messages between portions of a control task over the distributed system, the interrupts are converted to proxy tasks that may be scheduled like any task in a multitasked-operated system. More generally, interrupts may be assigned to a predetermined interrupt window being a portion of the total processing bandwidth of the processor. In pre-allocating the processor bandwidth to the control tasks, this interrupt window may be subtracted out thereby guaranteeing adequate bandwidth for both interrupt processing and user tasks.

Abstract: An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

Abstract: Interrupt controller for controlling access by interrupt sources (11, 12, 13, 14) to a processor (100) and for controlling the associated branching of the current signal processing program (Rx) with a current priority (Px) in the processor. At the input end, the interrupt controller has a predetermined number of interrupt interfaces (21, 22, 23, 24) for the connection of the interrupt sources, each of the interrupt interfaces (21, 22, 23, 24) being assigned a priority value (Pi) and an address (Adi). A selection unit (30) determines from the activated interrupt interfaces the one with the highest priority value (Pmax).

Abstract: A method and apparatus are described which allow for greater control of interrupt generation to a processor or the like. In one embodiment, a priority selection device is provided which allows a processor or other devices to set the relative priorities among different interrupt requests. The priority information may be dynamic in that it can be modified at other times (e.g., based on the needs of the computer system). A priority resolution device and mask logic device determine which of the generated interrupt requests is of the highest priority and generates an interrupt to the processor to service that high-priority interrupt. In one embodiment, when a processor is servicing an interrupt and a higher priority interrupt is generated, the processor nests the servicing of the higher-priority interrupt in the servicing of the current interrupt.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. The node controller also implements an interrupt arbitration scheme designed to choose among multiple eligible interrupt distribution units without using dedicated sideband signals on the bus.

Abstract: An interrupt arbiter for a computer is described. The arbiter allocates interrupt resources to a plurality of devices within a computer such as a modem, keyboard, video controller, serial port, PCMCIA card, etc. As devices request interrupt resources, the inventive arbiter uses the Advanced Configuration and Power Interface (ACPI) to allocate interrupt resources based on the actual hardware topology of the computer. The improved arbiter allocates the interrupt resources by using configuration information that conforms to the ACPI specification and that describes the underlying connection circuitry, such as the multiplexors, routers, switches, etc., that communicates interrupt signals generated by the devices. In addition, the arbiter reconfigures connection circuitry of the computing system when necessary in order to improve the allocation of interrupt resources.

Abstract: A data processing system 2 for identifying the highest priority source signal from a plurality of signals each controlling the setting of a bit of a status word held within a status register 10 using programmable mask words. The mask words are used in a branch search strategy to successively narrow the possibilities for the highest priority bit at each search level until a single bit within the status word is identified corresponding to the highest priority interrupt signal. The programmable masks may be programmed for a particular configuration of the priorities of the respective bits within the status word. The branch search strategy provides a reduced maximum interrupt latency and improved predictability in the interrupt latency.

Abstract: A fiber optic channel loop provides a transmission path between a computer platform and a multiple number of peripheral devices. When any change occurs in the number of connected peripheral devices or their operation status, then Fiber Channel loop is interrupted so to disable ongoing Input/Output operations to a targeted peripheral device. When this interruption is sensed, the Master Control Program of the platform will institute corrective measures to re-originate any interrupted I/O operations.

Abstract: To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers or stacks processing data into a RAM. The processing data include a PSR (i.e., system register) value and a PC (i.e., program counter) value of the interrupt processing presently running in CPU. At the same time, the CPU sends a stack signal “STK” to the interrupt controller. In response to the stack signal “STK”, the interrupt controller temporarily transfers the interrupt mask level stored in the register into the RAM. When the CPU restarts the suspended interrupt processing, the CPU reads the PSR value and the PC value from the RAM while the CPU produces a return signal “RTN.” In response to the return signal “RTN”, the interrupt mask level is returned from the RAM to the register.

Abstract: A communications system includes a communications channel, a first processing unit; and interface unit, and an interrupt controller. The first processing unit is adapted to monitor the communications channel and provide a plurality of status bits. The interface unit includes an interrupt register. The interrupt controller is adapted to identify a plurality of interrupts in response to changes in the status bits. Each interrupt has a priority, and the interrupt controller is adapted to store selected interrupts in the interrupt register in an order determined by the priority of the interrupts. A method includes monitoring a communications channel. A plurality of status bits associated with the monitoring are provided. A plurality of interrupts are identified based on changes in the status bits, each interrupt having a priority. Selected interrupts are stored in an interrupt queue in an order determined by the priority of the interrupts.

Abstract: A computer system provides on chip at least one CPU connected to another module by an address and data path, the module generating interrupt request packets with a destination address, the CPU decoding the packet, identifying a priority for the interrupt request and selectively responding to the request.

Abstract: A microprocessor interrupt controller capable of receiving a plurality of interrupt requests organized in a plurality of groups, at least one of the groups including a plurality of interrupt requests, and providing the interrupts requests to a microprocessor. The controller includes a plurality of storage units corresponding to the plurality of groups and capable of storing one or more of the interrupt requests, by group, and providing the interrupt requests so stored as outputs, on a first in first out basis. At least one write arbiter unit is also included, associated with the storage unit for the at least one of the groups including a plurality of interrupt requests, for providing simultaneously pending interrupt requests of the at least one of the groups to the associated storage unit on a priority basis.

Abstract: When a request for reception of radio signals is delivered by wireless communication section 3, subordinate processing portion 12 fetches programs necessary for reception of radio data from external memory 2 and stores them into command cache memory 13. At this instant, to prevent data stored in command cache memory 13 from being altered by other interrupt requests, the system instructs interrupt controller 16 to mask all interrupt requests except urgent ones. Through this arrangement it is possible to reduce noise during execution of a specific processing, particularly during reception of data.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. Two sets of interrupt vectors are maintained. Interrupts vectors pertaining to interrupts originated by one set of interrupt sources (820, 821, 822) are stored in a DSP interrupt vector table (850) located in a memory circuit 801 that is private to the DSP. Interrupt vectors pertaining to interrupts originated by a host processor (810) are stored in a Host interrupt vector table (851) located in a dual ported communication memory circuit (802). The DSP executes interrupt service routines to service all of the interrupts, but the host can change the interrupt vectors for host initiated interrupts.

Abstract: Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against intrusions, yet is still accessible and/or alterable under certain defined conditions. In a non-volatile storage portion (48) of the data processing system (10), censorship information is stored to enable an access control mechanism. Access control information (42) to selectively disable the access control mechanism is programmably generated. Additional access control information (44) can be employed to reprogram a data processing system (10) containing access protected data in a secure mode.

Abstract: A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

Abstract: A method for arbitrating interrupt priorities among peripherals in a microprocessor-based system includes providing a bus which connects a central processing unit (CPU) to a plurality of peripherals and for transmitting a current priority value of the CPU thereon. The method further includes waiting-for activation of an interrupt line connecting all the peripherals and the CPU by the peripherals having a CPU interrupt request priority which is at least equal to, or greater than, the priority of the CPU. The highest priority among the CPU interrupt requests is determined, and the bus is provided with the value of the corresponding interrupt request.

Abstract: A system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is “soft” and freely defined. A system management interrupt (SMI) pin is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.

Abstract: A computer system is implemented according to the invention when priority information is included with a bus transaction. Instead of processing bus transactions on a first-come-first-served basis, a computer peripheral device can make decisions about the relative importance of a transaction and process the most important ones first. The priority scheme can be based upon the priority of the process that generates the transaction or on any other scheme. Included in the invention is logic to ensure that transactions of low relative priority do not get completely ignored during periods of high activity.

Abstract: A system operable to perform scaleable arbitration and prioritization of multiple interrupts. The present invention presents a solution that is theoretically indefinitely scaleable to accommodate any number of interrupt sources. The invention provides for orthogonal scalability of interrupt sources—a feature absolutely non-existent in the prior art. The propagation time of an interrupt within the system is predictable and nearly independent of the number of priority levels or the number of interrupt sources. In addition, the invention presents a novel solution to support multiple interrupt sources having a common priority level. The solution is scaleable in two dimensions, namely, modularity in the number of interrupt sources that can be supported and scaleable in the number of priority levels that can be supported. The solution significantly reduces the deleterious effects of hardware latency in slowing interrupt processing.

Abstract: An interrupt handling mechanism within a data processing system is used to assign interrupts among multiple interrupt presentation controllers while avoiding the use of a significant amount of signal lines. An interrupt input message from an interrupt source controller is input into an interrupt presentation controller. Fields are added to the interrupt input message to facilitate the assignment of the interrupt input message to an interrupt presentation controller. The input interrupt message is passed between the interrupt presentation controller in a sequential fashion such that the collection of controllers forms a logical ring. On the first circle of the ring, the priority of the processors capable of handling the interrupt is discovered. A second pass through the interrupt presentation controller is used to assign the first processor that is both capable of taking the interrupt and also has an equal or lower priority to that noted on the first pass as to best priority.

Abstract: A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

Abstract: One embodiment of the invention includes an apparatus, such as a bridge, for use in connection a with computer system. The apparatus includes remote priority capture logic to hold task priority data indicative of a task priority of each processor in the computer system that is available for lowest priority interrupt destination arbitration (LPIDA). The apparatus also includes lowest priority logic to perform the LPIDA to select processor in the computer system is to receive an interrupt message based on contents of the remote priority capture logic. Another embodiment of the invention includes a multi-processor system having processors and a processor bus coupled to the processors. The system includes remote priority capture logic to hold task priority data indicative of a task priority of the processors while they are available for lowest priority interrupt destination arbitration (LPIDA).