Abstract: Disclosed are an SPI controller and a method of operating an SPI controller. The SPI controller includes: an SPI clock signal generator; a register group configured to store SPI operating configuration of the SPI controller; SPI pins configured to connect to one or more SPI peripherals; and an input/output controller configured to perform data input or output between the SPI controller and the SPI peripherals according to the SPI clock signal and the SPI operating configuration; an SPI state machine configured to control a working state of the SPI controller. The SPI controller is electrically coupled via a bus to a CPU, a DMA controller, and a system memory located outside the SPI controller; and the input/output controller is further configured to receive an updated SPI operating configuration from the DMA controller and to update the updated SPI operating configuration into the register group between two consecutive SPI transmissions.

Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.

Abstract: In a solution for accessing a storage system, a client sends, based on an obtained start address that is of a queue of an NVMe storage device and to which an access request points and an obtained logical address that is of the NVMe storage device and to which the access request points, a remote direct memory access command to a storage node in which the NVMe storage device is located.

Abstract: Serial communication is performed at high speed by combining different communication methods. A communication device includes a communication unit configured to add, to a batch of data blocks including a serial signal group conforming to a serial peripheral interface (SPI) and transmitted from a master in synchronization with a clock, identification information for identifying the data blocks, and transmit the data blocks to a communication partner device within one frame period of a predetermined communication protocol, or add identification information for identifying each of a plurality of data blocks to the plurality of data blocks each including each part of the serial signal group, and transmit the data blocks to the communication partner device in a plurality of frame periods.

Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity.

Abstract: Provided are autonomous vehicles and methods of controlling autonomous vehicles through topological planning with bounds, including receiving map data and sensor data, expanding a topological tree by adding a plurality of nodes to represent a plurality of actions associated with the plurality of constraints, generating a bound based on a constraint in the geographic area, the bound associated with an action for navigating the autonomous vehicle relative to the at least one constraint, storing the bound in a central bound storage, linking a set of bounds of a tree node to the bound via a bound identifier, wherein the first bound is initially linked as an active bound, or alternatively, as an inactive bound after determining it is not the most restrictive bound at any sample index, and control the autonomous vehicle based on the topological tree, to navigate the plurality of constraints.

Abstract: The present invention provides a method for accessing a system memory, wherein the method includes the steps of: reading a descriptor from the system memory, where the descriptor includes a buffer start address field and a buffer size field, wherein the buffer start address field includes a start address of a buffer in the system memory, and the buffer size field indicates a size of the buffer; receiving multiple packets, and writing the multiple packets in to the buffer; modifying the descriptor according to the multiple packets stored in the buffer to generate a modified descriptor, wherein the modified descriptor only comprises information of part of the multiple packets or does not comprise information of any one of the multiple packets; and writing the modified descriptor into the system memory.

Abstract: A method for detecting a Direct Memory Access (DMA) memory address violation when testing PCIe devices is disclosed. The method for detecting a DMA memory address violation when testing PCIe devices applies to unintentional and intentional accesses of memory space outside of an area in memory specified by the device driver developed for the device.

Abstract: An example apparatus can receive a DMA request from a device, where the DMA request comprises an address and an ID of the device that uniquely identifies the device and wherein the device is a bus mastering device. The example apparatus can access a range of addresses using the ID of the device. An example apparatus can determine whether the address is in the range of addresses and can process the DMA request responsive to verifying that the address is in the range of addresses.

Abstract: A network adapter includes a network interface controller and a processor. The network interface controller is to communicate over a peripheral bus with a host, and over a network with a remote storage device. The processor is to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive first I/O transactions of the bus storage protocol from the host, via the exposed peripheral-bus device, and to complete the first I/O transactions in the remote storage device by (i) translating between the first I/O transactions and second I/O transactions of a network storage protocol, and (ii) executing the second I/O transactions in the remote storage device. For receiving and completing the first I/O transactions, the processor is to cause the network interface controller to transfer data directly between the remote storage device and a memory of the host using zero-copy.

Abstract: Provided are autonomous vehicles and methods of controlling autonomous vehicles through topological planning with bounds, including receiving map data and sensor data, expanding a topological tree by adding a plurality of nodes to represent a plurality of actions associated with the plurality of constraints, generating a bound based on a constraint in the geographic area, the bound associated with an action for navigating the autonomous vehicle relative to the at least one constraint, storing the bound in a central bound storage, linking a set of bounds of a tree node to the bound via a bound identifier, wherein the first bound is initially linked as an active bound, or alternatively, as an inactive bound after determining it is not the most restrictive bound at any sample index, and control the autonomous vehicle based on the topological tree, to navigate the plurality of constraints.

Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity.

Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

Abstract: Various embodiments enable a memory sub-system to perform a read operation based on consolidated memory region description data, which can be generated based on a memory region description data (e.g., SGL) provided by a host system for the read operation.

Abstract: In a solution for accessing a storage system, a client sends, based on an obtained start address that is of a queue of an NVMe storage device and to which an access request points and an obtained logical address that is of the NVMe storage device and to which the access request points, a remote direct memory access command to a storage node in which the NVMe storage device is located.

Abstract: A memory stores: a communication driver that is a software program which runs in an operating system and communicates with a host; and a storage service program that is a software program which runs on the operating system and controls retention of data by a storage apparatus as a storage. The processor is capable of configuring a plurality of queue pairs which transmit information in inter-process communication between the communication driver and the storage service program, and the processor further configures command distribution information which associates a queue pair and a logical volume with each other, specifies a queue pair corresponding to a logical volume that is an access destination of a command requested by the host, and enqueues a command request of the command to the specified queue pair.

Abstract: A method of accessing data by a storage device includes issuing a DMA read request of a host memory to a host. A host turnaround time is estimated. The host turnaround time is a time interval between when the DMA read request is issued and when an initial data packet of requested data from the host from the DMA read request arrives to the storage device. A data-path of the storage device is initialized to transfer the requested data of the DMA read request to a device buffer of the storage device. Initialization of the data-path is started after issuance of the DMA read request and is completed at an end of the estimated host turnaround time. The requested data is received from the host. The received requested data is transferred utilizing the data-path to the device buffer.

Abstract: Systems, apparatus and methods are described including operations for a dual mode GMM (Gaussian Mixture Model) scoring accelerator for both speech and video data.

Abstract: A first sequence of transaction control sets (TCSs) collectively describe a first data transfer by which first data is to be moved between a first peripheral and first and second memory buffers. A first portion of the first data is transferred between the first memory buffer and the first peripheral according to a first TCS in the first sequence. Subsequently, a second portion of the first data is transferred between the second memory buffer and the first peripheral according to a second TCS in the first sequence. An actual error detection code is determined based on the first and/or second portions of the first data or an address actually processed during execution of the first and/or second TCSs. An error is selectively flagged based on whether the actual error detection code is the same as an expected error detection code contained in a third TCS in the first sequence.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: A DMA-capable device of a virtualization host stores a DMA write record, indicating a portion of host memory that is targeted by a DMA write operation, in a write buffer accessible from a virtualization management component of the host. The virtualization management component uses the DMA write record to identify a portion of memory to be copied to a target location to save a representation of a state of a particular virtual machine instantiated at the host.

Abstract: A direct memory access control device for at least one computing unit includes a terminal for connecting the direct memory access control device to a bus system that connects the computing unit to a working memory, and processing circuitry configured to read out, from a source module connected to the bus system, first data of at least one information block stored at least temporarily in the source module, ascertain a target address in the working memory for the at least one information block as a function of the first data and of configuration information, and transmit the at least one information block from the source module to the target address using a direct memory access by the source module to the working memory.

Abstract: A data processing apparatus for accessing several system registers using a single command includes system registers and command generation circuitry capable of analysing a plurality of decoded system register access instructions, each specifying a system register identifier. In response to a predetermined condition, the command generation circuitry generates a single command to represent the plurality of decoded system register access instructions. The predetermined condition comprises a requirement that a total width of the system registers specified by the plurality of decoded system register access instructions is less than or equal to a predefined data processing width.

Abstract: A method for controlling access to a memory of a computer system configured with at least one logical partition may include receiving a first request to map a first page of the memory, the request identifying a first requester. A first logical partition associated with the first page may be determined. It may be determined that an attribute of the first logical partition limits access to individual pages of the first logical partition to a single requester, and that the first page is available to be mapped to a requester. The first page may be mapped to the first requester and a flag indicating that the first page is unavailable for an additional mapping may be set. The first request may be from a device driver on behalf of an input/output adapter, as the first requester, to use the first page in a direct memory access transfer.

Abstract: A video multiviewer system may include a video input/output (I/O) controller, a system memory, and a graphics processing unit (GPU) comprising a GPU memory. The system may further include a central processing unit (CPU) for operating the video I/O controller to transfer video data to the GPU memory via direct memory access (DMA) without being stored in the system memory, and a display for displaying multiple video windows based upon video data in the GPU memory.

Abstract: A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of PEs each having an associated PE number, where each of the plurality of PEs including one or more requesters each having a respective requester ID. An I/O host bridge, responsive to receiving an I/O message including a requester ID and an address, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index and validates the address by reference to the accessed entry in the second data structure. The I/O host bridge, responsive to successful validation, provides a service indicated by the I/O message.

Abstract: A data processing system includes a processor core, a system memory including a first data structure including entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers and a second data structure, and an input/output (I/O) subsystem including an I/O bridge and a plurality of PEs each including one or more requesters each having a respective requester ID. The I/O host bridge, responsive to receiving an I/O message including a requester ID, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index, where the second entry indicating one or more of the plurality of PEs affected by the message. The I/O host bridge services the I/O message with reference to each of the plurality of PEs indicated by the second entry.

Abstract: A semiconductor integrated circuit includes a bus, a memory connected to the bus, an arithmetic processing unit connected to the bus, a first DMA controller connected to the bus, and at least one functional block connected to the bus. The functional block includes a functional macro which is configured to perform a process that realizes a given function, a second DMA controller which is configured to control data transfer between the memory and the functional macro, and an access condition setting unit which is configured to set an access condition regarding the DMA transfer between the memory and the functional macro.

Abstract: A system and method for hosting one or more mobile devices on one or more servers in a cloud computing environment for testing mobile applications is provided. The system comprises client virtualization managers to collect and send information related to the mobile devices to the servers and mobile devices virtualization managers to receive and use the information to establish a connection with the client virtualization managers for accessing and hosting the mobile devices. Further, the system comprises a server application to facilitate testers to select a mobile device from a list of the hosted mobile devices and an automation tool interface handler to virtualize Universal Serial Bus (USB) port of local machines connected to the servers, connect the selected mobile device to the virtualized USB port of the local machines and facilitate testing of the mobile applications on the locally available mobile device by test automation tools.

Abstract: A communication channel controller includes a queue, a memory map, and a scheduler. The queue to store a first memory transfer request received at the communication channel controller. The memory map stores information to identify a memory address range to be associated with a memory. The scheduler to compare a source address of the first memory transfer in the queue to the memory address range in the memory map to determine whether the source address of the first memory transfer request targets the memory, and in response allocate the first memory transfer request to a first communication channel of a plurality of communication channels in response to the first communication channel having all of its outstanding memory transactions to a common source address bank and source address page as a source address bank and a source address page of the first memory transfer request.

Abstract: This invention discloses a method for data transfer between a host memory and a flash memory module through direct memory access (DMA), and a related data-transfer subsystem. In one embodiment, the subsystem comprises a DMA controller, a flash-memory controller, a data buffer for buffering data transferred between the DMA controller and the flash-memory controller, and a status-register group for storing a current status of the data buffer. The DMA controller and the flash-memory controller are configured such that both of them are allowed to update the current status and to detect a change of the current status during the data transfer, so that a substantial part of the data transfer's process is executed through direct interaction between the DMA controller and the flash-memory controller without involving a central processing unit. The subsystem may further comprise a command storing unit for storing command packages for execution by the flash-memory controller.

Abstract: A computing device may split a translation table used when performing a DMA operation into two different translation tables. To split the translation table, the computing device may update the registers in the IOMMU to include pointers to the two different translation tables. For example, the IOMMU may update one register to point to the same starting address as the original translation table but assign a shorter length (i.e., fewer entries) to that table. The extra entries may then be used to form the other translation table by adding a new pointer to one of the IOMMU registers. The two translation tables may be owned by the same service provider or two different service providers. Alternatively, the computing device may assign the two tables to the same service provider which in turn assigns the tables to respective client devices executed by the service provider.

Abstract: A computing device may split a translation table used when performing a DMA operation into two different translation tables. To split the translation table, the computing device may update the registers in the IOMMU to include pointers to the two different translation tables. For example, the IOMMU may update one register to point to the same starting address as the original translation table but assign a shorter length (i.e., fewer entries) to that table. The extra entries may then be used to form the other translation table by adding a new pointer to one of the IOMMU registers. The two translation tables may be owned by the same service provider or two different service providers. Alternatively, the computing device may assign the two tables to the same service provider which in turn assigns the tables to respective client devices executed by the service provider.

Abstract: APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams.

Abstract: A method and apparatus to interface a semiconductor storage device and a host in order to provide performance throttling of the semiconductor storage device. In the method, the semiconductor storage can receive a setting request command from the host. The semiconductor storage device sets a performance throttling parameter to a particular value in response to the setting request command. The semiconductor storage device can send to the host a setting response signal indicating completion of the setting of the performance throttling parameter.

Abstract: In one embodiment, a method includes storing, in a storage unit, a number of data transfer requests to issue for a data request signal. Data transfer requests are issued to a direct memory access (DMA) controller of a system for transfer of data to a buffer unit. The stored number of data transfer requests is determined. The issuance of data transfer requests are stopped when the stored number of data transfer requests is met.

Abstract: A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a part of the valid data may be transmitted to a plurality of member disks. That is, all of the valid data or the specific data may exist in the cache only, and may be deleted from the plurality of member disks. Accordingly, the plurality of member disks may secure more space, an internal copy overhead may be reduced, and more particularly, solid state disks may achieve better performance.

Abstract: Described herein are methods and systems for virtualization of a USB device to enable sharing of the USB device among a plurality of host processors in a multi-processor computing system. A USB virtualization unit for sharing of the USB device include a per-host register unit, each corresponding to a host processor includes one or more of a host register interface, host data interface, configuration registers, and host control registers, configured to receive simultaneous requests from one or more host processors from amongst the plurality of host processors for the USB device. The USB virtualization unit also includes a pre-fetch direct memory access (DMA) configured to pre-fetch DMA descriptors associated with the requests to store in a buffer. The USB virtualization unit further includes an endpoint specific switching decision logic (ESL) configured to schedule data access based on the DMA descriptors from the host processor's local memory corresponding to each request.

Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des

Abstract: A direct memory access circuit includes a buffer handler configured to store received data within a buffer in a buffer memory coupled to the direct memory access circuit and to generate a descriptor for the buffer. The direct memory access circuit further includes a descriptor handler coupled to the buffer handler. The descriptor handler is configured to determine a descriptor address for the descriptor and to store the descriptor at the determined address within a descriptor memory coupled to the direct memory access circuit.

Abstract: Data is written from a first domain to a FIFO memory buffer in a second domain. The first domain uses a first clock signal, the second domain uses a second clock signal and the memory buffer uses the first clock signal that is delivered alongside the data. The data is read from the memory buffer using the second clock signal. A read pointer is adjusted and synchronised with the delivered first clock signal. A token is generated using the delivered first clock signal, based on the read pointer. The token represents a capacity of the memory buffer having been made available. The token is passed to the first domain and synchronised with the first clock signal. The writing of data to the memory buffer is controlled based on a comparison between the synchronised token and a previously received token.

Abstract: SAS/SATA Store-Forward (SSSF) buffering enables SAS/SATA block storage devices capable of slower physical link rates to transfer data at a SAS topology data rate. 6 Gbps SAS and SATA disk drives can exchange data at 12 Gbps with 12 Gbps hosts through 12 Gbps SAS expanders employing an SSSF device. The SSSF device improves data transfer performance in the storage area network by optimizing host-side link utilization. The device includes a host-side interface communicating with the host at a host-side rate, a drive-side interface communicating with the target at a drive-side rate equal to or less than the host-side rate, a buffer receiving SAS frames or SATA FIS's, and control logic to control communication between the host-side interface and buffer at the host-side rate and between the drive-side interface and the buffer at the drive-side rate.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: Embodiments of the invention describe systems, apparatuses and methods that enable sharing Remote Direct Memory Access (RDMA) device hardware between a host and a peripheral device including a CPU and memory complex (alternatively referred to herein as a processor add-in card). Embodiments of the invention utilize interconnect hardware such as Peripheral Component Interconnect express (PCIe) hardware for peer-to-peer data transfers between processor add-in cards and RDMA devices. A host system may include modules or logic to map memory and registers to and/or from the RDMA device, thereby enabling I/O to be performed directly to and from user-mode applications on the processor add-in card, concurrently with host system I/O operations.

Abstract: A data processing device includes a memory, a direct memory access controller including a receiving module configured to receive data coming from outside the device and for writing the data in a main buffer memory of the memory, and a processing unit programmed to read and process data written by the receiving module in a work area of the main buffer memory. The main buffer memory is divided between a used space, where the receiving module is configured not to write, and free space, where the receiving module is configured to write. The processing unit is further programmed to define the work area, and the direct memory access controller includes a buffer memory manager configured to free data written in the main buffer memory, by defining a location of this data as a free space, only when this data is outside the work area.

Abstract: Described are techniques for providing access to storage devices. An I/O request directed to a storage device is sent over a network connection from a first computer system to a second computer system. The second computer system includes a simulated computing environment simulating aspects of the first computer system. The I/O request is received at the second computer system. The data storage system is connected to the second computer system over a first connection operating in accordance with a first protocol thereby providing the second computer system access to the storage device of the data storage system. The simulated computing environment of the second computer system may, for example, include emulation capabilities in accordance with the first protocol thereby allowing the second computer system to issue the first I/O request to the first storage device on behalf of the first computer system.

Abstract: A method and system for copying data within a guest using a direct memory access (DMA) engine. A computer system hosts a hypervisor and a guest. The hypervisor detects an inquiry of the guest about a DMA engine. In response to the inquiry, the hypervisor indicates to the guest that a DMA engine is available. The hypervisor then receives a DMA request from the guest, the DMA request indicating a source address and a target address for copying data. Both the source address and the target address are within an address space allocated to the guest. Based on one or more data transfer policies, the hypervisor determines whether to direct the DMA engine to copy the data for the guest.

Abstract: A data processing system includes an audio processor with a main memory for storing data, first and second buffers for temporarily storing the data to input/output an audio signal, and a data input/output (I/O) unit for outputting the stored data. A direct memory access (DMA) controller is provided for transmitting data between the main memory and the first and second buffers according to a DMA transmission process. If transmission of the data stored in the first buffer ends and an interrupt signal is thus generated, the DMA controller increases sizes of the first and second buffers during transmission of the data stored in the second buffer.

Abstract: In a network protocol processing system in which variables of each of TCP transmission processing and TCP reception processing depend on each other, asynchronous parallel processing is realized between a transmission processing block and a reception processing block for updated protocol processing. Specifically, the system includes a high priority queue for transferring control data to be processed with high priority, a low priority queue for control data other than the above control data, and priority control means for distributing the control data to two kinds of queues. When a request for session establishment and the session disconnection of a new TCP session is issued from an application during transmission of TCP data, data related with the session establishment and the session disconnection is notified preferentially through the high priority queue, and other control data is transferred through the low priority queue.

Abstract: An endpoint device (14) is registered in association with a host memory address in response to receipt of a request for a notification of a change in content state of the host memory address from the endpoint device (14). In response to a change in content state of the host memory address, a notification that the host memory address has changed content state is sent to the endpoint device (14). In response to receipt of the notification by the endpoint device (14), semantics associated with a change of content state of the host memory address by a data schema (42) is determined and an action is performed by the endpoint device (14) in accordance with the determined semantics.