Abstract: A communication system includes a master device and slave devices. Each slave device includes a request signal generation part configured to, when data to transmit is generated, generate a request signal indicating a transmission request to a master device; and a transmission part configured to transmit the request signal to the master device. The master device includes a request signal reception part configured to receive the request signals from the slave devices; a selection part acting configured to select one of the slave devices according to the request signals received by the reception part; a transmission part configured to transmit a signal indicating to allow data transmission to the slave device selected by the selection part; and a data reception part configured to receive data from the selected slave device.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core.

Abstract: Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

Abstract: Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core.

Abstract: Described herein are methods and systems for virtualization of a USB device to enable sharing of the USB device among a plurality of host processors in a multi-processor computing system. A USB virtualization unit for sharing of the USB device include a per-host register unit, each corresponding to a host processor includes one or more of a host register interface, host data interface, configuration registers, and host control registers, configured to receive simultaneous requests from one or more host processors from amongst the plurality of host processors for the USB device. The USB virtualization unit also includes a pre-fetch direct memory access (DMA) configured to pre-fetch DMA descriptors associated with the requests to store in a buffer. The USB virtualization unit further includes an endpoint specific switching decision logic (ESL) configured to schedule data access based on the DMA descriptors from the host processor's local memory corresponding to each request.

Abstract: A data transfer system includes: a processor; a main memory that is connected to the processor; a peripheral controller that is connected to the processor; and a peripheral device that is connected to the peripheral controller and includes a register set, wherein the peripheral device transfers data stored in the register set to a predetermined memory region of the main memory or the processor by a DMA (Direct Memory Access) transfer, and the processor reads out the data transferred to the memory region by the DMA transfer without accessing to the peripheral device.

Abstract: In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams.

Abstract: Methods and apparatus are provided for managing interrupts within a virtualizable communication device. Through virtualization, one port of the device may be able to support multiple hosts (e.g., computers) and multiple functions operating on each host. Any number of interrupt resources may be allocated to the supported functions, and may include receive/transmit DMAs, receive/transmit mailboxes, errors, and so on. Resources may migrate from one function to another, such as when a function requests additional resources. Each function's set of allocated resources is isolated from other functions' resources so that their interrupts may be managed and reported in a non-blocking manner. If an interrupt cannot be immediately reported to a destination host/function, the interrupt may be delayed, retried, cancelled or otherwise handled in a way that avoids blocking interrupts to other hosts and functions.

Abstract: A request to perform an operation, such as a remote direct memory access (RDMA) write operation or a send operation that writes to memory, is sent from a sending input/output (I/O) adapter (e.g., an RDMA-capable adapter) to a receiving I/O adapter. The receiving I/O adapter receives the request and initiates performance of the operation, but delays sending an acknowledgment for the operation. The acknowledgment is delayed until the operation is complete (i.e., until the memory is updated and the data is visible to the remote processor), as determined by a read operation initiated and performed by the receiving I/O adapter transparent to the sending I/O adapter.

Abstract: An I/O controller and method are provided. The I/O controller to which an I/O device can be connected, and instructs the I/O device to execute a process includes a descriptor transfer device that transfers a descriptor indicating contents of a process to be executed, and execution instruction unit that instructs the I/O device to execute the process, based on the descriptor transferred from the descriptor transfer device, wherein the descriptor transfer device includes a memory for storing the descriptor; descriptor reading unit that reads, according to an indication regarding a descriptor read source from a processor, an indicated descriptor from a main memory or said memory which stores the descriptor, and descriptor transfer unit that transfers the read descriptor to the execution instruction unit.

Abstract: An HBA driver manages a queue number for enqueuing and dequeuing data to an I/O queue by the main storage, and HBA-F/W manages a storage region at inside of HBA. The HBA driver reduces the number of access times by way of the PCIe bus by noticing an enqueued queue number or a dequeued queue number of an I/O queue to HBA-F/W by utilizing an MMIO area of the main storage in which a storage region on HBA is mapped.

Abstract: A technique for limiting an amount of write data stored in a cache memory includes determining a usable region of a non-volatile storage (NVS), determining an amount of write data in a current write request for the cache memory, and determining a failure boundary associated with the current write request. A count of the write data associated with the failure boundary is maintained. The current write request for the cache memory is rejected when a sum of the count of the write data associated with the failure boundary and the write data in the current write request exceeds a determined percentage of the usable region of the NVS.

Abstract: Embodiments of the invention describe systems, apparatuses and methods that enable sharing Remote Direct Memory Access (RDMA) device hardware between a host and a peripheral device including a CPU and memory complex (alternatively referred to herein as a processor add-in card). Embodiments of the invention utilize interconnect hardware such as Peripheral Component Interconnect express (PCIe) hardware for peer-to-peer data transfers between processor add-in cards and RDMA devices. A host system may include modules or logic to map memory and registers to and/or from the RDMA device, thereby enabling I/O to be performed directly to and from user-mode applications on the processor add-in card, concurrently with host system I/O operations.

Abstract: There is provided a data transmission apparatus, an image processing apparatus and a program, capable of preventing data from being transmitted to a destination to which the data should not be transmitted, in the case where there is a possibility that the data is forwarded to a destination other than the destination designated at the time of the transmission. When an address designated as a transmission destination has a possibility that data is forwarded to another address, such as an address of a mailing list, a forward destination information determining/acquiring unit acquires the information of the forward destination. When the forward destination includes the address that does not correspond to the transmission-permitted address held in a transmission-permitted address holder unit, an e-mail transmission canceling unit cancels the transmission to the address to which the transmission is not permitted.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: A method of address translation in a computing system providing direct memory access (DMA) by way of one or more remote memory management units (MMUs) is provided. The method comprises intercepting a request for a first DMA operation forwarded by a first device to a second device; and translating a guest address included in the request to a first address according to a mapping referencing a memory frame in a memory of the second device. A local MMU increments a first reference count indicating number of active DMA operations directed to the memory frame and a second reference count indicating number of remote MMUs that have mapped the memory frame.

Abstract: In one embodiment, a method includes storing, in a storage unit, a number of data transfer requests to issue for a data request signal. Data transfer requests are issued to a direct memory access (DMA) controller of a system for transfer of data to a buffer unit. The stored number of data transfer requests is determined. The issuance of data transfer requests are stopped when the stored number of data transfer requests is met.

Abstract: A method and system for accessing a computer system memory without processor intervention is disclosed. In one embodiment, the method includes initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface. The predetermined communication protocol enables an access operation to be performed on the first or second memory without intervention by the first or second processor. In one embodiment, the predetermined communication protocol utilizes a plurality of predefined packet types which are identified by a packet header decoder.

Abstract: Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core.

Abstract: Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

Abstract: Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.

Abstract: An apparatus includes a controller and a plurality of disk drives. The controller has a communication control unit for accepting a data input/output request, a disk controller unit for controlling a disk drive, and a cache memory for temporarily storing data transferred between the communication control unit and the disk controller unit. The plurality of disk drives has different communication interfaces and connected to the disk controller unit to communicate with the disk controller unit.

Abstract: In a disclosed example of a method, a requested value of a target register may be specified as a precondition to performing a requested read or write operation. The requested read or write operation may be generated by a requesting device, such as a processor, and sent over a bus to a peripheral device containing the target register. The target register may be polled internally to the peripheral device without generating additional bus traffic between the requesting device and the peripheral device. A ring topology may be used to internally poll the target register and to perform the requested read or write operation when the polled value of the target register equals the requested value.

Abstract: There is provided an apparatus including a plurality of modules. Each module includes a storage unit configured to store a waiting ID and a specific ID of the module, a communication unit configured to transmit and receive packets to and from a bus, and a processing unit configured to process data of a packet which includes a valid flag indicating that the packet is valid, wherein the communication unit takes in data held by a packet which has an ID that coincides with the waiting ID, and stores the processed data in a packet which includes the valid flag indicating invalid and an ID coincident with the specific ID, and transmits the packet.

Abstract: Device for real-time streaming to an array of solid state memory device sets, said device comprising receiving means for receiving data from data streams of individual data rate in parallel, an input cache for buffering received data, a bus system for transferring data from the input buffer to the solid state memory device sets, and a controller adapted for using a page-receiving-time t_r, a page-writing-time wrt_tm, the data amount p and the individual data rates for dynamically controlling the bus system such that data received from the first data stream is transferred to solid state memory device sets comprised in a first subset of said array of solid state memory device sets, only, and data received from the at least a second data stream is transferred to solid state memory device sets comprised in a different second subset of said array of solid state memory device sets, only.

Abstract: A system and method for a establishing a data connection between peripherals through a global computer network. The global computer network having at least two computerized addressable stations connected to a network, and each of the stations including at least one input and at least one output. A computerized server with a storage assembly with software that includes sufficient data and instructions to communicate with the stations to keep a database with information of the station's peripheral resources updated. Each station includes a service software that initiates upon booting the station and keeps track of the peripheral resources and assigned address (ex. IP address) for periodically updating the server's database with changes. Users with friendly interfaces have access to the subscribed stations and their resources as requested and target stations.

Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

Abstract: Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A system including a server apparatus executes an application program and a client apparatus enabling a user to utilize the application program by communicating with the server apparatus based on an instruction of the user. The server apparatus includes: an output detection section for detecting output-processing which is processing of outputting data from the application program into a shared area; and an output control section for storing instruction information in the shares area, instead of storing the output data outputted from the application program therein, in response to the detection of the output-processing, the instruction information specifying an acquisition method by which an authorized client apparatus acquires the output data.

Abstract: A command portal enables a host system to send non-standard or “vendor-specific” storage subsystem commands to a storage subsystem using an operating system (OS) device driver that does not support or recognize such non-standard commands. The architecture thereby reduces or eliminates the need to develop custom device drivers that support the storage subsystem's non-standard commands. To execute non-standard commands using the command portal, the host system embeds the non-standard commands in blocks of write data, and writes these data blocks to the storage subsystem using standard write commands supported by standard OS device drivers. The storage subsystem extracts and executes the non-standard commands. The non-standard commands may alternatively be implied by the particular target addresses used. The host system may retrieve execution results of the non-standard commands using standard read commands.

Abstract: A data transfer control device that selects one of a plurality of DMA channels and transfers data to or from memory includes a request holding section configured to hold a certain number of data transfer requests of the plurality of DMA channels and a request rearranging section configured to select and rearrange the data transfer requests that are held in a basic transfer order so that the data transfer requests of each of the plurality of DMA channels are successively outputted for a number of successive transfers set in advance.

Abstract: Embodiments are directed towards employing a plurality of single use passwords to provide phishing detection and user authentication. A user receives a plurality of single use passwords that expire within a defined time period after having been sent to a registered device. During a login attempt, the user enters a user name and a requested one of the passwords, which once entered expires. If valid, the user then enters a portion of another password to complete a displayed portion of a password, and a specified other one of passwords. If the displayed portion of the other passwords does not match any portion of one of passwords, then the user may detect a phishing attempt and terminate the login. If the user correctly the password data, the user may then access secured data. Each new login request requires a different set of passwords to be used.

Abstract: Software fault isolation methods using byte-granularity memory protection are described. In an embodiment, untrusted drivers or other extensions to a software system are run in a separate domain from the host portion of the software system, but share the same address space as the host portion. Calls between domains are mediated using an interposition library and access control data is maintained for substantially each byte of relevant virtual address space. Instrumentation added to the untrusted extension at compile-time, before load-time, or at runtime and added by the interposition library enforces the isolation between domains, for example by adding access right checks before any writes or indirect calls and by redirecting function calls to call wrappers in the interposition library. The instrumentation also updates the access control data to grant and revoke access rights on a fine granularity according to the semantics of the operation being invoked.

Abstract: Disclosed herein are techniques to manage access to a memory using a buffer construct that includes state information associated with a region of the memory. The disclosed techniques facilitate access to the region of memory through a direct memory access operation while the state information of the buffer construct is in a first state. The state information can be transitioned to a second state in response to a first instruction. The disclosed techniques also facilitate access to the region of memory through a cache operation while the state information of the buffer construct is in the second state is disclosed. The state information can be transitioned to the first state in response to a second instruction.

Abstract: A DMA transfer control device comprises: a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits that control the DMA arbiter; a judgment unit and a transfer time calculation unit that calculates a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter that times the judgment time at a unit time interval, and a comparator that compares the judgment time at which a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter when an output of the comparator indicates that the judgment time is not earlier than the DMA transfer scheduled time. The efficiency of data transfer by dynamically controlling DMA transfer is performed.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: Methods and apparatus for improved performance in communications with a SATA target device. Features and aspects hereof provide for continuing DMA transfers from a storage controller (e.g., a SATA host or a SAS/STP initiator) to a SATA target device without regard to receipt of DMA ACTIVATE Frame Information Structures (FIS). Logic to implement these features may be provided by bridge logic within an enhanced SAS expander coupled with an enhanced SAS/STP initiator or may be provided by suitable logic in an enhanced SATA host coupled directly with an enhanced SATA target device. By continuing DMA transfer of data from the initiator/host to the SATA target device without regard to receipt of a DMA ACTIVATE FIS, more of the available bandwidth of the SAS/SATA communication link may be utilized. Other standard features of the SAS/SATA protocols provide for flow control to prevent overrun of the SATA target device's buffers.

Abstract: In a system where a first storage system and a second storage system are connected to a third storage system, when the first storage system virtualizes and provides a device in the third storage system as a device in its own storage system, update data stored in a cache in the first storage system is written into the device of the third storage system to be reflected, attributes of the device are transferred to the second storage system, and the second storage system virtualizes the device of the third storage system as a device of its own storage system.

Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers by virtualizing DMA transfer requests into available DMA channel identifiers using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once an input value associated with the DMA transfer request is mapped to the selected DMA channel identifier, the DMA transfer is performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfer. When there is a request to wait for completion of the data transfer, the same input value is used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.

Abstract: A direct memory access controller including: a transfer module that transfers data from several data sources to at least one addressee for these data, through several buffer memories each including a predetermined number of successive elementary memory locations; a read management module that reads data stored in the buffer memories and that transfers them in sequence to the addressee; and a storage module that stores read pointers associated respectively with each buffer memory, each read pointer indicating an elementary location of the buffer memory with which it is associated and in which data can be read, wherein the buffer memories are associated respectively with each data source, and for each buffer memory, the controller includes means for executing a firmware that reads data and updates a read pointer associated with this buffer memory, and for synchronising execution of the firmwares as a function of a predetermined order of data originating from buffer memories required in a data sequence to be tra

Abstract: Disclosed is a method that simultaneously transfers DMA data from a peripheral device to a hardware assist function and processor memory. A first DMA transfer is configured to transfer data from the peripheral to a peripheral DMA engine. While receiving the data, the DMA engine simultaneously transfers this data to processor memory. The DMA engine also transfers a copy of the data to a hardware assist function. The DMA engine may also simultaneously transfer data from processor memory to a peripheral device while transferring a copy to a hardware assist function.

Abstract: Shared memory device apparatus and related methods are disclosed. An example method includes obtaining memory operation commands. The memory operation commands are received by a command dispatcher in a same order as obtained by the queue arbiter from the host device. The example method further includes separately and respectively queuing the memory operation commands for each of a plurality of memory devices and dispatching the memory operation commands for execution. The example method also includes receiving the dispatched memory operation commands at a plurality of command queues, where each command queue is associated with a respective one of the plurality of memory devices. Each command queue is configured to receive its respective dispatched memory operation commands from the command dispatcher in a same order as received by the dispatcher and provide the received memory operation commands to its respective memory device in a first-in-first-out order.

Abstract: Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.

Abstract: A first node includes a DMA engine for transferring data specified by a sequence of control blocks to a second node. When a control block does not require synchronization between memories, the DMA engine sends an end of transfer (EOT) message after the last datum, increments an EOT counter, and processes the next control block. When a control block requires synchronization and the EOT counter is at zero, the DMA engine sends an EOT with a flag after the last datum, increments the EOT counter, and waits for the EOT counter to return to zero before processing the next control block. A memory controller at the second node detects the EOT with or without a flag and generates an EOT acknowledgement with or without a flag. When a link interface at the second node detects the EOT acknowledgement with a flag, it sends an interrupt to a local processor complex.

Abstract: A network processor is connected to an external memory which includes storage areas for storing received data, and stores descriptors specifying locations of the storage areas, respectively.

Abstract: Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.