Abstract: A computer system includes first and second integrated circuits. The first integrated circuit provides a first input/output bus operating in accordance with a first protocol, such as ISA. The first input/output bus includes a plurality of address and data lines respectively providing address and data information. The second integrated circuit includes a plurality of second functional blocks at least some of which interface to legacy devices. The first integrated circuit includes a host controller circuit, coupled to the first input/output bus and for coupling to a register access bus which includes a register data out and a register data in signal line. The register access bus connects the first and second integrated circuits. The host controller circuit receives address and data information from the input/output bus and serially provides the address and data information to the data out line. A target controller circuit on the second integrated circuit is coupled to the register access bus.

Abstract: A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus.

Abstract: An apparatus for testing an IDE controller with random constraints, the apparatus including: an IDE controller module for simulating the IDE controller, wherein the IDE controller includes at least one channel and a host interface; a control module for generating data patterns and for transmitting and receiving the data patterns via the host interface and the at least one channel; a verification module, coupled to the control module, for determining whether received data patterns match expected values; and a device module, coupled to the at least one channel, for receiving the data patterns transmitted from the control module and transmitting the data patterns back to the verification module via the at least one channel.

Abstract: Higher speed data transactions between a host computer's system memory and a plurality of slow peripheral devices are accomplished by providing distributed DMA functions along with distributed pre-fetch buffers. The first I/O device accesses the host bus via a first DMA channel and a first pre-fetch buffer, the second I/O device accesses the host bus via a second DMA channel and a second pre-fetch buffer, and the third I/O device accesses the host bus via a third DMA channel and a third pre-fetch buffer. In a first DMA transaction, the first pre-fetch buffer is filled with data being transferred between the first I/O device and the host system memory. While the data are transferred between the pre-fetch buffer and either the first I/O device or the system memory, the second pre-fetch buffer is being filled pursuant to a second DMA transaction between the second I/O device and the system memory.

Abstract: A data processing unit capable of solving a conventional problem in that a CPU cannot acquire the right of using a bus as long as a DMAC (Direct Memory Access Controller) has that right, and hence the operating ratio of the CPU reduces. A CPU bus is kept disconnected from the DMAC bus as long as the CPU disables the access request to a memory connected to the DMAC bus, and is connected to a DMAC bus in response to the access request unless the DMAC has the right of using a DMAC bus.

Abstract: The present invention relates to a system and method for supporting DMA I/O devices. A PCI-PCI bridge is provided to support DMA I/O devices on the PCI bus. Through the use of two signal lines and a serial link, DMA transfers may be accomplished over the PCI bus. A PCI-ISA dock bridge is also provided to allow the system to support DMA I/O devices and ISA masters (i.e., any device including DMA I/O devices on the ISA bus that generates ISA cycles) on the ISA bus.

Abstract: To increase access speed, a single-chip computer system having a direct memory access (DMA) mode, includes a central processing unit (CPU) for executing instructions, a first bus connected to the CPU, a memory array connected to the first bus, for storing data, a buffer connected to the first bus, a second bus connected to the buffer, and a communication circuit, connected to the second bus, for receiving and outputting data. The buffer connects the first bus to the second bus when the DMA mode is executed, and disconnects the first bus from the second bus when the DMA mode is not executed.

Abstract: A system and method that allows ISA-compatible DMA devices (60) to communicate over non-ISA buses such as the VL bus (20) and a PCI bus (30). In a computer system (10) with a non-ISA bus, the present invention couples a secondary set of DMA controllers (50) in the same input/output space and a glue logic circuit (70) to the non-ISA bus in the computer system (10) to allow the ISA-compatible DMA device (60) to operate over the non-ISA bus. The secondary set of DMA controllers (50) provides the support for an ISA-compatible DMA device (60) to perform DMA transactions and the glue logic circuit (70) directs the DMA controller accesses to the proper place in the computer system (10).

Abstract: In a DMA controller in accordance with the present invention, in the case of memory-to-memory data transfer using the DMA process (transfer for changing addresses inside the memory), one channel for carrying out the data transfer is provided. In the case of data transfer between the I/O device and a memory using the DMA process, two channels for carrying out the data transfer are, on the other hand, provided by using a circuit that constitutes said one channel. Thus, it is possible to provide multiple channels in the DMA controller by using a compact, inexpensive circuit construction.