Abstract: A method and system for tracking data packets that utilizes a tree data structure with a recursive pruning algorithm that collapses the branches of the tree that represent contiguous ranges or regions to maintain a minimally optimum memory size. Each contiguous region is identified by a node, which includes the start and end range of packets. Each node further includes left and right pointer elements, which point to adjacent lower and higher nodes, respectively. When a packet sequence number is not contiguous with any other sequence numbers previously received, a new node is created that contains only a single value range. When a new packet is received that has a contiguous sequence number (i.e., immediately preceding or succeeding sequence number), the original node is updated so as to reflect the new contiguous range. Additionally, if this new contiguous range is contiguous with another node's range, the two nodes are “collapsed” into a new single node containing the new expanded contiguous range.

Abstract: An embodiment of this invention pertains to a system and method for balancing memory accesses to a low cost memory unit in order to sustain and guarantee a desired line rate regardless of the incoming traffic pattern. The memory unit may include, for example, a group of dynamic random access memory units. The memory unit is divided into memory channels and each of the memory channels is further divided into memory lines, each of the memory lines includes one or more buffers that correspond to the memory channels. The determination as to which of one or more buffers within a memory line an incoming information element is stored is based on factors such as the number of buffers pending to be read within each of the memory channels, the number of buffers pending to be written within each of the memory channels, and the number of buffers within each of the memory channels that has data written to it and is waiting to be read.

Abstract: A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.

Abstract: A method and system for transferring a transport stream, such as from a satellite receiver to a networked computer system, are provided. The transport stream is parsed to derive multiple elementary streams including associated program identifiers, which are used to determine corresponding transfer locations in a host memory. Direct memory access transfers of the multiple elementary streams are then performed to the corresponding transfer locations in the host memory.

Abstract: In parallel with accesses to a cache made by a core processor, a DMA controller is used to pre-load data from a main memory into the cache. In this manner, the pre-load function can make the data available to the processor application before the application references the data, thereby potentially providing a 100% cache hit ratio since the correct data is pre-loaded into the cache. In addition, if a copy-back cache is employed, the cache memory system can also be configured such that processed data can be dynamically unloaded from the cache to the main memory in parallel with accesses to the cache made by the core processor. The pre-loading and/or post unloading of data may be accomplished, for example, by using a DMA controller to burst data into and out of the cache in parallel with accesses to the cache by the core processor. This DMA control function may be integrated into the existing cache control logic so as to reduce the complexity of the cache hardware (e.g.

Abstract: System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. Thus, the data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer, respectively.

Abstract: A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described.

Abstract: An embedded controller includes a central processing unit, a memory interface for interface with an external memory, and a function block or peripheral device with a register for storing operation state information. The peripheral device includes a detection circuit, a storage unit, for example in the form of a FIFO, a multiplexer, and a direct memory access (DMA) controller. The state detection circuit activates a flag signal whenever the operation state information of the register is varied, and the FIFO stores the operation state information from the register in response to the flag signal. The multiplexer is controlled by the DMA controller and transmits the operation state information of the FIFO to an internal bus. As a result, the operation state information of the FIFO is stored in the external memory through the memory interface.

Abstract: An improved descriptor system is provided in which read pointers indicate to a host and a peripheral the next location to read from a queue of descriptors, and write pointers indicate the next location to be written in a queue. The system also allows an incoming descriptor to point to a plurality of data frames for transfer to the host processor, wherein the peripheral need not read a new descriptor each time a frame is to be transferred to the host.

Abstract: Various embodiments of a system and method for configuring a set of DMA resources as multiple virtual DMA channels are disclosed. In one embodiment, a system may include a context memory configured to store context parameters for each of the virtual DMA channels, a set of DMA resources, a DMA controller coupled to the context memory, and several I/O resources. The DMA controller is configured to configure the set of DMA resources as different virtual DMA channels using context parameters associated with different respective ones of the virtual DMA channels. Each virtual DMA channel corresponds to one of the I/O resources.

Abstract: Embodiments of the invention provide a status register for each channel of a DMA controller. The status register may be used to monitor and record events that occur during DMA data transfers, including timeouts and aborts.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.

Abstract: Complex control procedures employ direct memory access by a first DMA processing unit 54 to send control data to a first controller by means of DMA channels 54-1 to 54-n, and by a second DMA processing unit 56 to send control data to a second controller 36 by means of DMA channels 56-1 to 56-m. The first DMA processing unit 54 also has a branching controller 52 as a DMA channel for transferring timing data to a second timer 40. When a time specified by the received timing data passes, the second timer 40 sends an activation signal to DMA channel 56-1 of the second DMA processing unit 56, and the DMA channels 56-1 to 56-m are thereafter sequentially activated.

Abstract: A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. Configurable signal processing logic may be configured to host one or more signal processing functions which allow data to be autonomously accessed from the processor local memories, processed, and re-deposited in a local memory.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: The communication system stores packet data received via a plurality of communication channels in a memory or transmits packet data stored in the memory through the communication channels includes buffer descriptors in which information on packet data is stored. The system comprises a central processing unit (CPU) which stores the information on packet data in the buffer descriptors and indicates whether each of the buffer descriptors is being organized, whether an error occurred in packet data received, or whether the organization of each of the buffer descriptors is completed by allotting a flag bit to each of the buffer descriptors. The system comprises a direct memory access (DMA) controller which stops processing a buffer descriptor currently being accessed and accesses a next buffer descriptor, or processes packet data information stored in the buffer descriptor currently being accessed, after identifying the flag bit of the buffer descriptor currently being accessed.

Abstract: A system comprises a plurality of memory controllers connected to a memory bus. Each memory controller is able to generate memory requests on the memory bus according to a predetermined priority scheme. One priority scheme is a time slot priority scheme, and another priority scheme is a request-select priority scheme. The plurality of memory controllers are able to monitor memory requests generated by another memory controller in performing memory-related actions, such as memory requests (read or write), read-modify-write transaction, and cache coherency actions. In one arrangement, the memory bus is a Rambus channel.

Abstract: A network apparatus comprising storage units storing configuration information about the network apparatus, an input network interface to at least one network physical line, at least one processor receiving network data from said network interface, processing said data, storing information about said network data in said storage units, storing said data as formatted data units in said storage units, a first bus interface to two bus connections, a first hardware component reading said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface, a second bus interface to two bus connections, an output network interface to at least one network physical line, a second hardware component reading formatted data units arriving on at least one of the two bus connections of said second bus interface and storing said formatted data units in said storage un

Abstract: A semiconductor integrated circuit for use in direct memory access (DMA) has two sources which communicate with a bus through a bus interface. A DMA access signal generator is coupled to the bus interface and asserts a DMA access output signal at a DMA access signal pin whenever either of the sources requires a DMA access. The need for separate DMA access signal pins for each of the two sources is thereby avoided. With targets on two separate integrated circuits, a single DMA access pin can be used for the two targets, while chip select signals at chip select pins on the source integrated circuit indicate which of the two targets is intended for the DMA access.

Abstract: A method and system of memory management incorporates multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data. A tree memory controller controls data read and write accesses to each of the banks in each of the channels. A bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank. In response to a write request, the controller blocks all read requests once it has confirmed that data to be written is complete for the selected memory word length. As soon as each bank queue for read requests is empty, the controller initiates burst mode transfer of the completed data word to all banks concurrently.

Abstract: A method of write-protecting a MAC address of a peripheral terminal stored in a DMI memory. First, programs capable of erasing the MAC address stored in the first memory are disabled. Then, a DMI setting is executed to write-protect the MAC address stored in the second memory. Finally, a program is provided capable of pre-storing the original MAC address.

Abstract: A method and system for accessing a shared memory in a deterministic schedule. In one embodiment, a system comprises a plurality of processing elements and a system I/O controller where each processing element and system I/O controller comprises a DMA controller. The system further comprises a shared memory coupled to each of the plurality of processing elements where the shared memory comprises a master controller. The master controller may then issue tokens to DMA controllers to grant the right for the associated processing elements and system I/O controller to access the shared memory at deterministic points in time. Each token issued by the master controller grants access to the shared memory for a particular duration of time at a unique deterministic point in time. A processing element or system I/O controller may access the shared memory upon the associated DMA controller relinquishing to the master controller the token that grants the right to access the shared memory at that particular time.

Abstract: A trace and debug support unit (120) that works in conjunction with a bus sniffer (112). The trace and debug support unit (120) maintains in memory one or more configurable filter rules which are used to define parameters of the trace history. A plurality of conditions or rules are provided, satisfaction of one or more of which causes a trace history to be filed. A transfer-specific signal may be issued, whereby all cells of the identified transfer are filed as part of the trace history. Alternatively, a connection-specific flag may be carried with each cell, whereby all cells of the specific connection are filed as part of the trace history.

Abstract: A micro-controller direct memory access (DMA) unit includes hardware support for single read of the source address at a source word size and but writes to the target address at an independent target word size. This permits, for example, a single read of the source address at a larger word size and multiple sub-word sized writes to the target address. This is enabled by independent control register storage of a source word size, a source increment size, a target word size and a target increment size. A byte shifter/register that will shifts a full byte at a time to the next lower byte position allowing transfer of a large word to a destination having a small word size.

Abstract: A method for accessing I/O devices in embedded control environments is provided, wherein said I/O devices are remotely attached to an embedded microprocessor. By mapping said I/O devices' resources to said microprocessor's address or memory address space, existing device drivers can be reused and the time-to-market capability is greatly improved.

Abstract: A CAN microcontroller that supports a plurality of message objects, including a processor core that runs CAN applications, and a CAN/CAL module that processes incoming messages, and a data memory. The data memory includes a first memory segment that provides a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects. The memory-mapped registers for each message object contain respective command/control fields for configuration and setup of that message object.

Abstract: According to one embodiment of the present invention, a system (10) for data transfer is disclosed that comprises a transfer memory (24) having one or more buffers (40, 42, 44, 46, and 48). Accessing units comprising direct memory access units (20 and 22) are coupled to the transfer memory (24) and are operable to access the transfer memory (24). Pointers (50, 52, and 54) stored in the transfer memory (24) direct the accessing units (20 and 22) to selected ones of the buffers (44, 46, and 48) such that no two accessing units (20 and 22) are simultaneously accessing one buffer (44, 46, and 48). More specifically, the pointers (50, 52, and 54) may also direct a memory control unit (30) to a buffer that is not being accessed by an accessing units (20 and 22). According to one embodiment of the present invention, a method for data transfer is disclosed. First, a transfer memory (24) comprising one or more buffers (40, 42, 44, 46, and 48) is provided.

Abstract: A DMA system includes a plurality of transmit-receive pairs (102, 104) for communicating on a bus. A DMA controller (108) supervises bus handling. The DMA controller (108) includes a priority controller (114), a bus sniffer (112), and a context machine (116). The bus sniffer (112) and context machine (116) identify block transfers as frame or cell transfers and supervise interleaving. The priority controller (114) resolves the priority of each of the constituent transfers of the frame or cell block transfers using a matrix of priority tokens.

Abstract: Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and a second portion as a memory accessible by the one or more data transmission devices through a data bus independently of the core processing circuit.

Abstract: There is provided a data transfer apparatus for transferring data from a main memory coupled to a main bus to a local memory coupled to a local bus. The data transfer apparatus includes: a first-in-first-out buffer having a data region for storing one or more words of CPU access data which is accessed by a CPU coupled to the main bus, and a plurality of words of DMA access data which is accessed by a DMA controller coupled to the main bus; and a controller for controlling the first-in-first-out buffer. When the local bus is available, the controller controls the first-in-first-out buffer so as to consecutively transfer the one or more words of CPU access data stored in the data region to the local memory, and to burst transfer the plurality of words of DMA access data stored in the data region to the local memory.

Abstract: A method and system for mounting an information handling system disk drive with one or more storage disk drives coupled to an information handling system circuit board so that components of the information handling system are disposed in the space between the storage disk drive and the circuit board. In one embodiment, a server blade mounts plural hard disk drives to a motherboard with tool-less shoulder screws that elevate the hard disk drives relative to the motherboard to allow space for interfacing components, such as a bridge chip and video chip, with the motherboard below the hard disk drive. Cooling air flows through the space between the motherboard and the hard disk drives to cool plural processors interfaced with the motherboard.

Abstract: An SMP computing system has a RAID controller and an interconnect bus system for communication processors and the RAID controller. There are in host memory a plurality of reply queues, at least one of which is associated with each processor of the SMP computing system. Replies associated with commands originating from a first processor are buffered by the RAID controller in a first reply queue, and replies associated with commands originating from a second processor are buffered in a second reply queue.

Abstract: A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system.

Abstract: A digital system having a split transaction memory access. The digital system can access data from a system memory through a read buffer (FIFO) located between the processor of the digital system and the system bus. The read buffer is implemented with two FIFOs, a first incoming data FIFO for reading data, and a second outgoing address FIFO for transmitting read requests. The processor of the digital system can access the data FIFO and read data while the data transfer is still in progress. This decreases the processing latency, which allows the processor to be free to perform additional tasks.

Abstract: A DMA controller has a cycle register in which the number of data transfer cycles to be performed in response to a single DMA transfer request is set, a cycle counter for counting the number of data transfer cycles actually performed, and a transfer counter for holding a value that is updated every time the number of data transfer cycles as held in the cycle register are completed. From the start to the end of the data transfer cycles, the number held in the cycle register is kept unchanged, and the data transfer cycles are performed until the value held in the transfer counter becomes equal to a predetermined value. In this configuration, even in a case where a predetermined number of DMA transfer cycles are performed in response to a single DMA transfer request and a plurality of DMA transfer requests are made in succession, the CPU has to set in the DMA controller only once the addresses of the source and destination locations and the values to be held in the cycle register and the transfer counter.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. An exemplary technique utilizes a CPU and an SPI having a circular FIFO structure. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory. During a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware.

Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

Abstract: A architecture for a multifunction peripheral to service a plurality of clients simultaneously. A shared memory receives data from the plurality of clients. A channel multiplexer selects data to be routed to a peripheral, a SCSI emulator is used to logically select the peripheral. The data is then forwarded from the multiplexer via the SCSI emulator to a PCI bus, the PCI bus being physically connected with the peripheral's engine. When data needs to be sent from a peripheral to a client, it is forwarded from the PCI bridge to the SCSI emulator and routed via a demultiplexer to the shared memory wherein it is retrieved by the appropriate client. The multifunction peripheral can be interrupted while performing a first task using a first peripheral, switch to a second task needing a second peripheral, and return to the first task when completed.

Abstract: An integrated circuit including a DMA controller, an ADC having a plurality of conversion channels and address and data ports for connection to external memory means, the DMA controller being arranged to read a channel id from the memory means using the address and data port which channel id is representative of one of the said conversion channels, to pass the read channel id to the ADC, to cause the ADC to perform an analog-to-digital-conversion on the conversion channel represented by the channel id, to receive the conversion result from the ADC and to write the conversion result back to the memory means using the address and data ports.

Abstract: A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

Abstract: A DMA controller includes: a bus availability frequency register setting a ratio of a bus access frequency of DMA transfer to a bus access frequency of another bus master; a DMA request detecting portion detecting a DMA request; a bus availability counter counting the bus access frequency in accordance with the ratio set in the bus availability frequency counter; a bus access request controlling portion controlling the bus access request based on the DMA request detected by the DMA request detecting portion and the counted result of the counter; and a DMA controlling portion controlling execution of DMA transfer. Thus, a band which allows another bus master to use a bus during DMA transfer can be predicted.

Abstract: An accelerated filesystem includes a fast-path and a slow-path. The fast-path includes an enhanced storage controller and an enhanced network processing function. Uncontested READ and WRITE operations are processed on the fast-path. A READ session is initialized by obtaining file-storage metadata that is tagged with a session ID. The session ID is provided to the enhanced network processing function, and to the application as a file handle, and the tagged metadata is provided to the enhanced storage controller. Subsequent access is facilitated by communicating the file handle from the application to the enhanced network processing function, which passes the file handle to the enhanced storage controller in response. The enhanced storage controller executes a file handle to block list translation by employing the tagged metadata to retrieve the appropriate data. The retrieved data is transmitted to the application via the enhanced network processing function.

Abstract: A method, apparatus, and computer program product are described for controlling data transfer. A next data packet to be transferred is retrieved. A determination is made regarding whether a data bus busy signal is asserted. If the data bus busy signal is asserted, a determination is made regarding whether a data bus grant signal is asserted. If the data bus grant signal is asserted, the next data packet is transferred on the next cycle after a last cycle of data transfer of a previous data packet.

Abstract: An arbiter apparatus for selecting an agent to use a shared resource such as memory. A normal round robin list is utilized in the selection process during boot operation. During the initialization process, a dynamic list is generated in accordance with system requirements. The dynamic list selection process may take any of several forms. In a first mode, it may select only priority listed agents, any one of which may be repeated during a given cycle of selection. In a second mode, it may select a designated buddy agent when the selected priority agent is idle. In either mode, and in accordance with a set of priority selection rules, one or more lowest priority default agents may be given access when the designated higher priority agents for a given list entry slot are idle.

Abstract: A method and a system for arbitrating accesses to a memory in a data processing system having many memory access units (MAU) and an arbiter are disclosed. The arbiter initially sends a permission signal to each MAU to give each MAU a chance to reset its priority level if necessary. Then each of a first set of top priority MAUs that was not able to access to the memory for a predetermined period of time resets its priority level to a top priority value and sends a second priority value to the arbiter. Thereafter the arbiter selects a MAU among the first set of top priority MAUs and sends an acknowledgement signal to the selected MAU. If none of the first set of top priority MAUs exist, the arbiter identifies a second set of top priority MAUs by checking the predetermined starvation period of each MAU and sends an acknowledgement signal to one of the second set of top priority MAUs.

Abstract: A method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system is provided. In one embodiment, the system includes a hypervisor and at least one DMA address checking component. The hypervisor receives non-direct-memory-access requests for access to input/output slots and prohibits devices within one logical partition from accessing the input/output slots assigned to a different logical partition. The DMA address checking component receives direct-memory-access requests and prohibits requests for addresses not within the same logical partition as the requesting device from being completed. Requests with addresses corresponding to the same logical partition as the requesting device are placed on the primary PCI bus by the DMA address checking component for delivery to the system memory.

Abstract: The present invention is directed to an apparatus and system for selectively inhibiting access to a memory during a DMA block transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engine's request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.

Abstract: A system is provided that includes a bus master, a bus slave and a fly-by slave interface, all coupled to a peripheral bus. A peripheral device is coupled to the fly-by slave interface. The bus master is configured to control fly-by transfer of data between the bus slave and the peripheral device without buffering the data. The fly-by slave interface is configured to isolate the peripheral device from the peripheral bus during fly-by transfer of data between the bus slave and the peripheral device. In addiction, the bus slave is configured to provide a set of control signals on the peripheral bus, wherein the control signals regulate the flow of data on the peripheral bus during fly-by transfer of data between the bus slave and the peripheral device. Fly-by transfers can be fully synchronous, and burst operation at the rate of one data value per clock cycle is supported.

Abstract: A method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter are disclosed. The system includes one or more processors that have access to a system memory. A host bridge is connected between the processor(s) and an I/O bus. A first I/O adapter, which generates 32-bit addresses, is coupled to the host bridge. A second I/O adapter coupled to the host bridge is enabled to generate an address with a width greater than 32-bits (such as a 64-bit address). The system may include a Translation Control Entry (TCE) table, that is configured with information needed to translate an address generated by the 32-bit adapter to a wider address (such as a 64-bit address). In addition, the TCE may determine whether DMA access to the translated address by the requesting adapter is authorized. The system further includes an Access Control Table (ACT). The ACT determines whether DMA access to the address generated by the 64-bit I/O adapter is authorized.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.