Abstract: A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned system, from accessing data from a memory location allocated to another OS image is provided. The system includes logical partitions, operating systems (OSs), memory locations, I/O adapters (IOAs), and a hypervisor. Each operating system image is assigned memory locations and input/output adapter is assigned to a logical partition. Each of the input/output adapters is assigned a range of I/O bus DMA addresses by the hypervisor. When a DMA operation request is received from an OS image, the hypervisor checks that the memory address range and the I/O adapter are allocated to the requesting OS image and that the I/O bus DMA range is within the that allocated to the I/O adapter. If these checks are passed, the hypervisor performs the requested mapping; otherwise the request is rejected.

Abstract: A direct memory access function for servicing real-time events, ensures that any parameter reloads occur during times when the direct memory access channel is idle and guarantees completion before the channel begins active operation again. The direct memory access channel whose parameters are to be updated is disabled during the update cycle. This ensures that no requests are processed until the new parameters have been written to the direct memory access channel parameters. A second direct memory access channel may be used to reload the data transfer parameters permitting a self-modifying direct memory access function.

Abstract: In a network system in which a request of executing a process is sent from the higher level system to the lower level system, a time period of not executing a requested job is assured in the lower level system while assuring an asynchronism between the both systems and a certainty of the requested job. The higher level system transmits a pair of signals (a preparatory signal and an execution signal) to the lower level system in a predetermined interval after it holds a processing request to be sent to the lower system. The higher level system then resumes transmission of the processing request a predetermined time after transmitting the pair of signals.

Abstract: The control apparatus reads the value of an external switch, and checks whether the apparatus serves as a control side or subordinate side. If the control apparatus serves as a subordinate side, it waits until the control side writes a configuration through a bus. If the control apparatus serves as a control side, it sets necessary values in itself, and writes a configuration in a device on the bus. In this way, the control apparatus can operate as both the control side and subordinate side.

Abstract: An Infiniband channel adapter for performing direct data transfers between a PCI bus and an Infiniband link without double-buffering the data in system memory. A local processor programs the channel adapter to decode addresses in a range of the PCI bus address space dedicated to direct transfers. When an I/O controller attached to the PCI bus transfers data from an I/O device to an address in the dedicated range, the channel adapter receives the data into an internal buffer and creates an Infiniband RDMA Write packet for transmission to virtual address within a remote Infiniband node. When the channel adapter receives an Infiniband RDMA Read Response packet, the channel adapter provides the packet payload data to the I/O controller at a PCI address in the dedicated range. A plurality of programmable address range registers facilitates multiple of the direct transfers concurrently by dividing the dedicated address range into multiple sub-ranges.

Abstract: According to the present invention, an apparatus and method for improving reads from and writes to shared memory locations is disclosed. By giving writes priority over reads, the current invention can decrease the time associated with certain sequences of reads from and writes to shared memory locations. In particular, load-invalidate-load sequences are changed to load—load sequences with the current invention. Furthermore, contention for a shared memory location will be reduced in particular situations when using the current invention.

Abstract: A method and system for enhancing the efficiency of the completion of host-initiated I/O operations within a fiber channel node. The host computer component of the fiber channel node does not allocate the memory buffer for the FCP response frame received by the FC node at the completion of an I/O operation. Instead, the interface controller of the FC node processes FCP response frames in order to determine whether or not an I/O operation successfully completes. In the common case that the I/O operation successfully completes, the interface controller writes the FCP exchange ID corresponding to the I/O operation to a special location in memory which serves to invoke logic functions implemented in an ASIC that de-allocate host memory resources allocated for the I/O operation.

Abstract: A trace and debug support unit (120) that works in conjunction with a bus sniffer (112). The trace and debug support unit (120) maintains in memory one or more configurable filter rules which are used to define parameters of the trace history. A plurality of conditions or rules are provided, satisfaction of one or more of which causes a trace history to be filed. A transfer-specific signal may be issued, whereby all cells of the identified transfer are filed as part of the trace history. Alternatively, a connection-specific flag may be carried with each cell, whereby all cells of the specific connection are filed as part of the trace history.

Abstract: A DMA controller comprises an arbitration unit for arbitrating among a plurality of channels so as to select a DMA request from among a plurality of DMA requests accepted by way of the plurality of channels according to priorities assigned to the plurality of channels in advance, and a trace buffer for storing trace data associated with the DMA request selected by the arbitration unit. The DMA controller can also include a write control unit for enabling or disabling writing of the trace data associated with the DMA request selected by the arbitration unit in the trace buffer.

Abstract: The transfer controller with hub and ports (TCHP) performs the task of communication throughout an entire system in a centralized function. A single hub (435) tied to multiple ports (440, 447, 450, 452) by a central pipeline is the medium for all data communications among DSP clusters (455), external devices, and external memory. A transfer request queue manager (420) receives, prioritizes and queues data transfer requests. Each data port includes an identically configured interior interface (901) connected to the hub (435) and an exterior interface (902) configured for a target external memory/device connected to the port. The interior interfaces of all ports are clocked at a common internal frequency, while the exterior interfaces are clocked at the frequency of the external memory/device connected to the port.

Abstract: A bus control device having a plurality of devices such as a processor or a DMAC which can be a bus master accessing a system bus. When the processor transfers data to a memory or a processing circuit, a system bus controller for the processor and a system bus controller for the memory or a system bus controller for the processing circuit access the system bus within an accessible minimum time with each of input/output signals. When the DMAC transfers data to the memory or the processing circuit, a system bus controller for the DMAC and the system bus controller for the memory or the system bus controller for the processing circuit access the system bus within the accessible minimum time with each of the input/output signals.

Abstract: An input/output device used as a transfer request source outputs a data transfer set command for specifying each transfer channel, each transfer address, the number of transfers, etc. onto a bus together with a data transfer request without involving the use of the CPU. According to the data transfer set command, data transfer control information is set to direct memory access control means, and DMA transfer is started between the input/output device and a memory designated by the transfer address, for example. When the input/output device used as a data transfer request source desires to perform data transfer without regard to the state of processing by the microcomputer, it can perform data transfer processing with its own timing and the data transfer with the input/output device as a principal base is allowed.

Abstract: A controller (203) for coupling between a computer bus (20) and one or more units (221, 222) compatible with the bus. The controller comprises a first input (28) for receiving a first reset signal issued from the computer bus, and a second input (30) for receiving a second reset signal. The controller further comprises circuitry (26) for storing a first set of information which will be cleared in response to assertion of the first reset signal. Lastly, the controller comprises circuitry (24) for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal. In a described embodiment, the bus is a PCI bus, the first reset signal is a PCI Reset signal, and the second reset signal is an initialization signal.

Abstract: A modular optimizer, for use in determining a configuration of a production line with one or more component placement machines, is configured to handle precedence constraints. The precedence constraints may be of the form A B MT, which specifies that part A must be placed on a designated assembly board before part B if either part is to be placed by a machine type MT. A given set of precedence constraints includes at least a first class of constraints that apply to only one component placement machine type and a second class of constraints that apply to more than one component placement machine type. Assignment of constraints to the different classes is based on decisions of a part splitter module of the modular optimizer regarding which parts are assigned to which machine types. Each of the constraints in the first class of constraints associated with a given machine type are handled in a corresponding machine module of the modular optimizer.

Abstract: A method of using bank tag registers in a multi-bank memory device to avoid background operation collision is described. A memory controller includes a plurality of bank registers, each of which is associated with one of a plurality of memory banks, wherein a bank register is arranged to store information, a bank number, a bank status, and a bank counter for a particular bank. The memory controller further includes an adjustable bank comparator coupled to each bank register. The memory controller receives an incoming system address request, which includes a requested bank number. The requested bank number is used to configure the adjustable bank comparator with the particular bank operating characteristics, to locate the bank register, and to determine the bank status and the bank entry status of the requested memory bank. The requested memory bank is accessed when the bank entry status identifies the requested memory bank as open.

Abstract: A method and apparatus are provided for implementing direct memory access (DMA) with dataflow blocking for users for processing data communications in a communications system. A DMA starting address register receives an initial DMA starting address and a DMA length register receives an initial DMA length. A DMA state machine receives a control input for starting the DMA. The DMA state machine updates the DMA starting address to provide a current DMA starting address. The DMA state machine loads a DMA ending address. A DMA blocking logic receives the current DMA starting address and the DMA ending address and blocks received memory requests only within a current active DMA region.

Abstract: A digital computer comprising a plurality of processors interconnected by a network for transferring messages among the processors. At least one processor generates messages of a configuration type. The network comprises a plurality of nodes interconnected in a tree pattern in a series of levels from a lower leaf level to an upper physical root level, with the leaf nodes connected to the processors. Each of the nodes includes a root flag that can be set or cleared in response to a message of the configuration type to establish the node as a logical root. For each node, if the node is a logical root it transfers messages received from a node at a lower level in the tree back down the tree, but if the node is not a logical root it transfers messages received at a lower level node to a higher level node.

Abstract: Security is provided for a docking station. Within the docking station a docking password is stored. Upon a portable computer being attached to the docking station, a password stored in the portable computer is compared to the docking password. If the password stored in the portable computer is equal to the docking password, the portable computer is allowed to access the docking station. If the password stored in the portable computer is not equal to the docking password, the portable computer is prevented from accessing the docking station.

Abstract: A method and system for accessing a shared memory in a deterministic schedule. In one embodiment, a system comprises a plurality of processing elements and a system I/O controller where each processing element and system I/O controller comprises a DMA controller. The system further comprises a shared memory coupled to each of the plurality of processing elements where the shared memory comprises a master controller. The master controller may then issue tokens to DMA controllers to grant the right for the associated processing elements and system I/O controller to access the shared memory at deterministic points in time. Each token issued by the master controller grants access to the shared memory for a particular duration of time at a unique deterministic point in time. A processing element or system I/O controller may access the shared memory upon the associated DMA controller relinquishing to the master controller the token that grants the right to access the shared memory at that particular time.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: The present invention discloses a method and apparatus for processing a packet of data received from a direct memory access (DMA) engine. In one embodiment, a counter generates a self-ID code and increments the self-ID code after a bus reset. A formatter is coupled to the counter to format a start-of-packet (SOP) message which contains a self-ID field. The SOP message corresponds to the packet and the self-ID field corresponds to the self-ID code. A first-in-first-out (FIFO) is coupled to the formatter to store the SOP message and the packet. A comparator is coupled to the FIFO to compare the self-ID field of the message read from the FIFO with the self-ID code. A control circuit, which is coupled to the FIFO, flushes the packet if the self-ID field of the message is different than the self-ID code.

Abstract: Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given cycle to ensure that all devices will be serviced within a programmable time period. The data reservoir contains the data buffers for each channel of each device. A memory interface ensures that sufficient data for each channel is present in the data reservoir by making requests to a system's memory based on an analysis of each channel. Based on this analysis, a request is either made to the system's main memory, or the channel waits until it is evaluated again in the future. Each channel is thereby guaranteed a response time.

Abstract: A memory component on a single integrated circuit includes a RAM, one or more configuration registers, and an associated controller. The behavior of the memory component, including selection from a number of different operating modes, is controllable via configuration register mode bits. The various modes include several transfer-length modes, where each mode corresponds to data transfers of a predetermined length. Based on the mode selection specified by the mode bits, the controller determines the length of the data transfers.

Abstract: A device for the bidirectional transfer of data between two processors contains input and output control information memories for storing an item of binary control information for input and output memories. The memories can be accessed by the second processor and, via a DMA channel, by the first processor. The access operations of both processors to these memories are coordinated on the basis of the content of the input and output control information memories.

Abstract: An interface architecture includes a plurality of pipelines each controlled by a respective line processor. An onboard ESCON protocol conversion device distinguishes customer data to be stored on a disk or read from disk versus header information. Transmit and receive frame dual port rams store transmitted frame and received frame information, stripping frame/header information from user data. Data to be stored in Global Memory is stored temporarily in FIFOs. An assembler/disassembler in each pipeline receives data from FIFOs (on a write), and transfers data to FIFOs (on a read). A buffer dual port ram (DPR) is configured to receive data for buffering read operations from and write operations to the GM. Data transfers between the assembler/disassembler and the buffer DPR pass through Error Detection And Correction circuitry (EDAC). A plurality of state machines arranged as an Upper Machine, Middle Machine and Lower Machine facilitate movement of user data between DPR and Global Memory (GM).

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started.

Abstract: A bus bridge coupled between two bridges providing bus exception event isolation and address/data translation. In one embodiment the bus bridge includes two direct memory access (DMA) engines and a first-in-first-out (FIFO) buffer interface between the DMA engines to provide the bus exception isolation. The DMA engines and FIFOs also enable a packet based message passing architecture, which eliminates the need for address translation and also handles data reordering.

Abstract: In a controlled object, a process variable of a controlled object process is detected by a sensor and its detection time is measured by a timer. A process signal transmitting device transmits, as a process signal, the process variable and the detection time to a control apparatus. A control variable calculating device calculates a control variable based on the received process variable and a control reference value, and transmits a control signal including the control variable and the received process variable detection time to the controlled object. In the controlled object, a control signal receiving device calculates a transmission delay, that is, a difference between control signal reception time that is measured by the timer and the transmitted process variable detection time, corrects the control variable by processing it in accordance with the transmission delay, and drives an actuator by using the corrected control variable.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set, and a device bus. A bridge control mechanism is configured to provide geographic addressing for devices on the device bus and to be responsive to a request from a device on the device bus for direct access to a resource of a processing set to verify that an address supplied by the device falls within a correct geographic range. A different geographic address range can allocated to each of a plurality of device slots on the device bus. A different geographic address range can also be allocated to the processor set resources (e.g., processor set memory). An address decoding mechanism maintain geographic address mappings, and verifies geographic addresses for direct memory access. The geographic address mappings can be configured in random access memory of the bridge. A slot response register is associated with each slot on the device bus.

Abstract: A method and apparatus for transferring data in a computer system between a first memory region and second memory region in a single Direct Memory Access (DMA) operation. The first memory region, the second memory region, or both the first and second memory regions can include sub-regions of sequentially-addressable memory locations that are separated, within their respective regions, by a stride. The method and apparatus are particularly well adapted for use in computer graphics systems that include one or more regions of memory, such as frame buffers, that are organized in a rectangular manner as a plurality of contiguous but not sequentially-addressable memory locations within the memory of the graphics system.

Abstract: A combination mode of a transfer source and a transfer destination for the data transfer is previously defined depending on a value of the resource select information of a control register (CHCRn). An address comparator circuit (SACn, DACn) has a judging logic specified by the defined contents and detects, depending on such logical structure, the data transfer control disable address error by a data transfer controller (8) on the basis of such logical structure, in accordance with the resource select information and the transfer source address, transfer destination address of the address register (SARn, DARn). Since the data transfer is started only when the resource select information matches with the setting information of both address registers, high reliability can be assured for memory protection in the data transfer operation by the data transfer controller.

Abstract: A multiple-register-access-capable device includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device is controlled by a state machine. Information in one of the registers identifies whether the device is in a single-register or multiple-register mode. The state machine which controls the device operates in a single-register mode if the bit is disabled and operates in a multiple-register mode if the bit is enabled. In single-register mode, the device operates in a manner known in the prior art whereby a single register is identified for reading or writing and data is then either written into the register or read out from the register in response to a write or read request. In multiple register mode, data is written into or read out from all registers in a selected group of registers in the device in response to the write or read request.

Abstract: In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further than notification of non-error and maintenance status changes are processed with minimal latency.

Abstract: An apparatus and method of transmitting data from a PCI 2.1 compliant device is provided. PCI devices (i.e., PCI bridges) designed in accordance with the 2.1 PCI specification have a load data ordering feature that prohibits load data to bypass DMA write data in the bridge. The present apparatus and method allow load data to bypass DMA write data in the PCI bridge if the bridge is in an error state.

Abstract: An improved DMA controller is provided. The improved DMA controller uses a peripheral control bus which has scan codes to indicate the DMA channel, conventional data request/data acknowledge lines, and additional lines indicating a "terminate," "type fetch," "end of buffer" and "store status." List entries are associated with the buffers in the memory. Each list entry has a type/status field which can be coded with information indicating "ready buffer," whether to notify "end of buffer," "buffer in progress," "completed buffer without status," "completed buffer with status," "ready buffer with command," and "ready buffer without command." The type of status byte can be checked before processing the buffers.

Abstract: A method for transferring DMA data between the video port and the host interface in a multimedia processor is disclosed. The method includes determining whether one frame data should be transferred between the host interface and the video port; preloading some DMA instructions in the frame buffer and setting the DMA register to be fitted for the DMA operation; and fetching the preloaded instructions from the frame buffer subsequently by the DMA controller to perform video data transfer at a predetermined data bandwidth. According to this invention, the time consumption of a microprocessor for programming the DMA controller is reduced, thereby enhancing the data transfer rate between the host interface and video port of the multimedia computer system.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: A recording apparatus is disclosed that, in use, is connected with a host apparatus, receives recording information from the host apparatus by direct memory access ("DMA") and can print received recording information by using a recording head. A first memory access circuit receives recording information from the host apparatus by DMA. A second memory access circuit supplies received recording information to the recording head with a timing appropriate for recording, using DMA. A priority circuit controls the respective priorities assigned to various types of DMA to ensure that all types of DMA demands can be accommodated within an acceptable length of time.

Abstract: A multiple channel data communication buffer includes a first side having a plurality of communication ports and a second side having data routing port. A single port transmit memory is coupled between the plurality of communication ports and the data routing port. A transmit arbitration circuit is coupled to the single port transmit memory, which arbitrates access by the plurality of communication ports and the data routing port to the single port transmit memory. A single port receive memory is coupled between the plurality of communication ports and the data routing port. A receive arbitration circuit coupled to the single port receive memory, which arbitrates access by the plurality of communication ports and the data routing port to the single port receive memory.

Abstract: It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started.

Abstract: A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first device when it is determined that the first device should release the bus.

Abstract: A processor used in a synchronous data transfer system in which a processor, a direct memory access controller and peripheral devices are connected to a memory via the same bus, includes a detection circuit for detecting whether the processor uses the bus in a forthcoming cycle, and a control circuit having a first terminal for acknowledging a request signal from the direct memory access controller requesting a use of the bus, only when the detection circuit detects that the processor does not use the bus in the forthcoming cycle, wherein the control circuit discards a right to use the bus and outputs a response signal to the direct memory access controller indicating that the processor grants the right to use the bus to the direct memory access controller, when the request signal is acknowledged.

Abstract: Th present invention coordinates access to a shared resource, comprised of a plurality of segments, between a first device and a second device using an index and count mechanism. The present invention includes a respective descriptor, for each of the plurality of segments. Entries to the respective descriptors of the segments are maintained by the first device to inform the second device of activity between the first device and the shared resource. The present invention also includes a descriptor queue register, coupled to the first device and the second device. The first device writes an index into the descriptor queue register for indicating a starting descriptor of a corresponding segment that is available to the second device for access. The first device also writes a count into the descriptor queue register for indicating a subsequent number of descriptors, from the starting descriptor, of any corresponding segments that are available to the second device for access.

Abstract: A bus arbiter capable of avoiding needless increase in circuit scale is provided. The bus arbiter controls a bus shared by a CPU (central processing unit) and a plurality of apparatuses for generating addresses. The bus arbiter includes a determination unit for determining if a request of an address is a request of an address where no corresponding device is present, and a processor for passing the request by transmitting an ACK signal without performing a writing operation for a request of a writing operation, and transmitting dummy data and an ACK signal without performing a reading operation for a request of a reading operation, when the determination unit has determined that the request is a request of an address where no corresponding device is present.

Abstract: An input/output controller apparatus has a CPU arranged for directing an FPGA to generate a desired trace logic circuit and a channel controller to start communication with a host system. The channel controller while performing the communication with the host system delivers a channel sequence number via a buffer to the FPGA. In response, the FPGA saves the channel interface signal and the channel sequence number at given timing. When an error occurs during the communication, the CPU identifies the cause of the error by reviewing the channel interface signal and the channel sequence number saved in the FPGA. If the cause of the error fails to be identified, the FPGA is directed to generate another trace logic circuit suited for identifying the cause of the error.

Abstract: A multimedia system including a PCI bus master controller for transferring concurrent and independent video and audio data streams to video and audio devices. The controller includes a video request and DMA channel, a video sub-picture request and DMA channel, an audio request and DMA channel, and a decompressed video DMA and posted request channel for independently and concurrently transferring the data streams from host memory to the devices. The host processor builds lists of request packets in system memory and asynchronously submits the request packets to the controller. The request packets include commands which the request channels execute. The commands may include spinning on status conditions in registers of the multimedia devices, writing to registers of the devices, or performing bus master transfers of multimedia data streams from system memory to the devices. The device register accesses are performed by the controller on local buses thereby reducing PCI bus traffic.

Abstract: An apparatus and method of assigning communication channels for transmitting data through a host bridge are provided. In a preferred embodiment, a determination is made as to whether data is being transmitted through any one of the channels. If data is not being transmitted through one the channels, that channel is designated as the transmission channel for the present data transaction. If data is being transmitted through all of the channels, a least most recently used channel is selected as the data transmission channel. If however, more than one channel is not transmitting data, the data transmission channel assignments are made among the idle channels from a lowest channel number (e.g., channel 0) to a highest channel number (e.g., channel 7) or vice versa.

Abstract: A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit on each of the first and second communication links between each of the first and second ports and the first and second data storage devices, the bypassing means being operable to bypass the host computer by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.

Abstract: A computer system having interrupts synchronized to data storage by having an interrupt data signal (interrupt packet) follow the path of the data to an interrupt receiver, which interrupts the processor to execute an interrupt service routine. Rather than having a dedicated interrupt line from a peripheral device to a processor, the peripheral device sends the interrupt across a bus from the peripheral to the processing unit via an interrupt receiver.