Abstract: A method and apparatus for sending data. One exemplary embodiment may be a method comprising sending a data rate synchronization pulse from drive controller in a computer system to a storage device controller, calculating a bit transfer period by the storage device controller based on the time duration of the data rate synchronization pulse, serially driving a plurality of bits from the drive controller at a rate based on the bit transfer period, and sampling at the rate based on the bit transfer period to receive the plurality of bits by the storage device controller.

Abstract: A short message service (SMS) flood control routing node includes an SMS flood control module that receives short message service messages, determines the presence of short message service flooding, and takes appropriate action, such as discarding short message service messages that result in flooding. The presence of short message service message flooding may be determined by maintaining a count of short message service messages addressed to a particular called party within a time period. If the count exceeds a threshold, the short message service message that caused the count to exceed the threshold may be discarded. The routing node may generate a message the originator of a short message service message flood and/or to an enforcement agency.

Abstract: A bridge for interconnecting a processor to a peripheral device by way of a PCI bus may have a read buffer. The bridge autonomously requests data from the peripheral device and places received data in the read buffer. The processor reads the data from the receive buffer. The bridge may have a write buffer. The bridge accumulates data in the write buffer until a triggering event occurs. Upon the occurrence of a triggering event the bridge sends the data in the receive buffer to the peripheral device in a burst.

Abstract: A method for selectively inserting cache entries into a cache memory is proposed in which incoming data packets are directed to output links according to address information. The method comprises the following steps: a) an evaluation step for evaluating for each incoming data packet classification information which is relevant to the type of traffic flow or to the traffic priority to which the data packet is associated; b) a selection step for selecting based on the result of the evaluation step whether for the data packet the cache entry is to be inserted into the cache memory; c) an entry step for inserting as the cache entry into the cache memory, in the case the result of the selection step is that the cache entry is to be inserted, for the data packet the address information and associated output link information.

Abstract: In a device and method for controlling packet flow, priority data of a packet received by one of a plurality of ports are determined. A packet memory is monitored to determine whether an address pointer of the packet memory exceeds a predetermined limit value. A port is selected to control packet flow by using the priority data when the address pointer of the packet memory exceeds the predetermined limit value. Then, the selected port is directed to control the packet flow. By using the priority data designated to a packet or a port, the packet flow may be controlled in consideration of various kinds of network services.

Abstract: A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

Abstract: A system and method for low impact backup. In one embodiment, a method may comprise monitoring utilization of a system resource and a data management process selectively performing I/O operations dependent upon the monitored utilization of the system resource. The data management process may include functionality to backup desired data from a storage medium to a backup medium. In one particular implementation, the I/O operations may be allowed to be performed in response to the utilization of the system resource falling below a predetermined threshold. In another embodiment a method may comprise performing a plurality of I/O operations to complete a data management process executed by an application. The application separates said plurality of I/O operations with intermittent delays to achieve time-slicing of the data management process with respect to one or more other applications.

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

Abstract: A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.

Abstract: In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU.

Abstract: A method for managing read and write data congestion in a system for executing write and read data commands and having a buffer pool of blocks for temporarily storing read and write data is disclosed. Management of the buffer pool and the initiation of read and write commands ensures that free blocks are available to temporarily store read data arriving at a host bus adapter (HBA). If the currently available blocks would be substantially consumed by the total outstanding inbound read data requested, no more write data commands will be initiated. As inbound read data is received into the buffer pool and subsequently transferred out of the buffer pool to the initiator device, the blocks in the buffer pool are freed up. When the read data transfer is completed and sufficient buffer resources have been freed up, read and write data commands may resume.

Abstract: A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register stores a control parameter that specifies a drive strength adjustment to the signals to transmit over the plurality of conductors to the memory device using the transmitter.

Abstract: A system and method for supporting character interactive input/output operation in a half-duplex block-mode environment including a workstation and a server. Keystrokes at the workstation received into an auto enter, non-display entity on the workstation display are automatically transferred as entered from the workstation to a server application which processes the keystroke and responds in a manner appropriate to the context of the application.

Abstract: A method of merging a first data stream with a second data stream to generate a third data stream. The method comprises receiving a first packet from the first data stream, the first packet containing a first packet ID and a first data payload and receiving a second packet from the second data stream, the second packet containing a second packet ID and a second data payload. The method also includes storing first data in a plurality of packet ID arrival registers, a first portion of the first data indicating that the first packet ID is equal to the ID associated with a first of the plurality of the packet ID arrival registers and storing second data in the plurality of packet ID arrival registers, a first portion of the second data indicating that the second packet ID is equal to the ID associated with the second of the plurality of the packet ID arrival registers.

Abstract: A network device includes a group of queues, each having a weighted round robin mechanism. The priority queues on a port detect an overflow condition and transfer a flag to the weighted round robin device in response to detecting the overflow condition. The weighted round robin mechanism adjusts the weight associated with one or more of the priority queues in response to receiving the flag and transfers data from the queues based on the adjusted weights.

Abstract: A method and architecture optimizes transaction ordering in a hierarchical bridge environment. A parent-bridge is one level above a child-bridge, which in turn is one level above a grand-child component. The parent-bridge is a bridge-bridge. The child-bridge can be a bus-bridge or a bridge-bridge. The grand-child component can be a bus, a bus-bridge or a bridge-bridge. A parent-bridge is connected to a child-bridge via child-links, the child-bridge connected to grandchild-links, and the parent-bridge having multiple transaction order queues (TOQs) per child-link. Ideally, the parent-bridge has one TOQ for each grandchild-link where the parent-bridge applies separate transaction ordering for each of the grandchild-links. However, at a minimum, the system uses at least two TOQs per child-link, and as such, provides a higher level of transaction throughput than systems using one TOQ per child-link. The child-bridge sends a signal to the parent-bridge identifying from which grandchild-link a transaction was sent.

Abstract: An intelligent volumetric module for use in metering pressurized syrup to a drink dispenser machine comprises a solenoid driven metering system for controlling liquid flows from a pressurized syrup container and a controller for controlling operation of said solenoid driven metering system according to uniquely addressed instructions received from the drink dispenser's system controller. The controller comprises a self-addressing capability, wherein serial communication to all but one non-addressed volumetric module is disrupted while a first address is assigned to that one module. Communication is the enabled along a serial bus to a next non-addressed module, to which a second address is assigned. The process continues until each volumetric module is assigned a unique address and connected to the serial communication bus.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a plurality of flow controllable queues containing data to be transmitted. The queues are organized by flow. The apparatus also includes a plurality of destinations to receive data from the plurality of queues. The apparatus further includes a controller to continually maintain an aggregate count of data ready for transmission to the destinations and determine next queue to transmit data from based at least partially on the aggregate counts.

Abstract: An automatic flow control mechanism that supports two modes of automatic flow control is provided in a network interface. In the first flow control mode, the network interface periodically compares the number of available receive descriptors with low and high threshold values. When the number of available receive descriptors falls below the low threshold value, the network interface sends a PAUSE frame requesting the link partner to suspend its transmission (in a full-duplex mode), or enables the back pressure mechanism (in a half-duplex mode).

Abstract: A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the master device. The plurality of values includes a first value that specifies a transmit timing adjustment to the second signal to transmit to the master device by the transmitter.

Abstract: In general, in one aspect, the disclosure describes an apparatus for selecting a queue from a plurality of queues. The apparatus includes a hierarchal queue occupancy device to indicate an occupancy status of the plurality of queues, a next queue selector to select a queue based on said hierarchal queue occupancy device and a most recently serviced queue, and a queue identification register to identify a most recently serviced queue.

Abstract: A PLC system construction support tool is provided wherein a display 31 of text and numeric values is produced at the left of a paste board 22. The display 31 is provided for each row of a system and whenever a unit is added or deleted, the numeric values are updated. The display 31 contains a character string of “WIDTH” meaning the total length of the units on the corresponding row and the numeric value of the width (mm units), a character string of “CURRENT CONSUMPTION” meaning the total current consumption of the units on the corresponding row and the numeric value of the current consumption (mA units), and a character string of “WEIGHT” meaning the total weight of the units on the corresponding row and the numeric value of the weight (g units).

Abstract: The stream processor of the present invention includes: a selection section and first to fifth processing sections. In the selection section, a plurality of inputs are associated with a plurality of outputs according to control from outside so that streams sent to the plurality of inputs are passed to the associated outputs. The first processing section sends a first stream to the first input among the plurality of inputs. The second processing section sends a second stream to the second input among the plurality of inputs. The third processing section receives a stream from the first output among the plurality of outputs. The fourth processing section receives a stream from the second output among the plurality of outputs. The fifth processing section receives a stream from the third output among the plurality of outputs, subjects the received stream to predetermined processing, and sends the processed stream to the third input among the plurality of inputs.

Abstract: The present invention comprises a method and apparatus for selectively providing pre-emphasis to the output of a first driver during an initial portion of certain data transitions while transmitting data along a data bus from a source to a destination, with the certain data transitions being determined as a function of the content of the history of prior transmitted data cells. In the preferred embodiment, a pre-emphasis driver is connected in parallel to a normal driver and the pre-emphasis driver is activated preferably during the initial portion of a data transition to provide pre-emphasis in response to a control signal being applied to the pre-emphasis driver. The preferred embodiment of the present invention also comprises a sequence detector and control for monitoring the data cells or bits that are inputted to the normal driver to provide a history of the voltage levels of the data bits that are input to the normal driver.

Abstract: A system for handling data representative of audio/video information in a conferencing device. The system comprises a set of modules and subsystems for processing the data. The system further comprises at least one channel for transferring processed data between selected ones of the modules and subsystems, the at least one channel having a first buffer list associated therewith. Additionally, a work routine called by the at least one channel is configured to remove a buffer from the first buffer list and to send the buffer to an output routine called by the at least one channel.

Abstract: A buffer is provided with a CBW area (a randomly accessible command storage area) and an EP1 area (data storage area set to FIFO), when a CBW and data are allocated as informations to be transferred through one end point EP1. When a phase switches from a USB command phase (command transport) to a data phase (data transport), the information write area is switched from the CBW area to the EP1 area and OUT data transferred from the host to the end point EP1 is written into the EP1 area. The area switches from the CBW area to the EP1 area on condition that an acknowledgment has returned to the host in the command phase. In case of a toggle missing, area switching does not occur even if ACK is returned.

Abstract: A system and methods are shown for generating a transport stream. An application reads a transport stream file stored in memory. The application provides access to the transport stream file to a graphics card using a multimedia peripheral port (MPP). The MPP is used to provide data from the transport stream file to a transport stream demultiplexer. The application determines a desired transmission rate from the data present between program clock references in the transport stream file. The application suspends transmissions to the transport stream demultiplexer to allow a transmission bit-rate to match the desired bit-rate. The application also suspends transmission when the receiving transport demultiplexer determines its buffers are nearly full.

Abstract: In one embodiment, a method may include, if an amount of data requested to be transferred by a data transfer request according to a first protocol exceeds a maximum data transfer amount permitted to be requested by a single data transfer request according to a second protocol, generating one data transfer request according to the second protocol and a data structure, and modifying, at least in part, another data structure. This data transfer request may request transfer of a portion of the data. The data structure may include one or more values identifying, at least in part, another portion of the data. The modifying may be based, at least in part, upon the one or more values. The other data structure may include, prior to being modified, one or more other values indicating, at least in part, one or more parameters of the one data transfer request.

Abstract: An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.

Abstract: A mobile station includes an RF transceiver and a user interface. The mobile station further includes a plurality of data processor cores each having a first interface supporting a first bus coupled to an associated one of a plurality of program memories, a second interface supporting a second bus coupled to a common data memory, and a third interface supporting a third bus coupled to at least one input/output device. Each of the first, second and third buses include an address bus that is sourced from the processor core and a data bus. The plurality of data processor cores may be contained within a single integrated circuit package, such as an ASIC, in a System on Chip (SoC) configuration. In this case a first processor core may function as a CPU for controlling the overall operation of the mobile station, including the user interface, while a second processor core functions as a DSP for controlling operation of the RF transceiver.

Abstract: A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one potential load of data is predicted based on the load access pattern. In response to the prediction, the data is prefetched from a system memory to a cache before a DMA command requests the data.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: Various embodiments of systems and methods for implementing a streaming I/O protocol are disclosed. In some embodiments, a method may involve: receiving a packet initiating a streaming write operation, where the packet indicates that the size of the streaming write is larger than the size of the packet; initiating a write access having a size larger than the size of the packet to a storage device; receiving subsequent packets included in the streaming write operation; and writing data received in the subsequent packets to the storage device as part of the write access initiated in response to the earlier packet. In some embodiments, streaming read operations may also be supported.

Abstract: In general, in one aspect, the disclosure describes an apparatus capable to select a queue. The apparatus includes a queue occupancy device to indicate an occupancy status of the queues, a queue occupancy cache to record an update in occupancy status of a particular queue, a next queue selector to select a queue based on said queue occupancy device and a most recently serviced queue, and a queue identification register to identify a most recently serviced queue.

Abstract: A read-write interface system and method for a peripheral device includes storing data to be processed by a peripheral device; receiving a set of input data bits; transferring the set of input data bits from the shift register to the latch circuit in a write operation; accessing a leading bit of the set of input data bits from the latch circuit in advance of a read operation; and enabling in a read operation the rest of the input data bits in the latch circuit to be transferred to the shift register to be output with the leading bit.

Abstract: A method and apparatus optimizes the speed and efficiency of data transfer between two devices having different data input/output rates. In one embodiment, the present invention is directed to a computer software driver or hardware apparatus that may work with any port and/or network. The driver has a calibrator portion for optimizing data transfer between a CPU and a peripheral. The calibrator portion includes a data input/output rate profiler. The profiler preferably sends run-time data samples to the peripheral, builds a table that relates each data sample to an aggregate data transfer rate, and selects the optimum result as a model for further data transfer. A preferred method for performing the present invention is also included.

Abstract: A variable size first in first out (FIFO) memory is provided. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.

Abstract: A method for further processing data recorded on a computer arranged in a computer network. A quantity of data is recorded on the computer and stored in a memory. A quantity of supplementary data describing a property of the quantity of is generated centrally or peripherally in real time and stored. This quantity of supplementary data is used to specifically access or extract a selected quantity of the quantity of data recorded and stored.

Abstract: Provided are a method, system, and program implemented by a device driver executing in a computer for handling interrupts from an associated device, wherein the device driver is capable of interfacing with the associated device. The device driver receives a call requesting whether an interrupt received from a device is from the associated device and reads interrupt status information in memory within the computer to determine whether the associated device transmitted the interrupt, wherein the device writes the interrupt status information to the memory. If the associated device transmitted the interrupt, then the device driver requests resources from the operating system to handle the interrupt.

Abstract: An information processing apparatus having a common storage accessible by a host includes: an NIC group connected with a plurality of communication paths connected to the host; an I/O processing unit for executing I/O processing of the common storage in response to an I/O request of the host; a storing unit for holding log information for each data transfer performed from/to the host; and a communication path selection unit for selecting, as a data transfer path, a communication path having actually indicated good I/O processing performance among communication paths used in the past data transfer approximate in a communication condition by referring to the log information held by the storing unit.

Abstract: A network switch includes network switch ports, each including a port filter configured for detecting user-selected attributes from a received layer 2 frame. Each port filter, upon detecting a user-selected attribute in a received layer 2 frame, sends a signal to a switching module indicating the determined presence of the user-selected attribute, for example whether the data packet has a prescribed priority value. The network switch includes a flow control module that determines which of the network switch ports should output a flow control frame based on the determined depletion of network switch resources and based on the corresponding priority value of the network traffic on each network switch port. Hence, any network switch port that receives high priority traffic does not output a flow control frame to the corresponding network station, enabling that network station to continue transmission of the high priority traffic.

Abstract: A method and system that enables customized computer machines to be more readily developed by removing the function of resource translation out of the hardware abstraction layer (HAL). A machine manufacturer describes a machine in firmware, such as accordance with the Advanced Configuration and Power Interface (ACPI) specification, using ACPI machine language (AML). Operating system components such as a Plug and Play (PnP) manager in the kernel, in conjunction with an ACPI driver, interpret the description information and locate resources (bus bridges) for which translation is needed. For any arbitrary bus architecture or CPU to PCI bridge implementation that can be expressed, e.g., in ACPI firmware, the invention provides a translator external to the HAL. In one implementation, a PnP driver communicates with the ACPI driver and various drivers in driver stacks via I/O request packets (IRPs) to look for resource translators.

Abstract: A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.

Abstract: An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.

Abstract: Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory locations divided into memory pages, where each memory location has a row address and a column address; a row decoder connected to the memory array for selecting a row address in the memory array; a column decoder connected to the memory array for selecting a column address in the memory array; and a multi-sequence address generator for generating addresses, where the multi-sequence address generator has a burst mode and in burst mode generates one of two or more burst sequences of addresses according to received burst parameters, and where each sequence has an index indicating the separation between two addresses in the sequence.

Abstract: A peripheral communications protocol hub includes an input device such as a keyboard or remote cursor control wirelessly connected to a host computer. The input device has a number of connectors for connection of peripherals to the input device. The connection of input device to peripheral may be wired or wireless.

Abstract: A bus interface circuit arrangement and method. In various embodiments, a bus interface circuit arrangement interfaces with a bus functioning in accordance with a bus protocol. The bus interface circuit arrangement includes a bus interface circuit having a port arranged to be coupled to the bus. The bus interface circuit provides physical and link layers of the bus protocol. A bus processing block, implemented with a programmable device, is coupled to the bus interface circuit and is configured to perform selected processing in response to selected bus messages. A filter circuit, also implemented with a programmable device, is coupled to the bus interface circuit and to the bus processing block. The filter circuit is configured to direct bus messages to a selected one of the bus interface circuit and the bus processing block responsive to a code in the bus message.

Abstract: An apparatus for monitoring the state of computer system resources. According to the invention, the apparatus includes bus interface logic and a queue. The bus interface logic is used to interface with a serial bus and parse a bitstream through the serial bus into a command and an address. Also, the apparatus includes bridge logic, an arbitrator and a decoder. The decoder is used to decode the command. If the command represents a predetermined request for access to a resource bus, the decoder passes the predetermined request associated with the address to the queue. Whenever the predetermined request occurs, the arbitrator grants the resource bus to the predetermined request and allows the queue to output the predetermined request as well as the associated address. The bridge logic is provided to transfer data to and from computer system resources according to the predetermined request and the address.

Abstract: A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

Abstract: The SCSI control block interface provides for distributed processing of storage commands that provides transports and processing blocks the ability to interconnect with each other independent of the underlying transport or hardware architecture. The interface receives a SCSI control block from a transport and determines a storage command associated with the SCSI control block. Based upon the storage command, a particular processor that processes the storage command is determined. The SCSI control block is routed to the appropriate processor for processing. After processing, the SCB is routed to a transport for delivery.