Abstract: A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a memory address(es) are scanned into a control scan chain from a maintenance system. When the scan is complete, the information is collectively transferred to an access register bank. Based on the control signals, a selection multiplexer selects the information from the control scan chain provided by the maintenance system as opposed to standard signals generated by the computer system. Memory control input signals are generated in response to a clock trigger signal, and the read or write data transfer is initiated.

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract: A method according to one embodiment may include determining, at least in part, by an intermediate device at least one communication protocol via which at least one storage device connected to the intermediate device is capable of communicating. In this embodiment, the intermediate device may be capable of controlling, at least in part, by the intermediate device, at least one data stream coming from the at least one storage device in accordance with at least one communication protocol. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: Methods and apparatuses in which a throughput of a circuit is determined, the throughput is compared to a predetermined value; and the circuit is controlled so as to adjust the throughput in a manner that depends upon an outcome of the comparison.

Abstract: System and method for reacting to an expected impact involving a vehicle including an anticipatory sensor system for determining that an impact involving the vehicle is about to occur prior to the impact and an impact responsive system coupled to the sensor system and actuated after its determination of the expected impact. The sensor system includes wave receivers spaced apart from one another, each receiving waves generated by, modified by, or reflected from a common object exterior of the vehicle. The impact responsive system attempts to reduce the potential harm resulting from the impact and can be a protection apparatus which protects a vehicular occupant or a pedestrian, such as one including an airbag and an inflator for inflating the airbag.

Abstract: The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

Abstract: An embodiment of the present invention is an efficient interconnecting bus. A first clock source generates a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device. The device has a second clock source to generate a second clock signal at a second frequency synchronized with second data when the device transmits the second data. The first and second data each forms a packet being one of a posted, completion, and non-posted packets. The first and second frequencies are independent of each other and bounded within first and second frequency ranges, respectively. A queue structure stores packets used in a credit-based flow control policy.

Abstract: An apparatus for expanding I/O is described in which no additional strobes or enable lines are necessary from the host controller. By sequencing data in a specific way when output to two existing data or select lines, an expansion I/O device can generate a strobe or enable signal internally. This internal strobe or enable signal is then used to store output data or enable input data. The host controller needs software or firmware to perform the data sequencing, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.

Abstract: A method and system for pre-empting a low-priority traffic with high-priority traffic over a serial link utilizes special codes to delimit a high-priority message embedded within a low-priority message.

Abstract: Disclosed is a method and circuit for synchronizing dual data buses. In one embodiment, the method includes a receiving circuit receiving first and second streams of multibit data portions transmitted via first and second parallel data buses, respectively, coupled thereto. The receiving circuit compares first-stream multibit data portions with a first predefined multibit data portion to identify a first-stream multibit data portion that matches the first predefined multibit data portion. The receiving circuit stores into a first FIFO, all first-stream multibit data portions that follow the identified first-stream multibit data portion. The receiving circuit also compares second-stream multibit data portions with a second predefined multibit data portion to identify a second-stream multibit data portion that matches the second predefined multibit data portion.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: An information terminal disclosed herein includes a data storage in which data is stored; an internal controller which accesses the data storage by a request from inside the information terminal; and an external controller which accesses the data storage by a request from outside the information terminal. If a request that the internal controller access the data storage is generated while the external controller is accessing the data storage, then the external controller repeatedly transmits a negative reply that data has not been properly received in response to access from the outside and the internal controller accesses the data storage while the external controller repeatedly transmits the negative reply.

Abstract: A transfer apparatus receives, from a controller, a bit string including a plurality of individual data addressed to plural input/output units. The bit string is divided into data fragments. The data fragments are specified as corresponding to a target input/output unit. The specified data fragment is processed without performing a bit shift operation, and transmitted to the target input/output unit as a target data fragment. The input/output unit receives and stores template information that indicates an area within the target data fragment where the individual data is stored. The individual data is extracted from the target data fragment based on the template information.

Abstract: Apparatus, methods and systems for controlling data flow between data processing systems. In an example embodiment, the apparatus includes descriptor logic for generating a plurality of descriptors including a frame descriptor defining a data packet to be communicated between a location in the memory and a data processing system, and a pointer descriptor identifying the location in the memory. The apparatus also includes a descriptor table for storing descriptors generated by the descriptor logic for access by the data processing systems.

Abstract: A dynamic network interface is described, intended to enable the efficient processing of received data within a computer network by a target computer system by reducing excessive copying of the received data prior to being accessed by a network software application.

Abstract: One embodiment of the present method and apparatus adaptive in-operator load shedding includes receiving at least two data streams (each comprising a plurality of tuples, or data items) into respective sliding windows of memory. A throttling fraction is then calculated based on input rates associated with the data streams and on currently available processing resources. Tuples are then selected for processing from the data streams in accordance with the throttling fraction, where the selected tuples represent a subset of all tuples contained within the sliding window.

Abstract: Disclosed are a method, upstream processing node, and computer readable medium for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. The further includes determining that an input data flow rate of at least one upstream processing element varies. The computing resource is dynamically allocated to the upstream processing element in response to the input rate of the upstream processing element varying. Data flow is dynamically controlled between the upstream processing element and at least one downstream processing element.

Abstract: A method for handling data between a clock and data recovery system CDR and a data processing unit DP of a telecommunications network node TNN of an asynchronous communications network, using a bit rate adaptation circuit BAS, the bit rate adaptation system BAS including a memory unit MEM with a write process circuit Wp controlled by the recovered clock Rclk and a read process circuit Rp controlled by the local clock Lclk where the bit rate adaptation system BAS also includes a pointer synchronization controller PSC which, depending on the data detected on the input data signal DIb1 of the bit rate adaptation system BAS, sets the read and write pointers to a fixed initial address value. A Clock and Data Recovery system and a telecommunications network node TNN of an asynchronous network, which include a bit adaptation circuit BAS according to the invention, are also disclosed.

Abstract: A method of controlling an access time for accessing a flash memory comprises comparing a target address of the flash memory with an address of the flash memory that was previously accessed; setting the access time for the flash memory to be a first access time if the target address does not correspond to the same page of the flash memory as the previous address; and setting the access time for the flash memory to be a second access time if the target address corresponds to the same page of the flash memory as the previous address, the first access time being greater than the second access time.

Abstract: An electronic control unit has two microcomputers. Each microcomputer has a data buffer storing data first to be transmitted in every 8 ms, a second data buffer storing data to be transmitted in every 16 ms, and a third data buffer storing data to be transmitted in every 16 ms and being different from the first and second data buffers. The microcomputer transfers at the transmission timing of every 8 ms data in the first data buffer to the transmitting buffer, while it transfers alternately the data in the second data buffer and the data in the third data buffer to the transmitting buffer. The microcomputer also transfers an ID that indicates content of the present transmitting data to the transmitting buffer.

Abstract: Presented herein is a scheme for reducing the likelihood of erroneous DQS signals. Logic is incorporated proximate to a memory controller and receives a signal indicating a read request and a DQS signal from a memory module. The logic transmits a signal indicating the presence of data, based on the timing relationship between the DQS signals and signal indicating read requests.

Abstract: A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system removes packets including a packet header and packet data from a packet buffer. The packet buffer is arranged into a plurality of packet buffer memory slots, each slot comprising a descriptor status array location including an availability bit set to “used” or “free”, and a packet buffer memory location comprising a descriptor memory slot and a data segment memory slot. The descriptor memory slot includes header information for each packet, and the data segment memory slot includes packet data. The memory controller operates on one or more queues of data, and data is placed into a particular queue in packet memory determined by priority information derived from incoming packet header or packet data.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. Channel control logic controls transfer of data through the DMA channels in response to parameters contained in at least one DMA descriptor having a programmable format.

Abstract: Numerous shortcomings exist in prior generation adapter cards for supporting remote consoles for multipartition computer systems. Emulation using memory in the adapter card supports some remote functions so that they appear to be resident on the host computer system to each partition. Additionally, the host computer system memory can be used in one mode to support the emulation of extended mode video console support functions. Scoreboarding and hardware compression are used to limit the volume of data required to be updated to support the emulation.

Abstract: Aspects for high speed USB data routing are presented. The aspects include routing a data stream to and from USB I/O ports serially, and maintaining a frequency of the data stream during the routing. Additionally, a root port router is provided for the root port and a data port router is provided for each I/O port, wherein each data port router delays the data stream by one bit during the routing.

Abstract: A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.

Abstract: A touch sensing apparatus is provided. A preferred embodiment of a touch sensing apparatus includes a sensor (13), an MCU (15), and an integration circuit (14). The sensor is for receiving electricity signals from an object that touches the sensor. The MCU (Microcontrol Unit) has a signal output port A and a signal input port B. The signal input port is connected to the sensor. The integration circuit interposes between the signal output port and the signal input port of the MCU. The signal output port outputs AC signals to the signal input port through the integration circuit. The integration circuit prolongs active transition times of the AC signals, and the MCU identifies a touch on the sensor when the active transition times of the AC signals fall in a predetermined range and accordingly implements a predetermined function.

Abstract: A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.

Abstract: In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of flow control and extended burst transfers are described.

Abstract: The present invention provides a method and computer program product for reading an encoded cable speed/length value contained within an interconnection cable to set the interconnection speed of two or more components connected by the interconnection cable within a computing environment. This method detects changes to the cable connections within the I/O fabric of the computing environment, and autonomically reconfigures the connected components to enable the interconnected devices to communicate at the maximum effective bandwidth, based on the length of the interconnection cables utilized.

Abstract: In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the occupancy level of data in the receiving buffer and the vacancy level of data in the transmitting buffer are determined. Access to the system bus is granted based on the determination result. Buffers in the transmitting and receiving paths are treated as a single virtual transmitting buffer and a single virtual receiving buffer, respectively. Bus priority is determined by the data occupancy level in each virtual buffer and any change in the occupancy level. Therefore, it is possible to prevent or reduce underflow of the transmitting buffer and overflow of the receiving buffer, thereby impartially arbitrating which of the buffers can access the memory.

Abstract: A method of transmitting data through an I2C router from a source port to a destination port, the method comprising: receiving data in a first I2C source port buffer of the I2C router; capturing the I2C destination port before the first I2C source port buffer has overflowed; and transmitting the data from the first I2C source port buffer to the I2C destination port while restricting transmission from the second I2C source port buffer to the I2C destination port.

Abstract: A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: A method and an apparatus are provided for loading data to a local store of a processor in a computer system having a direct memory access (DMA) mechanism. A transfer of data is performed from a system memory of the computer system to the local store. The data is fetched from the system memory to a cache of the processor. A DMA load request is issued to request data. It is determined whether the requested data is found in the cache. Upon a determination that the requested data is found in the cache, the requested data is loaded directly from the cache to the local store.

Abstract: Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case throughput rate (without use of SFBs) is computed, and maximization factor equaling a desired throughput rate divided by the worst case throughput rate is computed. A number of SFBs is determined as equaling one less than the maximization factor. By placing the SFBs at appropriate locations in the data transfer path, the desired throughput rate may be attained when transferring large volumes of data.

Abstract: The present invention provides for the scheduling of requests to one resource from a plurality of initiator devices. In one embodiment, scheduling of requests within threads and scheduling of initiator device access is performed wherein requests are only reordered between threads.

Abstract: Disclosed is a technique for throttling data transfer. An amount of resources that are in use is determined. When the amount of resources reaches a high threshold, one or more primary control units are notified to temporarily stop sending data. When the amount of resources reaches a low threshold, each previously notified primary control unit is notified to resume sending data.

Abstract: A fast with-in range comparator is implemented in digital logic. A packet arrives at a device for processing. Initial packet data that is available in a first read cycle, is used to compute data that is necessary for later cycles. The initial data and the subsequently data are then used to test a single value against a range of values. In a method of the present invention a range is separated into two ranges. An upper limit of the first range is tested to determine whether the value is below the upper limit. If this test fails, the value is tested to determine whether the value is between the upper limit of the first range and the upper limit of the full range. The ranges are tested by constructing a bit vector. Data representing the capability of a communicating port, is then used to index into the bit vector. The outcome of the index is a value that signifies whether the port can support the packet or not.

Abstract: In a transaction system, a dynamic batching process enables efficient flushing of data in a data buffer to a stable storage device. The transaction system uses constant values and dynamic values and a system performance history to adjust the rate of flushing data and also to adjust the amount of data flushed in each flush operation. The transaction system is able to respond to both spikes in rate of received transactions as well as more gradual changes in the rate of received transactions and to automatically adapt to stable storage device performance variations.

Abstract: Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media stream based on a sampling rate of the media stream. The mode of operation may be a wideband mode and/or a narrowband mode. Depending on the determined mode, the adaptive multimode media queue may be partitioned into a low band media queue and a high band media queue. A wideband media stream split into a high band and a low band is buffered into the adaptive multimode media queue wherein the high band is stored in the high band media queue, and the low band is stored in the low band media queue. The high band media queue and low band media queue may be a contiguous memory block within the adaptive multimode media queue. The received media stream, which may have different sampled data rates may be buffered within the partitioned adaptive multimode media queue.

Abstract: A method and system for monitoring frame flow in a Fiber Channel network is provided. The method includes, deleting fill words before any frame data is allowed to be stored in a buffer memory; storing only certain primitive signals and/or frame data in the buffer memory; reading the buffer memory without delay, if a primitive signal is stored in the buffer memory; and delaying reading the buffer memory if frame data is detected. The network includes, a host bus adapter that includes a fiber channel protocol manager that includes a receive logic that deletes fill words before any frame data is allowed to be stored in a buffer memory, wherein the buffer memory stores only certain primitive signals and/or frame data and the buffer memory is read without any delay, if a primitive signal is stored, while a read operation of the buffer memory involving frame data is delayed.

Abstract: An intelligent volumetric module for use in metering pressurized syrup to a drink dispenser machine comprises a solenoid driven metering system for controlling liquid flows from a pressurized syrup container and a controller for controlling operation of said solenoid driven metering system according to uniquely addressed instructions received from the drink dispenser's system controller. The controller comprises a self-addressing capability, wherein serial communication to all but one non-addressed volumetric module is disrupted while a first address is assigned to that one module. Communication is the enabled along a serial bus to a next non-addressed module, to which a second address is assigned. The process continues until each volumetric module is assigned a unique address and connected to the serial communication bus.

Abstract: A method and apparatus is described, by means of which a host data communication device obtains the effects of a desired data communication protocol, such as flow control, that may not be supported by a client device. To obtain the effects of the desired protocol, the host invokes a different protocol supported by the client, for example retransmission, by presenting an appropriate protocol-initiation signal, for example by asserting an error bit on a bidirectional connection to the client. Invoking the supported protocol repetitively, if necessary, the host interprets the client response to the invocation to achieve substantially the same effect as the desired protocol. Thus, a repetitive retransmission request by the host may have the effect of a flow hold request.

Abstract: Guaranteed, exactly once delivery of messages is disclosed. In one embodiment, there is a sender and a receiver. In a sender transaction, the sender does the following: receives a message from a sender queue; generates a substantially unique identifier and an expiration time for the message; and, saves the identifier, the expiration time, and the message in a sender database. The sender then sends the identifier, the expiration time, and the message to the receiver. In a receiver transaction, the receiver then does the following: receives the identifier, the expiration time, and the message from a receiver queue; determines whether the message has expired based on the expiration time and determines whether the message is present in a receiver database by its identifier; and, upon determining that the message has not expired and is not present in the receiver database, stores the message in the receiver database, and performs actions associated with the message.

Abstract: Provided are a method, system, and program for managing requests to an Input/Output (I/O) device. The I/O requests directed to the I/O device are queued and a determination is made as to whether a number of queued I/O requests exceeds a threshold. If the number of queued I/O requests exceeds the threshold, then a coalesce limit is calculated. A number of queued I/O requests not exceeding the calculated coalesce limit are coalesced into a coalesced /O request and the coalesced I/O request is transmitted.

Abstract: A memory management system adapted to process linked list data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of linked list files by the memories. The head and tail buffers and at any intermediate buffers of a linked list are written into the high speed memories. The intermediate buffers are immediately transferred from the high speed memories to said bulk memory while leaving the head buffer and the tail buffer of the linked list in the high speed memories. In read operations, the head and tail buffers are read from the high speed memories. The intermediate buffers are transferred from the bulk memory to said the high speed memory and then read from the high speed memories.

Abstract: A memory management system adapted to process large data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of data files by the memories. Large data files have a first part and an excess portion. Both parts of each file are written into the high speed memories. The excess portion of each file is immediately transferred from the high speed memories to the bulk memory while leaving the first part in the high speed memories. In read operations, the first part is read from the high speed memories. The excess portion is transferred from the bulk memory to the high speed memory in a burst mode and then read from the high speed memories.

Abstract: A computer system includes a system memory, a processor and a peripheral. The peripheral includes a peripheral memory, a circuit, a first interface to receive a packet and a second interface that is adapted to communicate with the system memory. The peripheral memory is adapted to store a table that includes entries that identify different packet flows. The circuit is adapted to use the table to associate the packet with one of the packet flows and based on the association, interact with the second interface to selectively transfer a portion of the packet to the system memory for processing by the processor.

Abstract: A dynamic network interface is described, intended to enable the efficient processing of received data within a computer network by a target computer system by reducing excessive copying of the received data prior to being accessed by a network software application.