Abstract: An apparatus for storing data includes a memory having minimum guaranteed amounts of storage corresponding to connections. The apparatus includes a mechanism for changing dynamically the minimum guaranteed amount during use. The changing mechanism is connected to the memory.

Abstract: A storage network control apparatus is operable to present virtualized storage to a host system and includes a monitoring component, an analysis component, a detection component, and a migration component. The monitoring component is for monitoring input/output (I/O) activity for virtual storage logical units over time. The analysis component is for identifying a repeating instance of peak I/O activity for a virtual storage logical unit over time and for generating a predictive signature therefrom. The detecting component is for identifying an instance of such a predictive signature. The migration component is responsive to the detecting component, and is for migrating data mapped by the virtual storage logical unit across additional real storage units to improve the I/O performance of the virtual storage logical unit prior to a recurrence of the repeating instance of peak I/O activity. A corresponding logic arrangement may be incorporated in hardware, software or a combination thereof.

Abstract: A circuit includes a high priority circuit and a non-high priority circuit. The high priority circuit is operative to communicate high priority information to a single path of a differential serial communication link. The non-high priority circuit communicates non-high priority information to the single path. The high priority information is communicated prior to the non-high priority information. In one example, the circuit includes a flow control distributor operatively coupled to the high priority circuit and the non-high priority circuit. The flow control distributor distributes a total number of flow control credits into high priority credits and non-high priority credits. The flow control distributor controls communication of the high priority information based on the high priority credits. The flow control distributor controls communication of the non-high priority information based on the non-high priority credits.

Abstract: Data is transferred from a terminal to a computer over a USB cable. This is accomplished when the terminal transmits a control signal to the computer through a control line of a USB cable based on a value stored in a terminal register unit. The computer receives the control signal, sets a value of the computer register unit, and generates an interrupt according to the value in the computer register unit. The computer executes a USB reception thread that receives data from the terminal. By controlling an operation of the USB reception thread of the computer through the control line and each register unit, a load applied to a kernel of the computer can be reduced.

Abstract: A data processor capable of preventing the occurrence of overrun, while efficiently performing DMA transfer. An SIO of a data processor starts the transmission of transmission data only when transmission data is stored in a transmission buffer and a reception buffer has no space available for data storage.

Abstract: A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The CPD provides a fast-path that avoids protocol processing for most large multipacket messages, greatly accelerating data communication. The CPD also assists the host CPU for those message packets that are chosen for processing by host software layers. A context for a message is defined that allows DMA controllers of the CPD to move data, free of headers, directly to or from a destination or source in the host. The context can be stored as a communication control block (CCB) that is controlled by either the CPD or by the host CPU. The CPD contains specialized hardware circuits that process media access control, network and transport layer headers of a packet received from the network, saving the host CPU from that processing for fast-path messages.

Abstract: A stream data control server includes: a processable flow rate managing unit which manages a processable flow rate corresponding to an amount of data per unit time, which can be processed in each of storage units serving as storing destinations; a classified data flow rate managing unit which manages a data flow rate corresponding to an amount of data processed per unit time for each class of data to which a data priority is attached; and a storing destination control unit which controls the storing destinations of respective data based upon the processable flow rate of each of the storage units and the data flow rate for each class in such a manner that the data having higher data priorities are stored in the storage units having higher priorities within a range of the processable flow rate of each of the storage units.

Abstract: A primary storage control unit receives an information unit from a remote host over a fibre channel connection. The primary storage control unit adjusts an information unit pacing parameter included in a response sent from the primary storage control unit to the remote host, wherein the information unit pacing parameter indicates the number of information units that the remote host is allowed to send to the primary storage control unit without waiting for any additional response from the primary storage control unit.

Abstract: A method for evaluating data transfer performance within a data recording apparatus is disclosed. The data recording apparatus includes a buffer and a recording medium. Initially, a Pause time P when data transfer between the buffer and a host being stopped temporarily is measured. Then, an ideal Pause time Y is determined. Next, a determination is made whether or not the Pause time P exceeds a sum of the ideal Pause time Y and an allowance a. If the Pause time P exceeds a sum of the ideal Pause time Y and the allowance a, a warning signal is sent to the host.

Abstract: A method of interacting with a speech recognition (SR)-enabled personal computer (PC) is provided in which a user SR profile is transferred from a wireless-enabled device to the SR-enabled PC. Interaction with SR applications, on the SR-enabled PC, is carried out by transmitting speech signals wirelessly to the SR-enabled PC. The transmitted speech signals are recognized with the help of the transferred user SR profile.

Abstract: A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

Abstract: The object of the invention is to create a router which has an enhanced processing speed. According to the invention, before access through a readout unit, the pointers for information packets stored in the buffer memory are arranged as required. If an overflow is imminent in a buffer memory area, for example, then individual pointers are selected and removed from the buffer memory area. The selected pointers are shifted into an additional buffer memory area, for example. This additional buffer memory area is then preferentially read out, so that the selected pointers are read out before the pointers in the buffer memory area. The criterion for the selection of a pointer is, for example, an expired reactivation time or a buffer memory area that is filled above a threshold value.

Abstract: A threshold mechanism is provided so that a producer and a corresponding consumer, executing on the same resource (e.g., CPU) are able to switch context between them in a manner that reduces the total number of such context switches. The threshold mechanism is associated with a buffer into which the producer stores packets up to a given threshold before the consumer is allowed to remove packets. The buffer has an associated upper limit on the number of packets that can be stored in the buffer. A flush empties the buffer of any remaining packets when no more packets are to be produced. This reduction in the total number of context switches in general leads to better performance at the cost of more latency.

Abstract: A computer-executed method for controlling transaction flow in a network comprises communicating transaction packets among a plurality of devices in a network fabric and subdividing a memory into a plurality of memory segments for storing received transaction cycles according to transaction packet type comprising posted, non-posted, and completion cycles. A plurality of transaction cycles are received in the memory segment plurality at a target device and transaction cycle priority is allocated according to transaction packet type wherein posted cycles have highest priority. Cycles are retrieved from the memory segment plurality in an order determined by priority.

Abstract: A method and apparatus are provided for managing dependencies between split command and data transactions. A command transaction is written into a command array. A data transaction is written into a data array. A marker is defined for both command transactions and data transactions, and a marked command counter is maintained. Marked data will not be sent unless the older commands have been sent. A data header is marked if the previous transaction written was a command, and a command is marked if the previous transaction written was data. The marked command counter maintains a count of marked commands sent relative to sending marked data.

Abstract: A processor prioritizes data traffic by limiting a number of data buffers that can be retrieved. By limiting the number of data buffers that can be retrieved, some packets are dropped on a receive side to save processing cycles that would be spent processing packets that may be dropped on the transmit side after processing.

Abstract: Keyboard, mouse and video (KVM) capture session architecture that includes command center forensics. That is, redirector hardware (HW) and a command center forensics (CCF) appliance. The redirector HW includes a computer interface module (CIM) with a computer readable encoded media. The CIM is configured to record at least one KVM session. The computer readable encoded media is configured to instruct sending an identical copy of the recorded at least one KVM session to the CCF appliance. The CCF appliance being configured to store and playback the identical copy.

Abstract: A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

Abstract: Method and system for a dynamic FIFO flow control circuit. The dynamic FIFO flow control circuit detects one or more obsolete entries in a FIFO memory, retrieves the address of the next valid read pointer, and reads from the retrieved address during the next read operation.

Abstract: The present invention is directed to providing configuration data to an EEPROM within a sealed enclosure without having to open the enclosure, using a Test Interface Card (TIC) connected to a particular external multi-use port on the enclosure. The present invention is generally applicable to any sealed enclosure containing a device that receives information through an internal serial bus, where the enclosure includes ports that have both high speed, low voltage connections and lower speed DC connections. DC blocking capacitors are placed on the high speed lines, and when a TIC is inserted into the multi-use port, a voltage detection circuit coupled to the high speed connections detects a DC control voltage, tri-states a Switch On a Chip (SOC) and configures switches to connect the lower speed connections to the serial bus and an EEPROM so that the TIC can supply new configuration data to the EEPROM.

Abstract: The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by t

Abstract: A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.

Abstract: Delivering data from a data input to a data output within a system includes selecting a system performance parameter to be optimized, receiving at the data input a sequence of discrete data words, determining an optimum mode of delivery of the data words to the data output so as to optimize the selected performance parameter, and delivering the data words from the data input to the data output in the determined optimum mode. The optimum mode of delivery may include at least one of an optimum time and sequence of delivery of the data words.

Abstract: Techniques are provided for processing data in real-time or near real-time using a processor. The processor passes the real-time input data directly to functional units via a bypass multiplexer without storing the data in memory. The functional units process the input data and provide output data. The output data of the functional units is transmitted outside the processor without being stored in memory. Alternatively, the output data of the functional units can be stored in memory in the processor. Input data that needs to be maintained in the processor for a period of time is stored in memory.

Abstract: A method according to one embodiment may include receiving data in a receive buffer, the receive buffer comprising a plurality of buffers, and sending a hold command to a transmitting node currently sending data to hold transmission of additional data when a level of the data in the receive buffer reaches a high threshold level. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: One embodiment of the present method and apparatus adaptive in-operator load shedding includes receiving at least two data streams (each comprising a plurality of tuples, or data items) into respective sliding windows of memory. A throttling fraction is then calculated based on input rates associated with the data streams and on currently available processing resources. Tuples are then selected for processing from the data streams in accordance with the throttling fraction, where the selected tuples represent a subset of all tuples contained within the sliding window.

Abstract: A device, arrangement and method may control bus request timing to disperse bus access timing, so that adverse effects of concentration-on-bus phenomenon may be avoided. The device may include a bus request signal generating circuit may generate a bus request signal under control of a counter, and a pulse signal generating circuit may generate a pulse signal as a function of a number of times the bus request signal generating circuit has generated a bus request signal and a first threshold value. The device may include a determining circuit and a control circuit. The determining circuit may generate a determination result representing whether a given process period for generating the bus request signal has ended as a function of the pulse signal. The control circuit may control the counter to adjust the process period for generating the bus request signal, based on the determination result.

Abstract: A computer program product and system for managing allocation of storage in a switch utilizing flow control are provided. The switch includes a plurality of ports and an internal storage divided into a plurality of storage units. The computer program product and system provide for monitoring an average number of storage units used by each of the plurality of ports over a predetermined time period, setting a threshold for the average number of storage units used by each of the plurality of ports, and allocating one or more available storage units assigned to a first port to a second port in response to storage allocation management being enabled for the second port and the average number of storage units used by the second port exceeding the threshold for the second port.

Abstract: An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.

Abstract: A system and method for supporting character interactive input/output operation in a half-duplex block-mode environment including a workstation and a server. Keystrokes at the workstation received into an auto enter, non-display entity on the workstation display are automatically transferred as entered from the workstation to a server application which processes the keystroke and responds in a manner appropriate to the context of the application.

Abstract: The present invention enhances the Direct Access Stimulus (DAS) interface presently employed within a logic simulation hardware emulator to provide alternative stimulus to signals internal to a model actively running on a logic simulation hardware emulator. The present invention accomplishes this by introducing a set of special logic within the logic model to provide an alternate source for selected signals, identifies the special logic so that it is subsequently connected directly to the DAS card interface, and adds information to a symbol table so that this special logic can be identified as signal accessible through the DAS card interface. At runtime, when the user control program accesses facilities that have been connected to the DAS card interface, a set of special routines automatically reference the symbol table information to access the special logic that is connected to the DAS card interface.

Abstract: Buffer-level arbitration is used to allocate released buffers, based on received flow control credits, between local packets and received packets on respective virtual channels in accordance with a determined insertion rate relative to a second number of received packets to be forwarded. Virtual channel arbitration also is performed to identify, from among the multiple virtual channels, the packets that should be sent next along the local and forwarded paths. Device arbitration is then performed to identify, from the insertion and forwarding paths, the packets that should be output onto an output transmission link, based on the determined insertion rate. Performing the arbitration at each step in accordance with the insertion rate maximizes packet bandwidth fairness among the multiple devices supplying packets across multiple virtual channels.

Abstract: There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

Abstract: Disclosed is a system and method for transmitting AV/C data over one or more transports. Further disclosed is a system and method for transmitting AV/C data over non-FCP communication media. The disclosed system and method includes an AV/C transaction delivery system which operates in conjunction with communicatively coupled AV/C protocol layers, AV/C transport layers, and AV/C transport controllers to effectuate transmission of AV/C transaction data without regard to protocol.

Abstract: A transfer start/end detecting section detects timing at which a DMARQ signal becomes an H level or an L level. A transfer time-measuring section measures a transfer time during which data transfer is actually performed within a period in which a predetermined number of data blocks are transferred. A transfer byte count-measuring section measures a transferred byte count of data that have successfully been transferred. An effective data transfer rate-computing section computes an effective data transfer rate by dividing the transferred byte count by the transfer time. A transfer rate-comparing section compares the effective data transfer rate with a transfer rate that is one step slower than a current transfer rate output from a selectable transfer rate-storing section. If the former is slower, a transfer rate-switching section switches to the transfer rate that is one step slower. A large decrease in the effective data transfer rate caused by data corruption is prevented.

Abstract: A communication system complying with SPI-4 Phase 2 standard includes a local device, an opposing device, a first data channel to transfer payload data from the local to the opposing device, a second data channel opposed to the first data channel, and a first status channel to be able to transfer data from the local to the opposing device. The local device periodically outputs buffer status information of a data buffer for storing payload data received over the second data channel to the first status channel. Further, the local device inserts the buffer status information between the payload data according to a priority of the buffer status information in order to output the buffer status information to the first data channel. The opposing device controls to output payload data to the second data channel according to the buffer status information received over the first status channel and the first data channel.

Abstract: Systems and methods for responding to a data transfer are disclosed. One embodiment comprises a method that includes the following steps: determining a sustainable data transfer rate for data transfers to/from an external memory medium, acquiring a data stream, transforming the data stream, and selecting a value for at least one operational parameter associated with acquiring or transforming the data stream in response to the sustainable data transfer rate.

Abstract: The present invention concerns a method and a system for data transmission and control based on Universal Serial Bus (USB). The system comprises a USB Master device and a USB Slave device. The USB Master device comprises a USB Master processor and a Data Storage connected to the USB Master processor. The Slave device comprises a USB Slave processor and a Data Consumer connected to the USB Slave processor. The USB Master processor is coupled with the USB Slave processor via a USB cable. The USB Master processor accepts requests from the USB Slave processor and reads data in the Data Storage connected to it, and then the data is sent to the USB Slave processor via the USB cable, and the USB Slave processor processes the data and transfers them to the Data Consumer for use.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.

Abstract: Circuits and methods convert parallel data into a serial data stream. A serializer according to the present invention generally includes a high speed section and a low speed section. The high speed section generally comprises a tree-based serializer configured to serialize an N-bit parallel data stream, where N is a power of two. The low speed section generally includes a data bank configured to load one or more samples of an M-bit parallel input stream, and a multiplexer configured to produce the N-bit parallel data stream from the data bank. The present invention advantageously provides high speed and relatively low power serialization of M-bit parallel data streams where M is not a power of two. In particular, the present invention advantageously provides high speed and relatively low power serialization of 10-bit parallel data streams.

Abstract: A dedicated processing module includes an input for data to be processed and an output for processed data. A block input and a block output are also included. A processing component for the module performs a digital processing operation on the data present at the data input and applies the processed data at the data output. The processor may further generate a block request. A control device within the module reproduces, at the block output, a block request applied to the block input or generated by the processing component. The control device thus may operate to block the application of processed data at the data output upon receipt of a block request at the block input. Two or more dedicated processing modules may be connected in series with each other to form a processing flow chain with the data output of one module connected to the data input of a subsequent module. Additionally, the block output of the subsequent module is connected to the block input of the preceding module.

Abstract: The present invention is directed towards reducing hard disk drive (HDD) activity by sharing the buffering activity between a provisional load sharing buffer (PLSB) and a time shift buffer (TSB). The HDD may be included in a digital host communications terminal (DHCT). Initially, the PLSB buffers initial streaming programs to accommodate for channel changes. Additionally, the streaming program is buffered in a standard definition quality regardless of the format of a connected television. Once a predetermined time has passed determined by the size of the PLSB without a channel change, the TSB begins buffering the streaming program. The TSB can then switch between buffering a high definition quality to a standard definition quality of a streaming high definition program depending on other factors to further decrease the HDD activity. Additionally, the TSB can be disabled to prevent buffering of the streaming program.

Abstract: Audio and visual information processing components are co-located on a PCI Express graphics card by communicating audio and visual information received through the PCI Express interface of the graphics card to a PCI Express switch which switches audio information to audio processing components and video information to video processing components for processing of the information to an audiovisual appliance output. The audio processing components may include an AC97 interface and CODEC or an audio controller that processes PCI Express information. The audiovisual output signal may include a variety of combined or separate audiovisual appliance compatible outputs such as coaxial cable output, EVC output, HDMI output, HDTV output or 1394 output.

Abstract: A system that includes a host and a peripheral device. The host transmits a packet that includes a command and a flow control field. The peripheral device receives the packet and has the ability to execute the command, wherein the peripheral device can determine whether the command can be processed in a timely manner, and can update the packet's flow control field with flow control data based on the determination. The host receives the updated packet and has the ability to adjust the flow control of subsequent packets to the peripheral device based on the flow control data in the updated packet.

Abstract: A method for processing a first input/output (I/O) request on a network attached storage (NAS) device that includes receiving the first I/O request from a source by the NAS device, placing the first I/O request in an I/O queue associated with the NAS device, wherein the first I/O request is placed in the I/O queue based on a priority of the first I/O request using a remote storage access protocol, and when the first I/O request is associated with the highest priority in the I/O queue, determining whether a bandwidth associated with the source of the first I/O request is exceeded, processing the first I/O request if the bandwidth associated with the source of the first I/O request is not exceeded, and placing the first I/O request in sleep mode if the bandwidth associated with the source of the first I/O request is exceeded.

Abstract: In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.

Abstract: A method according to one embodiment may include reserving a plurality of buffers having an aggregate capacity, receiving a frame having a size less than the aggregate capacity, and releasing at least one of the plurality of buffers that is unused to store the frame. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component to the apparatus for storing information utilizing the clock of the first component, a second component operated in response to the timing of a second clock, apparatus for utilizing the clock of the second component to transfer information from the apparatus for storing information in a condition in which it is synchronized for use by the second component whereby the information may be immediately utilized by the second component without the need for storage by the second component.