Abstract: A circuit for a storage device that communicates with a host device comprises a first high speed interface. A storage controller communicates with the high speed interface. A buffer communicates with the storage controller. The storage device generates storage buffer data during operation. The storage controller is adapted to selectively store the storage buffer data in at least one of the buffer and/or in the host device via the high speed interface. A bridge chip for enterprise applications couples the circuit to an enterprise device.

Abstract: A data transmission apparatus connecting to a network consisted of a plurality of data transmission apparatuses comprises a disconnecting device that disconnects a connection established between a transmission plug of a transmitting node and a reception plug of a receiving node, both nodes being connected to the network, an optimization requesting device that requests optimization of transmitting sequences to the transmitting node, a receiver that receives information about a transmission plug newly assigned to the transmitting sequence used by the transmitting nodes of which connection has been disconnected by the disconnecting device, the information being received as an answer for the optimization request from the transmitting node, and a connecting device that establishes a new connection between the newly assigned transmission plug and the reception plug of the receiving node of which connection has been disconnected by the disconnecting device.

Abstract: The system according to the present invention for data transfer between microcomputer devices contains a standard protocol controller, a generally known ethernet controller, for example, as a coupling device instead of the known multipart RAM. Instead of a parallel data connection, the microcomputer devices are coupled to one another via a standardized, serial data connection, for example, ethernet. Using functions of ethernet switches already known, a number of microcomputer devices in the system may be increased.

Abstract: A serial buffer having a plurality of virtual queues, which can be allocated to include various combinations of on-chip dual-port memory blocks, on-chip internal memory blocks and/or off-chip external memory blocks. The virtual queues are allocated and accessed in response to configuration bits and size bits stored on the serial buffer. Relatively large external memory blocks can be allocated to virtual queues used for data intensive operations, while relatively small and fast dual-port memory blocks can advantageously be allocated to virtual queues used for passing command and status information. The serial buffer provides an efficient and flexible manner for utilizing available memory, which not only minimizes the access latency but also provides a large amount of buffer space to meet different application needs.

Abstract: An embodiment of the present invention is an efficient interconnecting bus. A first clock source generates a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device. The device has a second clock source to generate a second clock signal at a second frequency synchronized with second data when the device transmits the second data. The first and second data each forms a packet being one of a posted, completion, and non-posted packets. The first and second frequencies are independent of each other and bounded within first and second frequency ranges, respectively. A queue structure stores packets used in a credit-based flow control policy.

Abstract: Apparatus and associated systems and methods may relate to a data traffic modification system that may include a processing module to handle SATA-compliant data transfers in which a source device or a target device issues requests to pause and subsequently to resume the data transfer. In various implementations, a data traffic modification device may selectively modify data traffic upon the occurrence of a predetermined condition. In one illustrative example, if a target device for the data transfer issues a pause request (e.g., to prevent a buffer overflow), the data traffic modification device may generate a pause acknowledge signal to the target device within a response time specified by the protocol. In another illustrative example, if a source device for the data transfer issues a pause request, the data traffic modification device may generate a pause acknowledge signal to the source device within the response time specified by the protocol.

Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: In a command output control apparatus, one of first and second storage areas that corresponds to the smaller number of subcommands is selected as a storage area subjected to division, according to a comparison result by a subcommand number comparison unit. From partial storage areas constituting the storage area subjected to the division, a partial storage area no smaller than a predetermined size is selected as a partial storage area subjected to the division, according to a comparison result by a size comparison unit. Subcommands for accessing partial storage areas obtained by dividing the partial storage area subjected to the division are generated by an access area division unit. A subcommand for accessing the partial storage area subjected to the division is replaced with the generated subcommands. Subcommands are alternately selected from first and second subcommand groups after the replacement and outputted to a memory.

Abstract: A network device is described that concurrently executing more than one instance of an operating system on a single processor. Each of the instances of the operating system executes completely independent of the other instances. In this way, disparate instances may exist for the same operating system or for different operating systems. The techniques allow the processor to concurrently execute, for example, an instance of the operating system may emulate a routing engine and an instance of the operating system may emulate an interface controller. A hyper scheduler performs context switches between the operating systems to enable the processor to concurrently execute the instances of the operating system. The techniques may provide a low cost alternative to employing multiple processors within a network device, such as a router, to execute multiple independent operating systems.

Abstract: An application may issue write operations intended for a SAN via a server cache. Monitoring of the SAN (e.g., the autonomous persistent cache of the storage arrays of the SAN), allows caching performance to be controlled by a write caching policy. The server cache memory may be increased, decreased or eliminated according to the write caching policy. In one embodiment, a storage volume manager may adjust the latency of write operations in the server cache. In some embodiments, the write caching policy may adapt and learn characteristics of the storage environment, which may include calibrated values for messaging timestamps.

Abstract: A device for data packet processing is disclosed. In one embodiment, the device includes a processor implemented on a chip, an on-chip internal segment memory accessible by the processor, an off-chip external segment memory and a data transfer channel between the internal segment memory and the external segment memory. The external segment memory comprises first and second memory segments wherein the first and second memory segments are different in size.

Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability. A storage system includes an interface unit having an interface with a server or hard drives, a memory unit, a processor unit, and an interconnection.

Abstract: A method of performing a burst read access at a memory device using a multiplexed data/address bus and a control signal including transferring a first portion of address information in a first phase via the multiplexed data/address bus to the memory device; transferring second portion of address information in a second phase via a multiplexed data/address bus to the memory device; transferring a series of data words from the memory via the multiplexed data/address bus; toggling the state of the control signal at the memory device as each data word is transferred; and suspending the transfer of the series of data words from the memory via the multiplexed data/address bus and the toggling of the state of the control signal.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: A method for preventing oversubscription to a file storage by multiple processes, whether such processes are operating on one node with directly attached storage or on several nodes of a computing cluster sharing a storage area network. Processes or nodes issue requests for bandwidth reservations to a controller daemon. The controller daemon maintains records of all existing bandwidth reservations and ensures that new reservations are granted only if a qualified bandwidth of the file storage will not be exceeded. The qualified bandwidth is empirically determined to take into account installation specific hardware configurations, workloads, and quality of service requirements.

Abstract: The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to device flow control includes a host and a chain of devices, including one or more memory device, coupled to each other and configured to communicate with the host device through a same host port. In one or more embodiments, at least one device in the chain is configured to regulate the flow of data by sending a token in downstream data packets, the token allowing devices downstream from the respective at least one device to send an upstream data packet to the respective at least one device.

Abstract: Embodiments of the present invention provide an interface device and method for command processing for commands requiring data flow in both directions on a Fiber Channel or other data transport protocol exchange. The commands can include proprietary commands, SCSI linked commands or other commands known in the art. According to one embodiment, and interface device can assign a command a data flow direction indicator. When a reply to the command is received, the interface device can determine if the reply is expected or unexpected based on the data flow direction specified by the data flow direction indicator. If the reply is unexpected, the interface device can determine whether to process the reply. According to one embodiment, the data flow direction indicator can be the exchange identification.

Abstract: A network gateway application is described that provides throttling, prioritization and traffic shaping for incoming requests from client applications. A request is received by a plug-in manager component of the gateway application. The plug-in manager can then invoke the budget service in order to determine a current available budget for the request. The budget can be computed according to a service level agreement for the service provider, application or network node. The requests can be of high or low priority. If the budget is greater than a specified priority threshold value, the low priority requests can be denied, while the high priority requests can be processed as long as there is some available budget left. If the budget for the request has reached the restricted level, the request can be denied and optionally enqueued to a traffic shaping queue to be processed at a later time.

Abstract: An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time.

Abstract: A method and an apparatus are provided for restricting input/output device peer-to-peer operations in a data processing system to improve reliability, availability, and serviceability. A peer-to-peer (P2P) control logic is provided to perform a lookup of P2P lookup table entries. Each P2P lookup table entry comprises bus, device and function number fields, optional control fields, and an accept/reject bit. Upon receiving a communication request from a requesting I/O device, P2P control logic implemented in either a logical bridge or an I/O device identifies the requester ID of the request and determines if a match exists in the P2P lookup table entries. If a match is found and the accept/reject bit is enabled, I/O operations can be received from the requester.

Abstract: A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction. The method then includes the step of performing a second transaction between the host controller and the hub. The second transaction is based on the single transaction.

Abstract: Support for virtualization in a storage area networks may be provided using a variety of techniques. In one embodiment of the present invention, exchange level load balancing may be provided by determining if input/outputs (IOs) received by a device are new. If a particular IO is new, the IO may be assigned to a particular data path processor and an context may be created corresponding to the IO and to the processor. Then, when an event corresponding to the IO is received, the event may be forwarded to the processor assigned to the IO.

Abstract: A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

Abstract: Systems, methods, and computer-readable media for resuming a media object presented following a data loss event are provided. A physical disconnection that occurs at a point during the presentation of the media object is detected. The physical disconnection interrupts the presentation of the media object. Upon detecting the physical disconnection, a reestablishment of the physical connection is detected. Subsequently, an option to resume the presentation of the media object at the interrupted point is presented to a user.

Abstract: Methods and systems for coordinating the handling of information are disclosed herein and may include scheduling multiple processing tasks for processing multimedia data by a processor. A portion of the scheduled multiple processing tasks may be preprocessed and the preprocessed portion may be buffered within a modifiable buffer that handles overflow and underflow. A portion of the buffered preprocessed portion of the scheduled multiple processing tasks may be executed. The scheduling may utilize a non-preemptive scheduling algorithm, such as an earliest deadline first (EDF) scheduling algorithm and/or a rate monotonic (RM) scheduling algorithm. The scheduled multiple processing tasks may include at least one maximum real deadline. The preprocessed portion of the scheduled multiple processing tasks may be outputted during processing of the blocking task, if a current task of the scheduled multiple processing tasks comprises a blocking task.

Abstract: A method and apparatus are described to provide shared switch and cache memory. The apparatus may comprise a message switch module, a cache controller module, and shared switch and cache memory to provide shared memory to the message switch module and to the cache controller module. The cache controller module may comprise pointer memory to store a plurality of pointers, each pointer pointing to a location in the shared switch and cache memory (e.g., point to a message header partition in the shared switch and cache memory). If there is a corresponding pointer, a memory read response may be sent to the requesting agent. If there is no corresponding pointer, a write data request may be sent to a corresponding destination agent and, in response to receiving the requested data, a pointer to the stored data in the pointer memory may be provided.

Abstract: A computing system having an apparatus for providing an inline data conversion processor. The inline data conversion processor includes a host processor interface, a network interface, a peripheral interface, and a packer stream address for defining a data transformation applied to a block of data as it passes between the host processor interface and the peripheral and network interfaces.

Abstract: An apparatus such as a Device Wire Adapter (DWA) with improved buffer management and packaging of Wireless Universal Serial Bus (WUSB) isochronous packets for transmission to a host. The apparatus includes an isochronous IN endpoint that receives data segments from a device function. Memory is associated with the endpoint and includes an endpoint buffer configured in a loop and a plurality of registers. The apparatus includes an endpoint controller that stores the received data segments sequentially in the loop buffer, assigns a set of the registers to each of the stored data segments, and stores additional packet information in the registers for each of the data segments rather than in the endpoint buffer. The additional packet information includes presentation time for the stored data segment derived from a sample time of a last segment in the buffer and a time interval between two consecutive data segments in the buffer.

Abstract: The present invention relates to an application of the Universal Serial Bus (USB) technology, and more particularly, to a USB apparatus with data storage and security token and control method therein. In an embodiment of the present invention, both mass storage and security token are implemented in a USB apparatus with a single controller. Thus, the host needs to enumerate the apparatus only once, and then may operate differentially in response to different commands. The mass storage is capable of swapping a mass of data, and has a file allocation table compatible with the system. The security token can be used for authenticating a person through digital certificates or biometric characteristics, maintaining the security of the computer and network applications.

Abstract: A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters.

Abstract: A method for performing a data exchange between an initiator and a receiver in a fiber channel protocol (FCP) is provided. A control flag is set in a write command to indicate the presence of an identifier. The identifier is copied into a command descriptor block (CDB) of the write command and appended to a data frame. The write command and data frame, including the identifier, is sent from the initiator to the receiver.

Abstract: A universal serial bus (USB) communication system, the system includes: (a) a wired communication component, which is adapted to receive a received USB transfer; (b) a processor which is adapted to process the received USB transfer to provide a transmittable wireless USB transfer; and (c) a wireless communication component, which is adapted to transmit the transmittable wireless USB transfer; wherein the system is adapted to transmit a portion of the transmittable wireless USB transfer before the entire received USB transfer is received.

Abstract: A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate.

Abstract: An apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address is provided. The apparatus is composed by all cheap electronic devices, so as to achieve a purpose of lowering a cost for design. In addition, in the apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address of the invention, all the I2C slave devices are addressed by an I2C master device to perform the data transmission subsequently before a basic input/output system (BIOS) completes a power-on self-test (POST), but all the I2C slave devices are addressed by a system chip (for example, a baseboard management controller (BMC)) to perform the data transmission subsequently after the BIOS completes the POST. Therefore, the purpose of performing the data transmission for all the I2C slave devices on real time is achieved.

Abstract: In one embodiment, the present invention includes a method for transmitting a packet from a transmitter to a receiver along an interconnect and terminating transmission of the packet at a packet disconnect boundary, which has a length less than a payload length of the packet. After such termination, another packet such as a higher priority packet can be transmitted, or a remainder of the original packet may be transmitted as a separate packet. Other embodiments are described and claimed.

Abstract: A scalable first-in-first-out queue implementation adjusts to load on a host system. The scalable FIFO queue implementation is lock-free and linearizable, and scales to large numbers of threads. The FIFO queue implementation includes a central queue and an elimination structure for eliminating enqueue-dequeue operation pairs. The elimination mechanism tracks enqueue operations and/or dequeue operations and eliminates without synchronizing on the FIFO queue implementation.

Abstract: Disclosed is a single wire communication system for communicating between integrated circuits. The single wire communication system comprises an upper control device generating control commands, a to-be-controlled chip operating with the control commands, and a single wire communication module transferring the control commands. The single wire communication module processes the control commands from the upper control device with the control commands separated into a start signal, a data signal, an end signal, and an ack signal, converts them to at least one or more bits of data bits, and the transfers them to the to-be-controlled chip. By doing so, the present invention can transfer the control commands from the upper control device to the to-be-controlled chip without any loss or distortion caused from unstable factors such as noises, and enables high speed process of a number of commands.

Abstract: An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.

Abstract: A method of Ethernet virtualization using hardware control flow override. The method comprises providing, at a first logical entity of a first programmable logic device, control signals used for performing control-flow, selectively routing the control signals to a second programmable logic device that is external to the first programmable logic device, receiving processed control signals from the second programmable logic device, and forwarding the processed control signals to a second logic entity of the first programmable logic device.

Abstract: An apparatus and a method for intelligent analysis of device compatibility and adaptive processing of multimedia data are disclosed. By performing a unique intelligent analysis of device compatibility, the present invention provides a full application-level compatibility between the apparatus performing the intelligent analysis and an external device operatively connected to the apparatus even when device driver-level information of the external device is unavailable. Furthermore, a unique intelligent analysis for adaptive processing of multimedia data between the apparatus and the external devices enables an efficient and flexible usage of storage space in the external device for a multimedia data transfer from the apparatus to the external device.

Abstract: A method for enhancing data transmission efficiency in a data transmission system having a host, a subsystem and a transmission interface, utilized for the host to transmit and receive a data from a memory of the subsystem via the transmission interface includes steps of the host outputting a query command to the subsystem via the transmission interface for querying available memory utilization of the subsystem; the subsystem outputting a return message to the host via the transmission interface for indicating the available memory utilization according to the query command; and controlling data transmission from the host to the subsystem according to the return message.

Abstract: A mechanism for speculative packet transmission including a credit-based flow control interconnect device to initiate speculative transmission of a Transaction Layer Packet if the number of available flow control (FC) credits is insufficient for completing the transmission. The sending device initiates a speculative transmission of packets to the receiving device even though the packet for transmission requires a number of FC credits greater than the available FC credits. If the additional FC credits required to complete the packet transmission become available to the sending device before the transmission is completed, the packets are then fully transmitted by the sending device. Otherwise, if the additional FC credits required do not become available prior to completion of the transmission, then the sending device aborts the transmission without utilization of the FC credits. The sending device may initiate speculative packet transmission only if a particular minimal amount of FC credits is available.

Abstract: A host device is disclosed. The host device includes a receive frame and primitive sequence processor and a connection manager to open a connection with a target device based on a probability of a blocked pathway.

Abstract: A system that includes a host and a peripheral device. The host transmits a packet that includes a command and a flow control field. The peripheral device receives the packet and has the ability to execute the command, wherein the peripheral device can determine whether the command can be processed in a timely manner, and can update the packet's flow control field with flow control data based on the determination. The host receives the updated packet and has the ability to adjust the flow control of subsequent packets to the peripheral device based on the flow control data in the updated packet.

Abstract: A system and method for supporting character interactive input/output operation in a half-duplex block-mode environment including a workstation and a server. Keystrokes at the workstation received into an auto enter, non-display entity on the workstation display are automatically transferred as entered from the workstation to a server application which processes the keystroke and responds in a manner appropriate to the context of the application.

Abstract: A method reading bank register values is provided. Register values are stored in a readback bank. The register values are output sequentially from the serial bank. An indicator is received by the serial bank. A determination is then made as to whether the indicator was received by the serial bank prior to completion of the outputting of the register values. If the indicator was received prior to completion of the outputting of the register values, the register values are loaded into the serial bank from the readback bank.

Abstract: A data storage system includes a data management system that transfers data between a host system and multiple storage devices through multiple channels. The data management system receives data from the host system and writes the data as data segments to the multiple storage devices. Each data segment may comprise one sector, more than one sector, or a portion of a sector, depending on the embodiment. The data segments are transferred to and from the multiple storage devices in parallel fashion while the data in each data segment is transferred to its corresponding data storage device sequentially. The data management system reassembles data segments received from the data storage devices and sends the data to the host system.

Abstract: A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method for determining and communicating the existence of a hybrid bus is disclosed. A method for determining a path to a senior border node is disclosed, as is a method for identifying a senior border node Various methods for properly issuing gap tokens within a beta cloud are disclosed.

Abstract: Dataflow control for an application with timing parameters, including interfacing temporal and non-temporal domains, is described. The domains receive input data to a first dataflow network block, which is processed for untimed output of first tokens. The first tokens are obtained by a memory interface for timed writing of data portions of the first tokens to data storage and for timed reading of the data portions therefrom. Sending of the data portions read to a first queue of a first controller block is untimed, and the data portions are output by the first controller block with physical timing parameters. Second tokens are generated by the first controller block responsive to the physical timing parameters. The second tokens are fed back to a second queue of the first dataflow network block to control rate of generation of the first tokens by the first dataflow network block.

Abstract: The present invention is directed towards reducing hard disk drive (HDD) activity by sharing the buffering activity between a provisional load sharing buffer (PLSB) and a time shift buffer (TSB). The HDD may be included in a digital host communications terminal (DHCT). Initially, the PLSB buffers initial streaming programs to accommodate for channel changes. Additionally, the streaming program is buffered in a standard definition quality regardless of the format of a connected television. Once a predetermined time has passed determined by the size of the PLSB without a channel change, the TSB begins buffering the streaming program. The TSB can then switch between buffering a high definition quality to a standard definition quality of a streaming high definition program depending on other factors to further decrease the HDD activity. Additionally, the TSB can be disabled to prevent buffering of the streaming program.