Abstract: A reduced complexity maximum likelihood decoder receives a stream of received symbols Y accompanied by a channel estimate matrix H. A variable transformation part includes a first part which converts Y and H into Z and R by computing a matrix R having at least one non-zero element in a row, such that the product of R and Q produces matrix H. A second variable transformation part column-swaps matrix H to form H?, thereafter generating Q? and R? subject to the same constraints as was described for Q and R. Transformed variables Z and Z? are formed by multiplying Y by QH and Q?H, respectively. A reduced complexity maximum likelihood decoder has a first part which accepts Z and R and forms a first metric table having entries of all possible x2 accompanied by estimates of x1 derived from x2 and Z, and also including a distance metric.

Abstract: Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method for transmitting a source data stream from a source device to a sink device includes, forming a logical channel from a source device to a sink device, where the logical channel is configured to carry the source data stream, and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel.

Abstract: Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.

Abstract: A data transmission apparatus connecting to a network consisted of a plurality of data transmission apparatuses comprises a disconnecting device that disconnects a connection established between a transmission plug of a transmitting node and a reception plug of a receiving node, both nodes being connected to the network, an optimization requesting device that requests optimization of transmitting sequences to the transmitting node, a receiver that receives information about a transmission plug newly assigned to the transmitting sequence used by the transmitting nodes of which connection has been disconnected by the disconnecting device, the information being received as an answer for the optimization request from the transmitting node, and a connecting device that establishes a new connection between the newly assigned transmission plug and the reception plug of the receiving node of which connection has been disconnected by the disconnecting device.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: There are provided a terminal capable of selecting a suitable wireless module among a plurality of wireless modules depending on a situation and providing an optimal image even in a state in which a display unit is separated from a main body by performing wireless communication, and a wireless communication method thereof. To enable this, the terminal includes a main body generating and transmitting image data in response to an external input; a display unit mountable on or demountable from the main body, receiving the image data from the main body and displaying an image corresponding to the image data; and a wireless communication unit provided in each of the main body and the display unit, switching a wireless communication frequency band on the basis of a transmission rate of the image data and transmitting the image data to the display unit.

Abstract: Methods, apparatus, and products are disclosed for pacing network traffic among a plurality of compute nodes connected using a data communications network. The network has a plurality of network regions, and the plurality of compute nodes are distributed among these network regions. Pacing network traffic among a plurality of compute nodes connected using a data communications network includes: identifying, by a compute node for each region of the network, a roundtrip time delay for communicating with at least one of the compute nodes in that region; determining, by the compute node for each region, a pacing algorithm for that region in dependence upon the roundtrip time delay for that region; and transmitting, by the compute node, network packets to at least one of the compute nodes in at least one of the network regions in dependence upon the pacing algorithm for that region.

Abstract: System and method for a four-slot asynchronous communication mechanism with increased throughput. The system may include a host system and a client device. The host may comprise a data structure with four (two pairs of) slots and first information indicating a status of read operations from the data structure by the host. The client may read the first information from the host. The client may read second information from a local memory. The second information may indicate a status of write operations to the data structure by the client. The client may determine a slot of the data structure to be written. The slot may be determined based on the first information and the second information and may be the slot which has not been written to more recently of the pair of slots which has not been read from most recently. The client may increment a value of a counter. The value of the counter may be useable to indicate which slot has been written to most recently.

Abstract: A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the signal levels in a specific way when controlling two existing data or select lines, an expansion input and/or output device can generate a strobe and/or enable signal internally. This internal strobe and/or enable signal is then used to store output data or enable input data. The host controller typically utilizes software or firmware to control the data transitions, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.

Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: An apparatus, computer program and method for packet buffer management in an IP network system. The apparatus includes at least one link queue buffer, a shared buffer, a buffer state detector, and a buffer manager. The at least one link queue buffer is allocated a buffer of a packet stored in a memory. The shared buffer is excessively allocated when exceeding a minimum buffer threshold value. The buffer state detector determines whether a buffer value stored in a link queue buffer of a corresponding link exceeds a preset minimum buffer threshold value. The buffer manager sets the shared buffer to be included in the link queue buffer if the stored buffer value exceeds the preset minimum buffer threshold value.

Abstract: A memory control apparatus generates a plurality of commands whose unit of data transfer is smaller than the unit of data transfer of a memory access request, and when the memory access requests are transmitted from a plurality of request sources, issues the plurality of commands to a memory in alternate order for each request source. The plurality of memory access requests are executed by time division and concurrently.

Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.

Abstract: A power supplying device for supplying power through a network to a plurality of communication terminals to transmit or receive data in a form of a packet including: a power supply controlling unit to preset a count of the communication terminals which are to be targeted for power supply, for every predetermined time period, out of the plurality of communication terminals, and to measure a flow rate of packets to be transmitted or received for every communication terminal to which power is being supplied, out of the communication terminals targeted for the power supply in each time period, and to supply power to at least one communication terminal to which power is not yet being supplied, out of the communication terminals targeted for the power supply, when the measured flow rate of packets in any communication terminal becomes not less than a predetermined threshold.

Abstract: A method, system and apparatus of shared bus architecture are disclosed. In one embodiment, a method controlling set of multiplexers using an arbiter circuit per transaction, selecting one of a memory clock and a host clock based on an arbitration status, driving a final output on an interface to provide glitchless switching of an interface signal, connecting the interface signal to a tri-state buffer, and setting the direction of a data and address bus based on the connection of the interface signal to the tri-state buffer. The method may include applying a fair arbitration policy to ensure that none of the devices coupled to the interface signal and application threads running on processor requiring data from different devices are starved.

Abstract: A processor determines whether a prescribed period of time has elapsed or not. When the processor has determined that the prescribed period of time has elapsed, the processor determines whether a mode 0 is set or not. When it is determined that the mode 0 is set, a wireless packet including remote controller button data, remote controller acceleration data and remote controller DPD data is generated. Then, the generated wireless packet is transmitted to a game device. When the processor has determined that a mode 1 is set, a wireless packet including remote controller information including the remote controller button data and the remote controller acceleration data and biological information including previous pulse wave data, present pulse wave data and light reception level data, instead of the remote controller DPD data, is generated.

Abstract: A control apparatus includes a first processor that is operative to perform outputting first data including control data, a first input/output interface that receives the first data, a second input/output interface that receives and outputs data, a third input/output interface that receives and outputs data using a second communication method, in which transmission speed is lower than transmission speed in the first communication method, and a second processor that is operable to perform controlling the second input/output interface outputs third data, which is obtained by replacing the control data included in the first data received by the first input/output interface with second data received by the third input/output interface, to a control target apparatus, controlling the control target apparatus outputs the third data received from the second input/output interface, and controlling the third input/output interface outputs response data in response to the third data received from the control target appa

Abstract: A media system includes at least a source media device and a playback media device coupled through a network. The source media device presents media to the network. The media comprises at least one digital content file with a first format. A playback media device plays back digital content files formatted in a second format. A transcoder, also coupled to the network, converts the first format of the digital content file to a second format. In one embodiment, the transcoder comprises a device separate from the source media device and the playback media device. In another embodiment, the transcoder comprises a device integrated with the source media device. The playback device receives the digital content file, formatted in the second format, over the network, and processes the digital content file in the second format to generate processed signals. The processed signals drive the playback device to play the digital content file.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: For each broadcast control channel of a plurality of broadcast control channels associated with a plurality of wireless networks, a mobile device decodes control information on the broadcast control channel and stores this control information in its memory. The control information includes a network identification which uniquely identifies a particular wireless communication network. Such decoding is performed in between or during repeated acts of measuring signal strength levels of an RF signal on the broadcast control channel, and prior to completion of an averaging function for calculating an averaged signal strength level of the signal strength levels on the broadcast control channel. Decoding may be performed only for those broadcast control channels identified to have the most optimal signal strengths.

Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.

Abstract: The invention relates to a method for setting an operating parameter in a peripheral IC. In this method, the operating parameter is transmitted from a central IC via a bus connection to the peripheral IC. The method is characterized in that the operating parameter is initially buffered in a preregister in the peripheral IC, and in that the buffered operating parameter is transferred into a working register only if a transfer signal is sent from the central IC via the bus connection. This method has the advantage that, for example in the case of rapidly changing receive conditions in a send/receive unit, adjustment of the send or receive gain setting is very flexible, and it is easy to avoid an incorrect setting due to a detected signal fluctuation. The invention also relates to a device for carrying out said method.

Abstract: An isolated highway addressable remote transfer (HART) interface with programmable data flow is provided. The isolated HART interface includes a HART channel having at least one pair of terminals configured to connect with a HART device via a current loop. The HART channel is programmable to have each pair of terminals assigned as a current loop input or a current loop output.

Abstract: Provided is a unit for protecting data with respect to data transfer between memories of a disk controller. The disk controller for controlling data transfer between a host computer and a disk drive includes: a channel unit having a channel memory; a cache unit having a cache memory, and a control unit for controlling the data transfer. The data transferred to/from the host computer is transferred in a packet between the channel memory and the cache memory, and The control unit for verifying consistency of information included in a header of the packet to be transferred to decide whether transfer can be permitted when the packet is transferred.

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: One embodiment of the invention sets forth a control crossbar unit that is designed to transmit control information from control information generators to destination components within the computer system. The control information may belong to various traffic paradigms, such as short-latency data traffic, narrow-width data traffic or broadcast data traffic. The physical connections within the control crossbar unit are categorized based on the different types of control information being transmitted through the control crossbar unit. The physical connections belong to the following categories: one-to-one (OTO) connections, one-to-many (OTM) connections, valid-to-one (VTO) connections, valid-to-many (VTM) connections wire-to-one (WTO) connections and wire-to-many (WTM) connections.

Abstract: Devices in a process control system communicate by data messages over a communication medium segment. Each device includes a communication controller that includes a data queue and a queue of received message objects. The data queue stores a plurality of messages received on the communication medium. The received message objects contain information about a corresponding message in the data queue.

Abstract: The invention provides a method for serial data transmission. First, a chip select signal is enabled to a device for serial data transmission. Data stored in a first buffer of a controller is then transmitted to a second buffer of the device. A clock signal is then halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the controller while the clock signal is halted. The clock signal is the restarted to operate the device after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: In one embodiment, a receiver on a credit-based flow-controlled interface is configured to free one or more data credits early when a data payload is received that incurs fewer unused data credits within a buffer memory that is allocated at a coarser granularity than the data credits. In another embodiment, header credits and data credits are dynamically adjusted based on actual packet data payload sizes.

Abstract: A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.

Abstract: A method for adjusting a transmission speed of an electronic aid includes the steps of making a rate negotiation between the electronic aid and a computer, judging whether the rate negotiation is successful or not, if it is successful but data can not be transferred between the electronic aid and the computer, the computer will self-correct the transmission speed of the electronic aid. The present invention ensures that the electronic aid, which can not work normally at high-speed, works normally after deceleration, thereby improving the compatibility of the electronic aid.

Abstract: Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Rate logic may couple to the communication fabric. The rate logic is configured to determine a data bandwidth difference between a first data bandwidth capability of the sending device and the lower of 1) a second data bandwidth capability of the sending device or 2) a third data bandwidth capability of the communication fabric.

Abstract: Systems, methods, and computer-readable media for resuming a media object presented following a data loss event are provided. A physical disconnection that occurs at a point during the presentation of the media object is detected. The physical disconnection interrupts the presentation of the media object. Upon detecting the physical disconnection, a reestablishment of the physical connection is detected. Subsequently, an option to resume the presentation of the media object at the interrupted point is presented to a user.

Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

Abstract: A computer-executed method for controlling transaction flow in a network comprises communicating transaction packets among a plurality of devices in a network fabric and subdividing a memory into a plurality of memory segments for storing received transaction cycles according to transaction packet type comprising posted, non-posted, and completion cycles. A plurality of transaction cycles are received in the memory segment plurality at a target device and transaction cycle priority is allocated according to transaction packet type wherein posted cycles have highest priority. Cycles are retrieved from the memory segment plurality in an order determined by priority.

Abstract: In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold. If fulfilling the read request would cause the total size of the completion queue to exceed the first predefined threshold, then the read request is temporarily restricted from being forwarded upstream.

Abstract: A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock generated by the internal oscillator. In the processing device, a clock control circuit that switches a system clock between the internal clock and the external clock in accordance with the interface is provided. When the system clock is switched, the switching is performed after the CPU is set in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart the operation.

Abstract: Provided are a method, system, and article of manufacture, in which a logical path is established between a control unit and a channel over a fiber channel connection. Code for persistent information unit pacing is loaded into the control unit and the channel. An indicator is set in node descriptors of the control unit and the channel to indicate concurrent enablement of persistent pacing while retaining the established logical path between the control unit and the channel.

Abstract: Multiple computing devices are connected together using a high-speed wireless link. The wireless link enables expansion of available resources to the host device, such as one or more of volatile memory resources, non-volatile memory resources, and additional processor resources.

Abstract: Systems and methods for aggregating transmit completion interrupts for multiple packets are provided. A network device can include a buffer with multiple memory locations capable of temporarily storing a packet being transmitted across the network via the network device and nodes connected to the network device. The network device can include a high watermark for determining when to process transmit completion interrupts. If the number of packets stored in the memory exceeds the high watermark, an aggregated transmit completion interrupt for all of the packets can be processed. Otherwise, the network device waits until sufficient packets are received to reach the high watermark.

Abstract: The disclosure relates to a method and apparatus to efficiently address livelock in a multi-processor system. In one embodiment, the disclosure is directed to a method for preventing a system bus livelock in a system having a plurality of processors communicating respectively through a plurality of bus masters to a plurality of IO Controllers across a system bus by: receiving at an MMIO state machine a plurality of snoop commands issued from the plurality of processors, identifying a first processor and a second processor from the plurality of processors, each of the first processor and the second processor having a first number of snoop commands in the input queue and a second number of responses in the output queue, the first number and the second number exceeding a threshold; issuing a burst prevention response to the first processor and the second process.

Abstract: There is provided a method that includes (a) inputting data to a buffer, wherein the inputting increases a quantity of the data in the buffer, (b) processing the data from the buffer, wherein the processing decreases a quantity of the data in the buffer, (c) determining an average quantity of the data in the buffer, and (d) converting a data stream for inputting to the buffer, from a first quantity of samples to a second quantity of samples, if the average quantity is outside of a target range.

Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.

Abstract: A port optimization component and method for selecting a pair of ports, each port having predetermined operating parameters, for connecting to a storage device in a storage area network, the port optimization component comprising: a determination component for requesting configuration data and policy data pertaining to a storage device in response to a request to configure access to the storage device; and the determination component for comparing the configuration data to the policy data to determine a difference in operating parameters for each storage device port located on the storage device and in dependence on the detected difference, selecting a pair of ports having a preferred operating parameter.

Abstract: An information processing apparatus includes a communication unit that transmits/receives data to and from an external device; a detection unit that detects communication connection with the external device by the communication unit; an operation input unit that accepts an operation input; a command allocation unit that, when the detection unit detects communication connection with the external device, allocates a data transmission command with respect to a one-click operation to a symbol corresponding to a data storage place to be displayed on a display unit, which is accepted by the operation input unit; and a control unit that, when the operation input unit accepts the one-click operation to the symbol, in case the data transmission command is allocated with respect to the one-click operation, controls so that the communication unit transmits data stored in the data storage place corresponding to the symbol to the external device.

Abstract: In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

Abstract: In the transfer of AV data flows, especially in a network environment, a delayed transition from one operating mode to the other operating mode will be possible when changing the operating mode from e.g. normal replay to fast forward search. This is due to the fact that—in the transfer from data source to data sink different buffer memory stages must be passed before the transferred data finally come to decoding. When the request for changing the operating mode comes, the data already present in the buffer memories must first be processed before the actually requested new data come to be decoded. For the solution of the problem described, it is suggested according to the invention that after the request of changing the operating mode the undesirable data in the buffer memories are quickly eliminated through suitable measures so that the desired data can then be decoded faster. To do that, an identifier for the new operating mode is inserted in the data flow on the part of the data source device.

Abstract: A disk controller for coupling a disk drive to a host includes an interface controller and a buffer memory. The interface controller is configured to interface the disk drive to the host using a NAND flash memory interface having a 14-line bus. The interface controller includes a flash controller configured to emulate data transfer protocols of the disk drive, including interpreting flash commands received from the host via the 14-line bus of the NAND flash memory interface, and generating control signals to control the disk drive. The control signals are generated based on the interpreted flash commands. The buffer memory is configured to store data received from the host and the disk drive.

Abstract: A method for enhancing performance of data access between a personal computer and a USB Mass Storage is provided. The personal computer is equipped with a plurality of layers of drivers regarding USB data access, and a lower layer of the layers of the drivers includes a USB Bus Driver. The method includes: monitoring commands sent from an operating system (OS) file system to an upper layer; and when a command sent from the OS file system to the upper layer is utilized for accessing data of a data amount that is greater than a predetermined threshold value, omitting a portion of a plurality of IRPs, automatically generating a plurality of replies for replying to the omitted IRPs, and altering at least one IRP of remaining IRPs in order to correctly access the data with a lower IRP count, wherein the plurality of IRPs is associated with the command.