Buffer Or Que Control Patents (Class 710/310)
  • Patent number: 10929302
    Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space. The address space maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and translates, based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Christoph Raisch, Marco Kraemer, Carsten Otte, Jonathan D. Bradbury, David Craddock
  • Patent number: 10929332
    Abstract: The present application relates to the field of integrated circuit design and manufacturing, and discloses a USB transmission device and a transmission method, which may greatly improve the transmission rate when transmitting a large number of small files. The device includes: a configuration module, configured to configure a first transfer ring corresponding to a first transfer thread and a second transfer ring corresponding to a second transfer thread for one endpoint in a memory; a USB host controller, configured to directly perform a transmission of the second transfer thread according to the configured second transfer ring when a transmission of the first transfer thread ends.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: February 23, 2021
    Assignee: MONTAGE LZ TECHNOLOGIES (Chengdu) Co., Ltd.
    Inventor: Zeng Xu
  • Patent number: 10901862
    Abstract: A memory system includes a processing device (e.g., a controller implemented using a CPU, FPGA, and/or logic circuitry) and memory regions (e.g., in a flash memory or other non-volatile memory) storing data. The processing device receives an access request from a host system that is requesting to read the stored data. In one approach, the memory system is configured to: receive, from the host system over a bus, a read command to access data associated with an address in a non-volatile memory; in response to receiving the read command, access, by the processing device, multiple copies of data stored in at least one memory region of the non-volatile memory; match, by the processing device, data from the copies with each other; select, based on matching data from the copies with each other, first data from a first copy of the copies; and provide, to the host system over the bus, the first data as output data.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Gil Golov
  • Patent number: 10901871
    Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Rolf Kuehnis, Peter Lachner
  • Patent number: 10878887
    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 29, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, James E. Harris
  • Patent number: 10783104
    Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 22, 2020
    Assignee: Apple Inc.
    Inventors: Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Sukulpa Biswas
  • Patent number: 10756055
    Abstract: Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: August 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Un-Byoung Kang, Yungcheol Kong, Kyoungsei Choi
  • Patent number: 10749706
    Abstract: The present invention relates to an integrated circuit device for controlling LIN slave nodes based on a control signal transmitted by a LIN master control device. The IC device comprises a slave node circuit for processing the control signal when received in the form of a LIN message frame via a first data line terminal. The IC device also comprises a master node circuit for processing further control signals to be transmitted in the form of LIN message frames via a second data line terminal to the LIN slave nodes. The IC device also comprises a processing unit for controlling the LIN slave nodes based on the control signal by composing the further control signals.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: August 18, 2020
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Michael Bender, Philip Mckenna, Thomas Freitag
  • Patent number: 10733302
    Abstract: Vulnerability data is classified as described herein. A finding object is created based on vulnerability data associated with a vulnerability finding and that finding object is populated with property values based on the vulnerability data. Technical owner rules associated with a plurality of technical owners are evaluated based on the property values of the finding object and a technical owner is assigned to the finding object based on the evaluated technical owner rules. Once a technical owner is assigned, the finding object is provided to a governance, risk, and compliance (GRC) module for distribution of the vulnerability finding to the assigned technical owner for remediation. Classification of vulnerability data using the described property values and technical owner rules provides an efficient, accurate, and automated way of distributing vulnerability findings of large, complex code bases to teams for remediation.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: August 4, 2020
    Assignee: MASTERCARD INTERNATIONAL INCORPORATED
    Inventors: Eric Gunn, Martin Gonzalo Enriquez
  • Patent number: 10664945
    Abstract: Devices for coordinating or establishing a direct memory access for a network interface card to a graphics processing unit, and for a network interface card to access a graphics processing unit via a direct memory access are disclosed. For example, a central processing unit may request a graphics processing unit to allocate a memory buffer of the graphics processing unit for a direct memory access by a network interface card and receive from the graphics processing unit a first confirmation of an allocation of the memory buffer. The central processing unit may further transmit to the network interface card a first notification of the allocation of the memory buffer of the graphics processing unit, poll the network interface card to determine when a packet is received by the network interface card, and transmit a second notification to the graphics processing unit that the packet is written to the memory buffer.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 26, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Brian S. Amento, Kermit Hal Purdy, Minsung Jang
  • Patent number: 10664422
    Abstract: Various implementations of a multi-chip system operable according to a predefined transport protocol are disclosed. In one embodiment, a system comprises a first IC comprising a processing element communicatively coupled with first physical ports. The system further comprises a second IC comprising second physical ports communicatively coupled with a first set of the first physical ports via first physical links, and one or more memory devices that are communicatively coupled with the second physical ports and accessible by the processing element via the first physical links. The first IC further comprises a data structure describing a first level of port aggregation to be applied across the first set. The second IC comprises a first distribution function configured to provide ordering to data communicated using the second physical ports. The first distribution function is based on the first level of port aggregation.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 26, 2020
    Assignee: XILINX, INC.
    Inventors: Millind Mittal, Jaideep Dastidar
  • Patent number: 10657053
    Abstract: Methods and apparatus for filtering input data objects are provided. A computing device can receive an input data object to be filtered; e.g., compressed/decompressed, decrypted/encrypted, bit converted. The computing device can determine whether the input data object has been previously filtered. After determining that the input data object has been previously filtered, the computing device can: determine a previously filtered data size for the input data object, allocate a memory buffer to store a filtered version of the input data object based on the previously filtered data size, and filter the input data object using the memory buffer. The computing device can generate an output based on the filtered data object.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 19, 2020
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventor: Eric Pugh
  • Patent number: 10652610
    Abstract: A content providing device includes a first wired interface that communicates with a first external electronic device through a wired cable or a wireless dongle, and a processor that determines whether the wired cable or the wireless dongle is connected to the first wired interface, and selects a power source based on whether the wired cable or the wireless dongle is connected to the first wired interface.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Bok Lee, Eung Sik Yoon, Jin Lee
  • Patent number: 10649922
    Abstract: A system and method for efficiently scheduling requests. In various embodiments, a processor sends commands such as read requests and write requests to an arbiter. The arbiter reduces latencies between commands being sent to a communication fabric and corresponding data being sent to the fabric. When the arbiter selects a given request, the arbiter identifies a first subset of stored requests affected by the given request being selected. The arbiter adjusts one or more attributes of the first subset of requests based on the selection of the given request. In one example, the arbiter replaces a weight attribute with a value, such as a zero value, indicating the first subset of requests should not be selected. Therefore, during the next selection by the arbiter, only the requests in a second subset different from the first subset are candidates for selection.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: May 12, 2020
    Assignee: Apple Inc.
    Inventors: Shawn Munetoshi Fukami, Jaideep Dastidar, Yiu Chun Tse
  • Patent number: 10621115
    Abstract: A system and method for communication link management in a credit-based system is disclosed. In one embodiment, a system includes first and second functional circuit blocks implemented on an integrated circuit and being able to communicate with one another through establishment of source synchronous links. The first functional circuit block includes a write queue for storing data and information regarding write requests sent from the second functional circuit block. The write queue includes credit management circuitry arranged to convey one or more credits to the second functional circuit block responsive to receiving one or more write requests therefrom. Responsive to receiving the one or more credits and in the absence of any pending additional requests, the second functional circuit block may deactivate a link with the first functional circuit block.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Apple Inc
    Inventors: Gregory S. Mathews, Shane J. Keil, Lakshmi Narasimha Nukala
  • Patent number: 10599550
    Abstract: Systems and methods for managing Application Programming Interfaces (APIs) are disclosed. For example, the system may include one or more memory units storing instructions and one or more processors configured to execute the instructions to perform operations. The operations may include sending a first call to a first node-testing model associated with a first API and receiving a first model output comprising a first model result and a first model-result category. The operations may include identifying a second node-testing model associated with a second API and sending a second call to the second node testing model. The operations may include receiving a second model output comprising a second model result and a second model-result category. The operations may include performing at least one of sending a notification, generating an updated first node-testing model, generating an updated second node-testing model, generating an updated first call, or generating an updated second call.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 24, 2020
    Assignee: Capital One Services, LLC
    Inventors: Austin Walters, Jeremy Goodsitt, Vincent Pham, Kate Key
  • Patent number: 10565004
    Abstract: In an example, memory register interrupt based signaling and messaging may include receiving, at a control register of a receiver, a signal number from a sender, and copying, by a memory register interrupt management device of the receiver, the signal number to an associated status register of the receiver. Further, memory register interrupt based signaling and messaging may include generating, independently of the signal number from the status register, an interrupt to a central processing unit of the receiver, and triggering, based on the interrupt, an interrupt handler of the receiver to perform an action associated with the signal number.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: February 18, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jean Tourrilhes, Mike Schlansker
  • Patent number: 10515030
    Abstract: An Advanced Microcontroller Bus Architecture (AMBA)/Advanced eXtensible Interface (AXI) compatible device and corresponding method capable of efficient reordering of responses from a last level cache (LLC) and/or dynamic random access memory (DRAM).
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: December 24, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Arkadi Avrukin, Seungyoon Song, Milan Shah, Thomas Zou
  • Patent number: 10515038
    Abstract: The present disclosure provides new methods and systems for input/output command rebalancing in virtualized computer systems. For example, an I/O command may be received by a rebalancer from a virtual queue in a container. The container may be in a first virtual machine. A second I/O command may be received from a second virtual queue in a second container which may be located in a second virtual machine. The rebalancer may detect a priority of the first I/O command and a priority of the second I/O command. The rebalancer may then assign an updated priority each I/O command based on a quantity of virtual queues in the virtual machine of origin and a quantity of I/O commands in the virtual queue of origin. The rebalancer may dispatch the I/O commands to a physical queue.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: December 24, 2019
    Assignee: Red Hat, Inc.
    Inventor: Huamin Chen
  • Patent number: 10515027
    Abstract: According to examples, an apparatus may include a memory to which a first queue and a second queue are assigned, in which a storage device is to access data task requests stored in the first queue and the second queue, in which the apparatus is to transfer the first queue to a second apparatus. The apparatus may also include a central processing unit (CPU), the CPU to input data task requests for the storage device into the second queue, in which the second apparatus is to store the first queue in a second memory of the second apparatus, and the storage device is to access data task requests from the first queue stored in the second memory of the second apparatus and data task requests from the second queue stored in the memory to cause the apparatus and the second apparatus to share access to the storage device.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 24, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kirill Malkin, Alan Poston, Matthew Jacob
  • Patent number: 10509743
    Abstract: A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or software mechanism can be provided to detect at least one memory load parameter indicating how heavily loaded the memory system is, and a group size of the block of data transferred per group can be varied based on the memory load parameter. By adapting the size of the block of data transferred per group based on memory system load, a better balance between energy efficiency and quality of service can be achieved.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 17, 2019
    Assignee: ARM Limited
    Inventors: Daren Croxford, Sharjeel Saeed, Quinn Carter, Michael Andrew Campbell
  • Patent number: 10496457
    Abstract: A memory system having a set of media, a plurality of inter-process communication channels, and a controller configured to run a plurality of processes that communicate with each other using inter-process communication messages transmitted via the plurality of inter-process communication channels, in response to requests from a host system to store data in the media or retrieve data from the media. The memory system has a message manager that examines requests from the host system, identifies a plurality of combinable requests, generates a combined request, and provides the combined request to the plurality of processes as a substitute of the plurality of combinable requests.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: December 3, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Alex Frolikov
  • Patent number: 10491641
    Abstract: A first communication provider supports an IP multimedia subsystem (IMS) having a border session control function (BGCF) that receives SIP requests. The SIP requests correspond to different SIP methods and specify various feature tags. The feature tags correspond to available services or media types that may be available from the IMS of a second communication provider. When receiving a SIP request that addresses a user supported by the second communication provider, the BGCF of the first communication provider checks the method and feature tag of the SIP request to make sure that they are supported by IMS of the second communication provider. If they are not, the SIP is rejected and a failure message is returned. The BGCF may also modify certain parameters of the SIP request, such as by removing one or more offered codecs or preconditions.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: November 26, 2019
    Assignee: T-Mobile USA, Inc.
    Inventors: Shujaur Mufti, Saqib Badar, Zeeshan Jahangir
  • Patent number: 10474620
    Abstract: An information handling system (IHS) and a method of transmitting data in an IHS. The method includes detecting, via a hardware logic device, a first memory transaction request from a first peripheral component interconnect express (PCIe) device to a system memory. The first memory transaction request includes a first system memory address. A second memory transaction request is detected from a second PCIe device to the system memory. The second memory transaction request includes a second system memory address. The method further includes determining if the first system memory address and the second system memory address are the same system memory address. In response to the first and second system memory addresses being the same, the first memory transaction request and the second memory transaction request are coalesced into a common memory transaction request. The common memory transaction request is issued to the system memory.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: November 12, 2019
    Assignee: Dell Products, L.P.
    Inventors: Srikrishna Ramaswamy, Shyamkumar T. Iyer, Duk M. Kim
  • Patent number: 10459842
    Abstract: In an embodiment of the invention, an apparatus comprises: a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and wherein any of the prefetch buffers is configured to store prefetch data. The prefetch data is available to a host that sends a memory read transaction request to the data storage device. In another embodiment of the invention, a method comprises: storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a storage device; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer. The prefetch data is available to a host that sends a memory read transaction request to a data storage device.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: October 29, 2019
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rey H. Bruce, Ricardo H. Bruce, Marlon B. Verdan, Elsbeth Lauren Tagayo-Villapaña
  • Patent number: 10380446
    Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, Steven P. King
  • Patent number: 10379995
    Abstract: Systems and methods for managing Application Programming Interfaces (APIs) are disclosed. For example, the system may include one or more memory units storing instructions and one or more processors configured to execute the instructions to perform operations. The operations may include sending a first call to a first node-testing model associated with a first API and receiving a first model output comprising a first model result and a first model-result category. The operations may include identifying a second node-testing model associated with a second API and sending a second call to the second node testing model. The operations may include receiving a second model output comprising a second model result and a second model-result category. The operations may include performing at least one of sending a notification, generating an updated first node-testing model, generating an updated second node-testing model, generating an updated first call, or generating an updated second call.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 13, 2019
    Assignee: Capital One Services, LLC
    Inventors: Austin Walters, Jeremy Goodsitt, Vincent Pham, Kate Key
  • Patent number: 10374825
    Abstract: Communication between one communication bus having one set of characteristics and another communication bus having another set of characteristics is facilitated by a bridge coupling the two communication buses. The bridge includes a scoreboard to manage data communicated between the buses. In one particular example, the one communication bus is a Processor Local Bus (PLB6) and the other communication bus is an Application Specific Integrated Chip (ASIC) Interconnect Bus (AIB).
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUISNESS MACHINES CORPORATION
    Inventors: Andrew R. Ranck, Mushfiq U. Saleheen, Jie Zheng
  • Patent number: 10353088
    Abstract: Neutron multiplicity detector control logic and firmware may control a neutron multiplicity detector such that higher count rates can be achieved by an order of magnitude of more over conventional control logic and firmware. Count rates of over 1,000,000 cps, and even over 1,500,000 cps, have been realized in some implementations.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 16, 2019
    Assignees: Triad National Security, LLC, Natl. Tech. & Engineering Solutions of Sandia, LLC, Lawrence Livermore National Security, LLC
    Inventors: Mark Nelson, Eric Sorensen, Brian Rooney, Richard Rothrock, Matthew Newell, Samuel Salazar, Christopher Romero, David Jones, Sean Walston, Scott Kiff
  • Patent number: 10353833
    Abstract: A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first data packets with an unordered attribute being set to an ordering controller. The computer system further comprises the coupling device configured to send second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The computer system further comprises the ordering controller configured to send the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Girish G. Kurup
  • Patent number: 10318238
    Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Brian Huber, Gary Howe
  • Patent number: 10311007
    Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: June 4, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: David M. Thompson, Timothy D. Anderson, Joseph R. M. Zbiciak, Abhijeet A. Chachad, Kai Chirca, Matthew D. Pierson
  • Patent number: 10310919
    Abstract: Embodiments of the present invention provide methods, program products, and systems to increase efficiency in message oriented middleware. Embodiments of the present invention can, responsive to receiving from an application an open request for a queue alias of a queue manager, provide to the application target cache information which includes a target name and a change flag count associated with the queue alias. Embodiments of the present invention can, responsive to receiving a message from the application that includes respective target cache information including a target name and a change flag count, determine a target location, wherein if the change flag count of the received message matches a current change flag count of the queue alias, the determined target location is a target location associated with the received target name.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Qian Li Jin, Yan Shi, Fan Yang, Shan Yu, Yang Zhang
  • Patent number: 10261699
    Abstract: In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: April 16, 2019
    Assignee: Dell Products L.P.
    Inventors: Srikrishna Ramaswamy, Shyam T. Iyer, Duk M. Kim
  • Patent number: 10262971
    Abstract: Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Un-Byoung Kang, Yungcheol Kong, Kyoungsei Choi
  • Patent number: 10204070
    Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing; the reliable TLP transmission module, configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time, so that a destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC, thereby implementing reliable transmission of a TLP in a case of a PCIE switching dual-plane networking connection.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: February 12, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Dexian Su, Yimin Yao, Jing Wang
  • Patent number: 10187044
    Abstract: A bistable cell includes a pair of inverters and multiple pairs of cross-coupled tristate buffers. Each pair of tristate buffers can be individually selected to implement an entropy harvesting state for the bistable cell. Each of the tristate buffers generally has lower strength than the inverters but the inverter-to-buffer strength ratio can be configured through selective use of one or more of the tristate buffer pairs. The resulting entropy harvesting state behavior can be varied based on the inverter-to-buffer strength ratio in terms of greater randomness of the output bits or decreased power consumption.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: January 22, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Dan Trock, Elad Valfer, Yair Armoza
  • Patent number: 10120809
    Abstract: This disclosure pertains to using traffic classes to selectively store data into cache memory or into system memory. A cache controller can map the traffic class of incoming data to portions of the cache memory allocated for corresponding traffic classes of data.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Philip C. Arellano, James A. Coleman
  • Patent number: 10075284
    Abstract: A system and method for clock phase alignment at a plurality of line cards over a backplane of a communication system. Phase adjustments are continually made for the clock signals at the line cards by dynamically measuring the propagation delay between the timing device and each of the plurality of line cards and continuously communicating the appropriate phase adjustment to each of the plurality of line cards.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: September 11, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Silvana Rodrigues, Michael Rupert, Zaher Baidas, Leon Goldin
  • Patent number: 10068640
    Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: September 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Hikaru Tamura
  • Patent number: 10061727
    Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 28, 2018
    Assignee: Seagate Technology LLC
    Inventors: Timothy Lawrence Canepa, Earl T. Cohen
  • Patent number: 10056058
    Abstract: A driver includes a plurality of driver chips and an operation method thereof are provided. Each of driver chips includes a first transmission interface, a second transmission interface and a third transmission interface. The driver chips are coupled to each other by the first transmission interfaces and the second transmission interfaces, and the third transmission interfaces are commonly coupled to a parameter source to receive a plurality of operation parameters during an operation initiating period. When an abnormal signal is not returned after receiving the operation parameters, the driver chips end the operation initiating period. When the abnormal signal is returned after receiving the operation parameters, the driver chips receive the operation parameters again.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: August 21, 2018
    Assignee: Au Optronics Corporation
    Inventors: Cheng-Hsien Hsu, Yung-Shu Lin
  • Patent number: 9973632
    Abstract: Conference systems are often installed in plenary halls or meeting rooms, whereby such conference systems typically consist of a central equipment and equipment for the participants of the discussion. The central equipment is usually used to control the conference system and supply power to the participant equipment.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 15, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Sjack Schellekens, Marc Smaak, John Meeusen, Hans Van Der Schaar
  • Patent number: 9971546
    Abstract: A method for scheduling read and write commands, performed by a processing unit, including at least the following steps: the processing unit obtains more than one read commands from a read queue successively and executes the obtained read commands until a first condition is met. After the first condition is met, the processing unit obtains more than one write commands from a write queue successively and executes the obtained write commands until a second condition is met.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: May 15, 2018
    Assignee: Silicon Motion, Inc.
    Inventor: Yang-Chih Shen
  • Patent number: 9935774
    Abstract: Embodiments of a device and method are disclosed. In an embodiment, a CAN device includes a security module connected between a CAN bus interface of a CAN transceiver and a microcontroller communications interface of the CAN transceiver and an operational mode controller connected between the security module and the CAN bus interface. The security module is configured to perform a security function on data traffic received from the CAN bus interface or from the microcontroller communications interface. The operational mode controller is configured to set an operational mode for the CAN transceiver such that a CAN Flexible Data-rate (FD) frame or a corresponding CAN frame is output from the CAN bus interface. An identifier of the CAN FD frame is the same as an identifier of the corresponding CAN frame.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 3, 2018
    Assignee: NXP B.V.
    Inventor: Vibhu Sharma
  • Patent number: 9858187
    Abstract: Techniques are disclosed relating to an in-memory cache for web application data. In some embodiments, received transactions include multiple operations, including one or more cache operations to access the in-memory cache. In some embodiments, transactions are performed atomically. In some embodiments, data for the one or more cache operations is stored locally in memory by an application server outside of the in-memory cache until the transaction is successfully completed. This may improve performance and facilitate atomicity, in some embodiments.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: January 2, 2018
    Assignee: salesforce.com, inc.
    Inventors: Barathkumar Sundaravaradan, Christopher James Wall, Lawrence Thomas Lopez, Paul Sydell, Sreeram Duvur, Vijayanth Devadhar
  • Patent number: 9804781
    Abstract: A method or system for determining a required certification level of storage area for storing data of a write request based on a characteristic of the data, selecting a target storage area based on a media certification table and the required determined certification level of the media area and storing data at the target storage area.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: October 31, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Andrew Michael Kowles
  • Patent number: 9774536
    Abstract: Generally, this disclosure describes techniques for buffer management based on link status. A host platform may include a Baseboard Management Controller (BMC) and a network controller that includes a buffer used by the BMC. When a network controller is in a lower power link state, the BMC may attempt to send data to the link partner which causes the network controller to transition out of the low power state. However, this transition may take longer than the buffer's ability to buffer the incoming flow from the BMC. Accordingly, to avoid the need for larger buffer space, a buffer manager is used to provide flow control management of the buffer based on link status.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: September 26, 2017
    Assignee: INTEL CORPORATION
    Inventors: Eliel Louzoun, Liron Elmaleh, Aviad Wertheimer
  • Patent number: 9710381
    Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, David M. Daly, Robert K. Montoye, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary
  • Patent number: 9639143
    Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: May 2, 2017
    Assignee: Apple Inc.
    Inventors: Erik P. Machnicki, Gurjeet S. Saund, Munetoshi Fukami, Shane J. Keil, Chaitanya Kosaraju, Erdem Guleyupoglu, Jason M. Kassoff, Kevin C. Wong