Abstract: An information handling system (IHS) and a method of transmitting data in an IHS. The method includes detecting, via a hardware logic device, a first memory transaction request from a first peripheral component interconnect express (PCIe) device to a system memory. The first memory transaction request includes a first system memory address. A second memory transaction request is detected from a second PCIe device to the system memory. The second memory transaction request includes a second system memory address. The method further includes determining if the first system memory address and the second system memory address are the same system memory address. In response to the first and second system memory addresses being the same, the first memory transaction request and the second memory transaction request are coalesced into a common memory transaction request. The common memory transaction request is issued to the system memory.

Abstract: In an embodiment of the invention, an apparatus comprises: a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and wherein any of the prefetch buffers is configured to store prefetch data. The prefetch data is available to a host that sends a memory read transaction request to the data storage device. In another embodiment of the invention, a method comprises: storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a storage device; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer. The prefetch data is available to a host that sends a memory read transaction request to a data storage device.

Abstract: Systems and methods for managing Application Programming Interfaces (APIs) are disclosed. For example, the system may include one or more memory units storing instructions and one or more processors configured to execute the instructions to perform operations. The operations may include sending a first call to a first node-testing model associated with a first API and receiving a first model output comprising a first model result and a first model-result category. The operations may include identifying a second node-testing model associated with a second API and sending a second call to the second node testing model. The operations may include receiving a second model output comprising a second model result and a second model-result category. The operations may include performing at least one of sending a notification, generating an updated first node-testing model, generating an updated second node-testing model, generating an updated first call, or generating an updated second call.

Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.

Abstract: Communication between one communication bus having one set of characteristics and another communication bus having another set of characteristics is facilitated by a bridge coupling the two communication buses. The bridge includes a scoreboard to manage data communicated between the buses. In one particular example, the one communication bus is a Processor Local Bus (PLB6) and the other communication bus is an Application Specific Integrated Chip (ASIC) Interconnect Bus (AIB).

Abstract: Neutron multiplicity detector control logic and firmware may control a neutron multiplicity detector such that higher count rates can be achieved by an order of magnitude of more over conventional control logic and firmware. Count rates of over 1,000,000 cps, and even over 1,500,000 cps, have been realized in some implementations.

Abstract: A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first data packets with an unordered attribute being set to an ordering controller. The computer system further comprises the coupling device configured to send second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The computer system further comprises the ordering controller configured to send the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

Abstract: Embodiments of the present invention provide methods, program products, and systems to increase efficiency in message oriented middleware. Embodiments of the present invention can, responsive to receiving from an application an open request for a queue alias of a queue manager, provide to the application target cache information which includes a target name and a change flag count associated with the queue alias. Embodiments of the present invention can, responsive to receiving a message from the application that includes respective target cache information including a target name and a change flag count, determine a target location, wherein if the change flag count of the received message matches a current change flag count of the queue alias, the determined target location is a target location associated with the received target name.

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

Abstract: Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween.

Abstract: In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing; the reliable TLP transmission module, configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time, so that a destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC, thereby implementing reliable transmission of a TLP in a case of a PCIE switching dual-plane networking connection.

Abstract: A bistable cell includes a pair of inverters and multiple pairs of cross-coupled tristate buffers. Each pair of tristate buffers can be individually selected to implement an entropy harvesting state for the bistable cell. Each of the tristate buffers generally has lower strength than the inverters but the inverter-to-buffer strength ratio can be configured through selective use of one or more of the tristate buffer pairs. The resulting entropy harvesting state behavior can be varied based on the inverter-to-buffer strength ratio in terms of greater randomness of the output bits or decreased power consumption.

Abstract: This disclosure pertains to using traffic classes to selectively store data into cache memory or into system memory. A cache controller can map the traffic class of incoming data to portions of the cache memory allocated for corresponding traffic classes of data.

Abstract: A system and method for clock phase alignment at a plurality of line cards over a backplane of a communication system. Phase adjustments are continually made for the clock signals at the line cards by dynamically measuring the propagation delay between the timing device and each of the plurality of line cards and continuously communicating the appropriate phase adjustment to each of the plurality of line cards.

Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.

Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.

Abstract: A driver includes a plurality of driver chips and an operation method thereof are provided. Each of driver chips includes a first transmission interface, a second transmission interface and a third transmission interface. The driver chips are coupled to each other by the first transmission interfaces and the second transmission interfaces, and the third transmission interfaces are commonly coupled to a parameter source to receive a plurality of operation parameters during an operation initiating period. When an abnormal signal is not returned after receiving the operation parameters, the driver chips end the operation initiating period. When the abnormal signal is returned after receiving the operation parameters, the driver chips receive the operation parameters again.

Abstract: Conference systems are often installed in plenary halls or meeting rooms, whereby such conference systems typically consist of a central equipment and equipment for the participants of the discussion. The central equipment is usually used to control the conference system and supply power to the participant equipment.

Abstract: A method for scheduling read and write commands, performed by a processing unit, including at least the following steps: the processing unit obtains more than one read commands from a read queue successively and executes the obtained read commands until a first condition is met. After the first condition is met, the processing unit obtains more than one write commands from a write queue successively and executes the obtained write commands until a second condition is met.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a CAN device includes a security module connected between a CAN bus interface of a CAN transceiver and a microcontroller communications interface of the CAN transceiver and an operational mode controller connected between the security module and the CAN bus interface. The security module is configured to perform a security function on data traffic received from the CAN bus interface or from the microcontroller communications interface. The operational mode controller is configured to set an operational mode for the CAN transceiver such that a CAN Flexible Data-rate (FD) frame or a corresponding CAN frame is output from the CAN bus interface. An identifier of the CAN FD frame is the same as an identifier of the corresponding CAN frame.

Abstract: Techniques are disclosed relating to an in-memory cache for web application data. In some embodiments, received transactions include multiple operations, including one or more cache operations to access the in-memory cache. In some embodiments, transactions are performed atomically. In some embodiments, data for the one or more cache operations is stored locally in memory by an application server outside of the in-memory cache until the transaction is successfully completed. This may improve performance and facilitate atomicity, in some embodiments.

Abstract: A method or system for determining a required certification level of storage area for storing data of a write request based on a characteristic of the data, selecting a target storage area based on a media certification table and the required determined certification level of the media area and storing data at the target storage area.

Abstract: Generally, this disclosure describes techniques for buffer management based on link status. A host platform may include a Baseboard Management Controller (BMC) and a network controller that includes a buffer used by the BMC. When a network controller is in a lower power link state, the BMC may attempt to send data to the link partner which causes the network controller to transition out of the low power state. However, this transition may take longer than the buffer's ability to buffer the incoming flow from the BMC. Accordingly, to avoid the need for larger buffer space, a buffer manager is used to provide flow control management of the buffer based on link status.

Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract: A compute node with multiple transfer processes that share an Infiniband connection to send and receive messages across a network. Transfer processes are first associated with an Infiniband queue pair (QP) connection. Then send message commands associated with a transfer process are issued. This causes an Infiniband message to be generated and sent, via the QP connection, to a remote compute node corresponding to the QP. Send message commands associated with another process are also issued. This causes another Infiniband message to be generated and sent, via the same QP connection, to the same remote compute node. As mentioned, multiple processes may receive network messages received via a shared QP connection. A transfer process on a receiving compute node receives a network message through a QP connection using a receive queue. A second transfer process receives another message through the same QP connection using another receive queue.

Abstract: Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order.

Abstract: In an system on a chip, multiple PCIe controllers may be present in which each PCIe controller may be configured to route input data to either itself or to another PCIe controller based on a priority level of the input data. Similarly, each PCIe controller may be configured to route output data by way of its own PCIe link or that of another PCIe controller based on a scheduling order which may be based on a priority level of the buffer in which the output data is stored. In this manner, multiple PCIe controllers which, in a first mode, are capable of operating independently from each other can be configured, in a second mode, to provide multiple channels for a single PCIe link, in which each channel may correspond to a different priority level.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: A transaction processing method is disclosed to solve the issue of multiple producers (software and hardware) and one or more consumers operating in a peer or hierarchical system. The transaction processing method is a deterministic method operable in a system having any number of producers. The producers themselves may be any combination of hardware and software and may be part of peer or hierarchical systems.

Abstract: Systems and methods are provided for managing power of a device coupled with a transceiver module, in communication with a high-speed interface. In one aspect, a dynamic clock trunk tree associated with the transceiver module is controlled by a trunk driver having a first clock tree gate. A dynamic clock leaf tree associated with the device is controlled by a leaf driver having a second clock tree gate. Significant power savings may be achieved, for example, by triggering activation of clock gating mechanisms.

Abstract: A method of transferring data in a flash storage device is provided. A plurality of data segments for transfer between a memory buffer and a plurality of flash memory devices via a plurality of flash memory interfaces is associated with a plurality of respective memory commands. The plurality of memory commands are allocated among the plurality of flash memory interfaces, with each respective memory command being queued at a respective memory interface for transfer of a respective data segment associated with the respective memory command. The plurality of data segments are transferred between the memory buffer and the plurality of flash memory devices based on the plurality of memory commands, with each respective data segment being transferred via the memory interface to which the memory command associated with the respective data segment is queued. The data segments are transferred sequentially in an order corresponding to the queued memory commands.

Abstract: An interconnect architecture device of an aspect includes a processor to generate a transaction that is of a different interconnect protocol than LLI. The interconnect architecture device also includes conversion logic coupled with the processor. The conversion logic is to convert the transaction, which is of the different interconnect protocol than LLI, to an LLI packet. The interconnect architecture device also includes an LLI controller coupled with the conversion logic. The LLI controller is to couple the interconnect architecture device with an LLI link. The LLI controller is to transmit the LLI packet on the LLI link.

Abstract: A method of avoiding unnecessary context switching in a multithreaded environment. A thread of execution of a process waiting on a lock protecting access to a shared resource may wait for the lock to be released by executing in a loop, or “spin”. The waiting thread may continuously check, in a user mode of an operating system, an indicator of whether the lock has been released. After a certain time period, the thread may stop spinning and enter a kernel mode of the operating system. Subsequently, before going to sleep which entails costly context switching, the thread may perform an additional check of the indicator to determine whether the lock has been released. If this is the case, the thread returns to user mode and the unnecessary context switching is avoided.

Abstract: A system and method for I/O optimization in a multi-queued environment are provided. In one embodiment, a host is provided that sorts commands into a plurality of queues, wherein a command is sorted based on its data characteristic. The host receives a read request from a storage module for commands in the plurality of queues and provides the storage module with the requested commands. In another embodiment, a storage module is provided that processes commands from a host based on the data characteristic of the queue that stored the command on the host. In another embodiment, a storage module sorts command completions into a plurality of queues, wherein a command completion is sorted based on its resulting status code.

Abstract: A system for adaptive application of device settings is disclosed. In the system, a first device may receive information identifying settings that are applied to one or more second devices. The settings may correspond to interactions, by a user, with the one or more second devices over a period of time. The one or more second devices be may non-mobile devices associated with one or more facilities. The first device may determine information identifying one or more conditions, associated with environmental conditions or conditions associated with the user's mood or physical state, under which the settings are applied to the one or more second devices; store information that correlates the settings of the one or more second devices with the one or more conditions; determine that at least one of the one or more conditions is met; and apply the settings to the one or more second devices.

Abstract: Generally, this disclosure provides systems and methods for providing forward compatibility between a driver module and one or more present or future versions of a network interface. The system may include a network interface configured to transfer data between a host system and a network; and a programmable circuit module associated with the network interface, the programmable circuit module configured to provide compatibility between the network interface and a driver module associated with the host system, wherein the driver module includes a first set of capabilities and the network interface includes a second set of capabilities.

Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor memory device. The controller generates a first command signal and receives a foreground data to generate a foreground control signal for controlling a drivability of the foreground data and to generate a second command signal. The semiconductor memory device receives the first command signal to output a pattern data as the foreground data through a foreground input/output (I/O) line, stores the foreground control signal therein in response to the second command signal, and controls the drivability of the foreground data according to the foreground control signal.

Abstract: An order controller stores each received event in a separate entry in one of at least two queues with a separate counter value set from an arrival order counter at the time of storage, wherein the arrival order counter is incremented after storage of each of the received events and on overflow the arrival order counter wraps back to zero. The order controller calculates an absolute value of the difference between a first counter value stored with an active first next entry in a first queue from among the at least two queues and a second counter value stored with an active second next entry in a second queue from among the at least two queues. The order controller compares the absolute value with a counter midpoint value to determine whether the first counter value was stored before the second counter value.

Abstract: A multiprocessor system includes a plurality of master devices, at least one slave device, and a system bus connecting the master devices to the at least one slave device. At least one of the master devices includes at least one cache memory, and the system bus processes a data write or data read request corresponding a transaction issued to the slave device from at least one of the master devices prior to termination of a snooping operation on the master devices.

Abstract: A power disconnect unit within a data transport topology of a NoC includes an asynchronous clock domain adapter unit inserted between a master side manager unit and a slave side manager unit. This configuration allows for the master and slave side managers of the power disconnect unit to be placed physically far apart on the chip, relieving the need to route long power rail signals on the chip. A response data path and associated asynchronous clock domain adapter unit is optionally included on the chip. A path to bypass the asynchronous clock domain adapter units is optionally included on the chip to enable a fully synchronous mode of operation without the data latency cost of the asynchronous adapter unit.

Abstract: An electronic device is provided, including an input output expander, at least one electronic device and a control module. The input output expander outputs a power source to a peripheral device by at least one output terminal The electronic device is coupled to the input output expander in a daisy chain configuration. The control module adjusts current powers of the electronic device and the peripheral device according to real time powers of the electronic device and the peripheral device, a maximum output power and parameters, thereby preventing power outputted by the input output expander from being larger than the maximum output power.

Abstract: An order controller stores each received event in a separate entry in one of at least two queues with a separate counter value set from an arrival order counter at the time of storage, wherein the arrival order counter is incremented after storage of each of the received events and on overflow the arrival order counter wraps back to zero. The order controller calculates an absolute value of the difference between a first counter value stored with an active first next entry in a first queue from among the at least two queues and a second counter value stored with an active second next entry in a second queue from among the at least two queues. The order controller compares the absolute value with a counter midpoint value to determine whether the first counter value was stored before the second counter value.

Abstract: One embodiment of the present invention provides a switch that includes a transmission mechanism configured to transmit frames stored in a queue, and a queue management mechanism configured to store frames associated with the queue in a number of sub-queues which allow frames in different sub-queues to be retrieved independently, thereby facilitating parallel processing of the frames stored in the sub-queues.

Abstract: Techniques for storage network bandwidth management are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for storage network bandwidth management comprising sampling, using at least one computer processor, application Input/Output (I/O) requests associated with the unit of storage during a specified period of time, determining a maximum latency value based on the sampling of the application Input/Output (I/O) requests, comparing the maximum latency value with a current latency value, and throttling administrative I/O requests in the event that the current latency value exceeds the maximum latency value.

Abstract: Aggregation of contiguous data packets, such as contiguous I/O adapter stores, is disclosed. Commensurate with receiving data packets to be written to a memory, multiple contiguous data units of the data packets are aggregated into an aggregated data block. The aggregated data block is validated for writing to memory responsive to either the aggregated data block reaching a size which with inclusion of a next contiguous data unit in the aggregated data block would result in the aggregated data block exceeding a configurable size limit, or a next data unit of the plurality of data units to be written to memory being non-contiguous with the multiple contiguous data units.

Abstract: A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

Abstract: An audio system including a first audio unit and a second audio unit coupled to the first audio unit through an audio bus. A first processor is coupled to the first audio unit. The first processor is configured to transmit bits comprising audio content to the second audio unit over the audio bus. The first processor is further configured to receive a control command selected from a plurality of control commands, and in response, interrupt the bits comprising audio content and send a preamble and a control message on the audio bus, wherein the control message corresponds to the control command. A second processor is coupled to the second audio unit. The second processor is configured to monitor the audio bus for a preamble, and if a preamble is detected, then process the control message and execute the corresponding control command.