Abstract: According to certain aspects, the present invention relates to a system and method of sending PCI Express video data over a lower speed Ethernet connection. In embodiments, a system according to the invention includes bridges at either end of an Ethernet connection that is disposed between a PCIe host and a PCIe device. According to aspects of the invention, the slower Ethernet connection can be used by forcing the faster PCIe link to operate at a slower rate than is possible, forcing a PCIe device with a large number of lanes to use only a single lane, forcing a PCIe link to use the shortest possible packet size and/or controlling the time when UpdateFC DLLP packets are sent.

Abstract: According to one exemplary embodiment, a host/client system includes a host module, which includes a CPU coupled to a system bridge. The host/client system further includes at least one client having an integrated interface, where the integrated interface is coupled to the system bridge through a scalable serial bus. The system bridge and the integrated interface enable high bandwidth communication between the CPU and the at least one client through the scalable serial bus, thereby allowing control of bus width between the host module and the client.

Abstract: An apparatus including a plurality of internal devices that communicates concurrently with a controller by one of the MDIO protocol and the SPI protocol is disclosed. The controller of the invention couples with respective devices by the point-to-point arrangement. The controller couples with the external apparatus by the MDIO protocol and receives a packet containing an address of one of internal devices, the controller communicates with the device defined by the address by the protocol attributed to the device.

Abstract: An I/O bridge device includes: a command receiver that receives a command signal indicating a command to a memory controller from a peripheral component; a converter that converts the command signal into a command packet including the command and identification information for identifying the command signal; a command transmitter that transmits the command packet to the memory controller; a response receiver that receives, from the memory controller, a response packet to the command packet, the response packet including the identification information; and a write command transmitter that transmits a write command signal to the peripheral component that is a transmission source of the command signal, the write command signal indicating a command for the writing a content of the response packet to an internal memory of the peripheral component.

Abstract: A switch apparatus capable of being coupled to a computer and a plurality of devices, the switch apparatus includes: a first bridge coupled to the computer; a second-bridge group coupled to the devices; and a controller for controlling the connection relationship between the first bridge and the second-bridge group, wherein the controller assigns physical identifiers having different bus identifiers to the plurality of devices, assigns logical identifiers to the devices in accordance with an identifier assigned to the first bridge in response to an instruction for reading connection states of the devices received from the computer when the computer is coupled to the first bridge, and converts a physical identifier and a logical identifier of a packet transmitted between the first bridge and the second-bridge group in accordance with the correspondence relationships between the physical identifiers and the logical identifiers.

Abstract: A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output.

Abstract: Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed.

Abstract: A computer system and a method are provided for accessing a peripheral component interconnect express PCIe endpoint device. The computer system includes: a processor, a PCIe bus, and an access proxy. The access proxy connects to the processor and the PCIe endpoint device; the processor acquires an operation instruction, where the operation instruction instructs the processor to access the PCIe endpoint device through the access proxy, and send an access request to the access proxy according to the operation instruction; and the access proxy sends a response message of the access request to the processor after receiving the access request sent by the processor. Because the processor does not directly access the PCIe endpoint device to be accessed but completes access through the access proxy, thereby avoiding an MCE reset for the processor.

Abstract: Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system.

Abstract: A bus system includes: a first connection apparatus and a second connection apparatus carrying-out an exchange in accordance with a predetermined protocol; a bus through which the first and second connection apparatuses are connected to each other; and a bridge inserted between the first connection apparatus and the bus, and carrying out an exchange with the second connection apparatus in accordance with the predetermined protocol instead of the first connection apparatus when receiving a disconnection instruction for the first connection apparatus.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A collaborative bus arbitration multiplex architecture includes of a main memory, a bus, a plurality of BMPDs, and a BAM. Arbitration can be done according to the following steps of awaiting whether any of the BMPDs renders any request for access; B) identifying whether the access authority of the bus is being fetched by any other BMPDs; C) identifying whether the main memory to which the request for access corresponds have any record that the corresponding BMPD needs special treatment; D) identifying whether all of the BMPDs have rendered the requests for access; E) according to a generic arbitration principle, identifying whether the corresponding BMPDs indicated in the steps C) and D) win the access authority; F) yielding the access authority of the bus to the BMPDs winning the access authority as indicated in the step E); and G) accessing the main memory.

Abstract: An apparatus adapts a pre-designed circuit module not supporting a power management protocol to a power management protocol. The apparatus disconnects a bus interface, disables interrupt and stops a clock to the pre-designed circuit module on a external idle request signal.

Abstract: Certain aspects of an apparatus and method for interconnection may include an interconnection section, a request processing section and a response processing section. The interconnection section may be configured to transfer a request from a master interface bus to a slave interface bus and to transfer a response from the slave interface bus to the master interface bus. A slot number within the request specifies a time slot during which the interconnection section may be permitted to transfer the response to the master interface bus. The request commands the processing section to load the slot number into a management table. The response commands the response processing section to read out the slot number from the management table.

Abstract: In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled between the MCP and an off-package agent and another PtP link coupled between first and second processors of the MCP, where the on-package PtP link operates at a greater bandwidth than the first PtP link. Other embodiments are described and claimed.

Abstract: A SAS expander forms a first path coupling the SAS initiator and a first port of a SAS target together. The first SAS expander notifies the SAS initiator of a virtual expander address instead of a SAS address of the first SAS expander. The first SAS expander notifies the SAS initiator of a virtual target port address, at least instead of a SAS address of the first port of the SAS target. A second SAS expander forms a second path coupling the SAS initiator and a second port of the SAS target together. The second SAS expander notifies the SAS initiator of the virtual expander address instead of a SAS address of the second SAS expander. The second SAS expander notifies the SAS initiator of the virtual target port address, at least instead of a SAS address of the second port of the SAS target.

Abstract: Systems and methods for providing a vehicular navigation control are disclosed herein. Some embodiments include a navigation system and a vehicle with a vehicle control module (VCM), a navigation control module (NCM), and a navigation control interface, where the VCM receives a manual command from an operator to implement a manual control function. In some embodiments the NCM receives an automatic command from the navigation system to implement an automatic control function via the VCM and the navigation control interface directly connects the VCM and the NCM to facilitate communication between the VCM and NCM for implementing automatic mode and for reporting implementation of a manual mode.

Abstract: A method of conversion by at least one interface circuit connected between a first bus including at least one data wire and one clock wire, and at least one second single-wire bus, of a transmission between a master circuit connected to the first bus and at least one slave circuit connected to the second bus, wherein a speculative read command is sent to the slave circuit before interpreting the state of a bit for controlling a reading or a writing, originating from the master circuit.

Abstract: A system-on-a-chip (SOC) bridge is described that applies an adapted delay, or latency, to data transfers across the bridge to avoid data corruption without reducing data transfer performance. The adapted delay assures that a source SOC service device transferring data to a destination SOC service device via the bridge and an SOC crossbar bus does not prematurely assume that the data transfer is complete upon transferring the data to the bridge. The bridge causes wait states to be inserted into the transfer between the source SOC service device and the SOC bridge until the SOC bridge receives confirmation that the data has arrived at the destination SOC service device. The adapted delay assures that subsequent operations are not prematurely initiated by the source SOC service device and/or the SOC CPU that may interfere with the data transfer from the SOC bridge to the destination SOC service device, causing corrupted data.

Abstract: A method for implementing connected input/output (I/O) hub configuration and management includes configuring a first I/O hub in wrap mode with a second I/O hub. The hubs are communicatively coupled via a wrap cable. The method further includes generating data traffic on a computing subsystem that includes the hubs. Generating traffic includes: converting, via the first hub, a request to implement a transaction into an I/O device-readable request packet and transmitting the request packet over the wrap cable; converting, via the second hub, the I/O device-readable (IODR) request packet into a system readable request and transmitting the request over a system bus; converting, via the second hub, the response to an IODR response packet, and transmitting the response packet over the wrap cable; and converting, via the first hub, the IODR response packet into a system readable response packet, and transmitting the response packet over the system bus.

Abstract: An interface comprises a storage device controller that controls data flow from a Serial ATA bus to a storage device. A configurable bridge circuit is configured in one of a plurality of operating modes including a device bridge mode, and converts Parallel ATA information received on a Parallel ATA bus to Serial ATA information output to the Serial ATA bus when in the device bridge mode.

Abstract: Embodiments of the invention relate to upbound input/output expansion requests and response processing in a PCIE architecture. A first request to perform an operation on a host system is intitiated. The first request is formatted for the first protocol and includes data that is required in order to process the first request. A second request is created in response to the first request, the second request includes a header and is formatted according to the second protocol. The data required to process the first request in the header of the second request is stored, and the second request is sent to the host system.

Abstract: Transactions of the request/response type between a first circuit module and a second circuit module operating with incompatible protocols or interfaces envisage organizing a queue of memory locations for storing transaction information items and transaction identifiers associated to said transactions and implementing the transactions via operations of reading/writing of the locations in the queue, mapping on the transaction identifiers information for management of the queue.

Abstract: An integrated circuit system includes: a first integrated circuit that is connected with a first data bus having first bus width and requires first time to perform data transmission and reception once; a second integrated circuit that is connected with a second data bus having second bus width larger than the first bus width in bit width and requires second time longer than the first time to perform data transmission and reception once; and a relay circuit that is connected with the first data bus and the second data bus and transmits and receives data to and from the first integrated circuit and the second integrated circuit respectively via the buses.

Abstract: A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

Abstract: An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is op

Abstract: In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.

Abstract: In an embodiment, a translation of a hierarchical bus number to a physical bus number and a bridge identifier of a bridge are written to a north chip. A request is received that comprises an identifier of a destination. A determination is made that the identifier comprises the hierarchical bus number. In response to the determination, the identifier of the destination is replaced in the request with the physical bus number and the bridge identifier. The request is sent to the bridge identified by the bridge identifier. A south chip comprises the bridge, and the south chip is connected to the north chip via a point-to-point serial link. The physical bus number identifies a bus that connects the bridge to a device. The request comprises a configuration write request that requests a write of data to the device.

Abstract: An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PHY.

Abstract: A method and system to improve the operations of an integrated non-transparent bridge device (NTB) that is coupled to another NTB device or Root Port device. The integrated NTB device has logic to maintain ordering of interrupts to be sent to the remote Root Port or NTB device. The integrated NTB device allocates a contiguous portion of the memory for both the primary Base Address Register 0 associated with the integrated NTB device and the secondary BAR0 associated with the remote NTB device. The integrated NTB device has logic to report the size of the primary BAR0 as the combined size of the primary BAR0 and the size of the secondary BAR0. The integrated NTB device facilitates the dynamic modification of a mapping of each bit of a doorbell register with a respective one of a plurality of interrupt vectors based on a mapping register.

Abstract: A system to mate logic nodes may include a connector to secure at least one of an inter-nodal circuit and a fabric bus, where the inter-nodal circuit provides communications between any connected logic nodes, and the fabric bus provides logical connections to a first logic node and any other logic node. The system may also include an element carried by the connector configured to provide an appropriate actuation force to mate the connector and at least one of the inter-nodal circuit and the fabric bus.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: An automation appliance (6) having at least one field bus interface (12) for connection to a field bus (2) and transmission of data packets (DP) with process data (PD) via the field bus (2) and having at least one local bus interface (21) for connection to a local bus (7) and transmission of process data (PD) between field devices (9a, 9b, 9c) connected to the local bus (7) and the automation appliance (6), and having means for converting the data packets (DP) coming from the field bus (2) into a data stream (DS) for the local bus (7) and for converting the data stream (DS) sent from the local bus (7) to the automation appliance (6) into data packets (DP) for the field bus (2) is described.

Abstract: Systems and methods schedule periodic and non-periodic transactions in a multi-speed bus environment that includes in a downstream hub a data forwarding component, such as a USB transaction translator, which accommodates communication speed shifts at the hub. The method may comprise receiving a split packet request defining a transaction with a device, tagging the request with an identifier allocated to the data forwarding component, storing the request in a transaction list associated with the identifier, initiating transfer of payload data, and updating a counter associated with the identifier to reflect an amount of payload data for which transfer was initiated. The identifier may have associated therewith a counter for tracking a number of bytes-in-progress to the data forwarding component and one or more transaction lists configured to store a plurality of split packet requests awaiting execution and state information regarding an execution status of the requests.

Abstract: An apparatus and method of low latency precedence ordering check in a PCI Express (PCIe) multiple root I/O virtualization (MR-IOV) environment. The precedence ordering check mechanism aids in enabling a port to comply with PCIe MR-IOV ordering rules. A posted information array mirrors a posted transaction queue, storing precedence order indicator and Virtual Hierarchy (VH) tag information for corresponding posted transaction entries stored in the posted transaction queue. The selector queries the posted information array periodically, such as each cycle, to determine whether the non-posted/completion transaction at the output of their respective queues have any preceding posted transactions of the same VH somewhere in the posted queue.

Abstract: An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.

Abstract: An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I2C) or I2C compatible bus. The IC is further configured to receive an address through the I2C bus and store the received address in a register, so as to be identified by the address. A method of address assignment in a master/slave system, the system comprises at least one master, a plurality of slaves, and an I2C or I2C compatible bus. The method comprises sending a first address by the master on the I2C bus to a first of the plurality of slaves and storing the first address on the first slave to identify the first slave by the first address. The method further comprises sending a second address by the master on the I2C bus to a second of the plurality of slaves and storing the second address on the second slave to identify the second slave by the second address. The steps of sending and storing are repeated until all slaves of the system have stored an address.

Abstract: A method and system for dynamically managing a bus within a portable computing device (“PCD”) are described. The method and system include monitoring software requests with a bus manager. The bus manager determines if a software request needs to be converted into at least one of an instantaneous bandwidth value and an average bandwidth value. The bus manager then converts the software requests into these two types of values as needed. The bus manager calculates a sum of average bandwidth values across all software requests in the PCD. With these values, the bus manager may dynamically adjust settings of the bus based on instantaneous or near instantaneous demands from the master devices. This dynamic adjustment of the bus settings may afford more power savings for the PCD during low loads or during sleep states.

Abstract: The present invention is directed to a method for implementing firmware in an expander system in such a way that a single hardware component (ex.—a chip) of the expander system may be presented as multiple virtual expanders to both upstream connected devices (ex.—HBAs) as well as downstream connected devices (ex.—disk drives).

Abstract: An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location.

Abstract: A data processing system includes a processor core, a system memory coupled to the processor core, an input/output adapter (IOA), and an input/output (I/O) host bridge coupled to the processor core and to the IOA. The I/O host bridge includes a register coupled to receive I/O messages from the processor core, a buffer coupled to receive I/O messages from the IOA, and logic coupled to the register and to the buffer that services I/O messages received from the register and from the buffer.

Abstract: A technique for providing network access in accordance with at least one layered network access technology comprising layer 1 processes and layer 2 processes is described. In a device implementation, the technique comprises a shared memory adapted to store at least layer 1 data and layer 2 data as well as a memory access component coupled to the shared memory and comprising a first client port adapted to receive memory access requests from a layer 1 processing client and a second client port adapted to receive memory access requests from a layer 2 processing client. The memory access component is configured to serve a memory access request from the layer 1 processing client with a lower priority than a memory access request from the layer 2 processing client. In particular, the memory access component may be adapted to prioritize reading of layer 1 data by the layer 2 processing client over writing of layer 2 data by the layer 1 processing client.

Abstract: In accordance with an embodiment, a method of operating a bus interface circuit includes detecting a start sequence on a plurality of input terminals, determining whether a first input terminal and a second input terminal is a data terminal and a clock terminal, respectively, or whether the first input terminal and the second terminal is a clock terminal and a data terminal, respectively. The method also includes routing the first input terminal to a data terminal and the second input terminal to a clock terminal if first input terminal and the second input terminal are determined to be a data terminal and a clock terminal, respectively, and routing the first input terminal to the clock terminal and the second input terminal to the data terminal if first input terminal and the second input terminal are determined to be a clock terminal and a data terminal, respectively.

Abstract: A data processing system includes a processor core, a system memory coupled to the processor core, an input/output adapter (IOA), and an input/output (I/O) host bridge coupled to the processor core and to the IOA. The I/O host bridge includes a register coupled to receive I/O messages from the processor core, a buffer coupled to receive I/O messages from the IOA, and logic coupled to the register and to the buffer that services I/O messages received from the register and from the buffer.

Abstract: A method for implementing connected input/output (I/O) hub configuration and management includes configuring a first I/O hub in wrap mode with a second I/O hub. The hubs are communicatively coupled via a wrap cable. The method further includes generating data traffic on a computing subsystem that includes the hubs. Generating traffic includes: converting, via the first hub, a request to implement a transaction into an I/O device-readable request packet and transmitting the request packet over the wrap cable; converting, via the second hub, the I/O device-readable (IODR) request packet into a system readable request and transmitting the request over a system bus; converting, via the second hub, the response to an IODR response packet, and transmitting the response packet over the wrap cable; and converting, via the first hub, the IODR response packet into a system readable response packet, and transmitting the response packet over the system bus.

Abstract: A control method for extender is proposed. A transmitting unit stops outputting image signal, voice signal or serial data to a receiving unit. A request signal is sent from the transmitting unit to the receiving unit by using the circuit through which the transmitting unit stops outputting image signal, voice signal or serial data to the receiving unit. Extended display identification data of a display device or peripheral data of a control device is sent from the receiving unit to the transmitting unit.

Abstract: Described embodiments provide a system having a bridge for communicating information between two processor buses. The bridge receives a command from a first bus, the command having an identification field and an address field. As the command is entered into a buffer in the bridge, the address field is checked against one or more addresses. If there is a match, then control bits are checked to see if the command will be allowed or not depending on the identification field value. If the command is not transferred to the second bus, a flag is set in the buffer, and an error message is returned to the first bus, and an interrupt may be generated. The control bits allow commands access to specific addresses on the second bus or deny the access depending on the command identification field. Bit-wise masking provides a range of values for identification and address field matching.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a command from a first bus, the command having an identification field having a value. The command is then entered into a buffer in the bridge unless another command having the same identification field value exists in the buffer. Once the command with the same identification field value is removed from the buffer, the received command is entered into the buffer. Next, the buffered command is transmitted over a second bus. A response to the command is eventually received from the second bus, the response is transmitted over the first bus, and the command is then removed from the buffer. By not entering the received command until a similar command with the same identification value is removed from the buffer, command ordering is enforced even though multiple commands are pending in the buffer.