Abstract: A network bridge with a configuration and control unit. The unit is connected to some or all of the functional components of the network bridge via interfaces. The unit may poll and evaluate data within the functional components, including operating data and/or parameters. The unit may manipulate the data and/or parameters within the functional components, based on the evaluation of that data.

Abstract: Methods and apparatus to enhance performance of Serial Advanced Technology Attachment (SATA) disk drives in Serial-Attached Small Computer System Interface (SAS) domains are described. In one embodiment, a data packets and/or commands communicated in accordance with SAS protocol may be converted into SATA protocol. Other embodiments are also described.

Abstract: In a programmable controller including a special unit, a special-purpose integrated circuit element can be readily utilized for multiple purposes to extend the range of applications to reduce a manufacture cost. A special unit (130) connected to a microprocessor for performing I/O control through a bus includes an integrated circuit element (10) having a logic circuit unit (1000n (n=0 to 7)) whose operation specifications are determined by a parameter memory. The logic circuit unit (1000n) includes a reversible counter used for both high-speed input processing and high-speed output processing as a main component, and is connected to I/O interface circuits (139X) (139Y) through a first port (11) and a second port (12).

Abstract: An IEEE 802.3 compliant physical layer device provides efficient loading of configuration information of the physical layer device. The configuration information is written into a volatile memory in the physical layer device, and then uploaded to at least one EEPROM. The configuration information is downloaded to the volatile memory during startup of the physical layer device. The system controller can also directly access the EEPROMs, bypassing the volatile memory. By providing a bridge between the system controller and the EEPROMs and providing additional bits in the volatile memory of the physical layer device, the system controller can read and write the EEPROMs one byte at a time. During reset time, the content of the EERPOMs is written to registers in the physical layer device to configure the physical layer device.

Abstract: An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure execution mode logic that is configured to monitor instructions within the secure application program, and that is configured to preclude execution of certain instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.

Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Abstract: A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected to the south bridge, and a resource manager coupled to the south bridge that allocates use of the at least one device between the first processor and the second processor.

Abstract: A method is provided for supporting device sharing between hosts via a bus fabric. A master host owns a device tree and provides IO services to at least one client host. The client host comprises generic device drivers and subscribes to IO services provided by the master host.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A programmable control interface is for circuits using complex commands. The programmable interface includes a memory for storing sampled commands and a sequencing circuit. The sequencing circuit is programmable. Thus, a processor downloads into the programmable interface a sequencing specific to the sequence of commands. Once the programmable interface has been programmed, the processor launches the start of the sequence and the programmable interface manages and controls in a standalone manner the inputs/outputs with the slave circuit. The management and control of the slave circuit is independent of any interrupt specific to the system. The programmable interface uses a software-type upgrade to interface with new slave circuits that may appear on the market.

Abstract: An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor, a bridge, and circuitry capable of coupling the bridge and the processor to a first bus and to a second bus. The first bus may be compatible with a first bus protocol, the second bus may be compatible with a second bus protocol, and the first and second bus protocols may be different from each other. The bridge may be capable of, in response at least in part to a request from the processor, preventing a command received at the bridge via the first bus from being forwarded from the bridge to the second bus. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: Systems and methods for providing distributed technology independent memory controllers. Systems include a computer memory system for storing and retrieving data. The system includes a memory bus, a main memory controller, one or more memory devices characterized by memory device protocols and signaling requirements, and one or more memory hub devices. The main memory controller is in communication with the memory bus for generating, receiving, and responding to memory access requests. The hub devices are in communication with the memory bus and with the memory devices for controlling the memory devices responsively to the memory access requests received from the main memory controller and for responding to the main memory controller with state or memory data.

Abstract: Intelligent NIC optimizations includes system and methods for Token Table Posting, use of a Master Completion Queue, Notification Request Area (NRA) associated with completion queues, preferably in the Network Interface Card (NIC) for providing notification of request completions, and what we call Lazy Memory Deregistration which allows non-critical memory deregistration processing to occur during non-busy times. These intelligent NIC optimizations which can be applied outside the scope of VIA (e.g. iWARP and the like), but also support VIA.

Abstract: Provided are a guaranteed isochronous services method and apparatus in bridged LAN. Isochronous streams are transmitted through bridges to a plurality of listener stations in a distributed network, and each bridge performs filtering, stream group registration and authentication for the isochronous streams. Accordingly, quality of service (QoS) in a distributed network can be improved. Furthermore, isochronous streams to the plurality of listener stations can be guaranteed.

Abstract: An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.

Abstract: A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to track performance and reliability statistics per virtual upstream and downstream port, thereby allowing a system and network management to be performed at finer granularity than what is possible using conventional physical port statistics, is provided. Particularly, a mechanism of managing per-virtual port performance metrics in a logically partitioned data processing system including allocating a subset of resources of a physical adapter to a virtual adapter of a plurality of virtual adapters is provided. The subset of resources includes a virtual port having an identifier assigned thereto. The identifier of the virtual port is associated with an address of a physical port. A metric table is associated with the virtual port, wherein the metric table includes metrics of operations that target the virtual port.

Abstract: A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function as a bootable memory. In addition, the device can act as a cache to the hard disk drive. Further, with the addition of an MP3 player controller into the device, the device can function as a stand alone audio playback device, even while the PC is turned off or is in a hibernating mode. Finally with the MP3 player controller, the device can access additional audio data stored on the hard drive, again with the PC in an off mode or a hibernating mode. Finally, the device can function to operate the disk drive, even while the PC is off or is in a hibernating mode, and control USB ports attached thereto.

Abstract: A virtualization of the internal interconnection bus, which results in a virtualized switch or virtualized multi-ported bridge. In the case of a PCI Express switch, one embodiment includes virtualization of the undefined interconnection bus. In the case of a Multi-ported bridge, one embodiment includes virtualization of the internal PCI/PCI-X bus. Through virtualization of the internal interconnection bus, the integrated circuit topology (the physical bridges and ports) may advantageously be spatially separated and remotely distributed far a field from the host computer, yet appear to the host system and host system software as single physical device (i.e. a normal PCIe switch or a normal multi-ported bridge).

Abstract: A multi-processor computer system includes a memory bridge configured in a processor socket on a motherboard. The memory bridge module electrically connects a processor bus and a memory bus that connect to the processor socket. Thus, an adjacent processor is capable of accessing an unused memory by way of the processor bus, the memory bridge and the memory bus.

Abstract: Embodiments of the present invention provide a unique capability of implementing a pair of pseudo-PHY interfaces using a bridge. From the host and device perspectives, the host and device communicate through a PHY interface. The bridge, however, avoids actually using a USB PHY interface. This PHY-less bridge allows communication between a host and a device at high speeds without high-power transceivers associated with a USB PHY interface. In accordance with the present invention, a host and a device may be coupled together using a PHY-less bridge using the same interface or translating between different interfaces by using a wrapper. Such PHY-less bridges include a UTMI-to-UTMI bridge, a UTMI-to-ULPI bridge, a ULPI-to-UTMI bridge and a ULPI-to-ULPI bridge, each avoiding the need for a USB PHY interface.

Abstract: In a programmable controller including a special unit, a special-purpose integrated circuit element can be readily utilized for multiple purposes to extend the range of applications to reduce a manufacture cost. A special unit (130) connected to a microprocessor for performing I/O control through a bus includes an integrated circuit element (10) having a logic circuit unit (1000n (n=0 to 7)) whose operation specifications are determined by a parameter memory. The logic circuit unit (1000n) includes a reversible counter used for both high-speed input processing and high-speed output processing as a main component, and is connected to I/O interface circuits (139X) (139Y) through a first port (11) and a second port (12).

Abstract: An interface is provided to couple an input/output device (e.g., a network interface unit) to one or more different host system buses without altering the configuration of the device (e.g., to include logic specific to the host buses). Functionality of the device (e.g., MTU size, error detection) is therefore independent of the host bus. Host bus logic for managing operation of the host bus is augmented with logic for translating between semantics of the interface and the host bus. Also, end-to-end verification of a complex ASIC in multiple configurations or environments can be performed over the interface without probing into the ASIC.

Abstract: Embodiments of the present invention provide for conversion between command protocols. A routing device, or other device in the command path, can receive a command from an initiator, determine if the initiator and target for the command support the same command protocol and, if not, convert the command and/or response between the command protocols used by the initiator and the target. For commands not supported by the target or for particular predetermined commands, the device can generate a response to the command rather than passing the command to the target. Additionally, the device can modify responses from the target to include additional data and indications of errors according to the command protocol supported by the initiator.

Abstract: The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The bus interconnect is further configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the bus interconnect can confirm have no unexecuted memory access requests from the originating processor.

Abstract: An integrated circuit bridge device can include a first interface circuit coupled to a buffer circuit and configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus. A second interface circuit can be coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit. In addition, a controller circuit formed in the same substrate as the first and second interface circuits can be configured to enable data transfers between the third interface circuit and the first interface circuits via the buffer circuit.

Abstract: A bus connection device, in the form of a hardware dongle, can be connected to a first electronic device, in the form of a USB peripheral device, and a second electronic device can be connected thereto. The dongle can determine whether the second connected device is a USB host device or a USB peripheral device and, if the second electronic device is a USB host device, it is connected directly to the first electronic device. If the second electronic device is a USB peripheral device, the bus connection device operates to allow the first electronic device to operate as a host device. When the bus connection device is operating to allow the first electronic device to act as a USB host device, it regularly sends tokens to the first electronic device and to the second electronic device, to which the first electronic device can respond by transmitting data intended for the second electronic device, and to which the second electronic device can respond by transmitting data intended for the first electronic device.

Abstract: Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.

Abstract: Resource management techniques in multi-processor systems are described. Embodiments include a multi-processor system having a primary processor for communication with pipelined secondary processors. The secondary processors include registers containing status information for tasks executed by the respective secondary processors. The primary processor is provided with direct access to contents of the registers and manages computational and memory resources of the multi-processor system based on the acquired status information.

Abstract: An I/O bus architecture is configurable so that I/O bandwidth may be re-allocated from one I/O slot or device to another. A first intermediate bus couples a system bus interface device to a first I/O bus interface device. A second intermediate bus couples the system bus interface device to a switching device. The switching device functions to couple the second intermediate bus either to the first or to the second I/O bus interface device responsive to a steering signal. The steering signal may be configured to indicate whether or not an I/O device is coupled to the second I/O bus interface device. If so, then the second intermediate bus is coupled to the second I/O bus interface device; but if not, it is coupled to the first I/O bus interface device so that the first I/O bus interface device may utilize the extra I/O bandwidth not being used by the second I/O bus interface device.

Abstract: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.

Abstract: Optimization of the Virtual Interface Architecture (VIA) on Multiprocessor Servers using Physically Independent Consolidated NICs (Network Interface Cards) allows for improved throughput, increased resiliency and transparent fail-over; and also by hiding the actual NICs involved in particular data transactions, enables operations with substantially unmodified applications software.

Abstract: A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is pending; comparing the received vector value with a vector value of the pending interrupt; and replacing a previous vector value with the received vector value if the received vector value has higher priority. The system includes, at least one register for storing a trigger mode value which specifies whether an interrupt is edge triggered or level sensitive, and a vector address field that specifies a priority and address for an interrupt, and a mask value which masks an interrupt source. Also provided is a method for generating a fast interrupt. The method includes, receiving an input signal from a fast interrupt source; and generating a fast interrupt signal based on priority and a mask signal.

Abstract: An electronic Input/Output Interface and device abstraction system used in gaming machines includes: a game central processing unit (game “CPU”); an intelligent input/output controller board (“IOCB”); an Industry Standard Architecture PC bus (“ISA” bus); and a framed message transport protocol. The IOCB facilitates communications between the game CPU and virtual device services, which are peripheral devices associated with the gaming system. The game CPU communicates to gaming peripherals by sending virtual device messages across the ISA bus to the IOCB. The IOCB routes virtual device messages to appropriate virtual device services. Virtual device services are responsible for handling specific hardware, and include virtual device drivers on the game CPU that communicate with virtual devices on the IOCB. Use of the IOCB and the high speed interface enables the game CPU to use more of its available functions for controlling gaming functions rather than one operation of its associated peripheral devices.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A method to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The method includes detecting an incoming address on the I2C bus, translating the incoming address to an outgoing address, and communicating data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, the present invention avoids address conflicts between commonly addressed slave devices while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts.

Abstract: The inventive multiple partition computer system allows the reconfiguration of the installed hardware, possibly while the various partitions continue normal operations. This aspect includes adding and removing process cell boards and I/O from partitions which may or may not continue to run. The invention also allows changes to the association between cells, I/O and partitions. The partitions may be able to stay running, or may have to be shut down from the resulting changes. In the invention, multiple copies of the OS are running independently of each other, each in a partition that has its own cell boards with processors and memory and connected I/O. This provides isolation between different applications. Consequently, a fatal error in one partition would not affect the other partitions.

Abstract: An integrated circuit, a computer system and a method of operating an computer system is disclosed. The method includes receiving a request for an authentication, at a microcontroller and requesting security data from a security device. The method also includes receiving the security data from the security device, at the microcontroller and evaluating the security data. The method also includes approving the authentication if the security data is evaluated as acceptable.

Abstract: A bridging device has at least two ports. The first port allows the device to communicate with devices on an expansion bus and at least one other port to allow the bridge to communicate with a system memory on a system bus or other devices on another expansion bus. The device is capable of identifying at least two regions in memory, a descriptor region and a data region. A descriptor provides information about segments of data in the data region. The bridge may detect descriptors read from the memory, extract information related to data associated with those descriptors and use this information to perform prefetching of data from the system memory.

Abstract: Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A method of locating peripheral component interconnect (PCI) devices is provided. The method includes analyzing peripheral component interconnect spaces (PCI spaces) of peripheral component interconnect-peripheral component interconnect bridges (PCI-PCI bridges) of a 0-numbered bus, so as to obtain a bus number of a next bus connected to each of PCI-PCI bridges and record the bus number in a linked list; continuing to record a bus number of a next bus connected to the PCI-PCI bridges corresponding to the bus number recorded in the linked list; and when no next bus number is found, traversing and locating the PCI devices according to all of the bus numbers recorded in the linked list.

Abstract: Systems and methods for coordinating the interoperability of devices in a network are disclosed. Embodiments of the present invention may provide the ability for a host device in a storage network to inquire as to the capabilities of a storage device in a storage network. A routing device between the host and the storage device may receive a response, and if the routing device has a higher capability than the storage device the routing device may convert the response to a response that reflects the higher capabilities of the routing device before sending the response on to the host. However, if the storage device has a higher capability than the routing device, the routing device may pass the response through to the host unaltered.

Abstract: A network device is configured in a manner to prevent connectivity loops such as one way connectivity loops. A user configures a port of the network device to have an associated state. The state indicates that the port is for communication up the spanning tree towards a root network device, or down the spanning tree away from the root network device. The spanning tree protocol is then executed and determines a role for the port. The role determined by the spanning tree protocol is compared to the user selected state, and if there is an inconsistency, for example one that would indicate a one way connectivity loop, the port is blocked.

Abstract: A protocol chip and a bridge are connected to a first bus, while the bridge and a micro processor (MP) are connected to a second bus. The MP generates parameter information and writes it into a local memory (LM), and issues a write command which includes access destination information to this parameter information to a protocol chip. The bridge pre-fetches the parameter information from the LM using the access destination information within the write command which is transferred to the protocol chip via itself, and when receiving a read command from the protocol chip, transmits the parameter information which has been pre-fetched to the protocol chip via the first bus, without passing the read command through to the MP.

Abstract: A data transfer control system includes: a port control section which controls ports P1 and P2 respectively connected with an electronic instrument PC1 and an electronic instrument PC2; and a bus reset issue section which issues a bus reset. The port P2 is set to a disabled state, and then the bus reset is issued to cause the electronic instrument PC1 to acquire an access right. The port P2 is set to an enabled state after the bus reset has been issued and the electronic instrument PC1 has acquired the access right. After the electronic instrument PC2 has been detected to be in a suspended state, a resume packet is transferred to the electronic instrument PC2. The port P2 is set to a disabled state after the power for the data transfer control system has been turned on.

Abstract: Embodiments of apparatuses, systems, and methods are described for a machine-readable medium having instructions stored thereon, which, when executed by a machine, to cause the machine to generate a representation of an apparatus. The apparatus includes a bridge agent, a first interconnect, and a second interconnect. The bridge agent is configured by bridge control signals to control transmission of a communication between the first interconnect and the second interconnect. The representation may be a sequence of instructions written in a programming language to mimic in a computer simulation environment attributes derived from a projected fabricated hardware instance of the apparatus.

Abstract: In a situation where a host computer or storage system is an initiator and the storage system or another storage system is a target, when the initiator intends to check LUs in the target, if the initiator judges that the number of delay ACKs is set to more than one, it simultaneously issues the same number of check commands—SCSI Inquiry LUN#a and LUN#b—as the number of delayed ACKs, or check commands in multiples of the number of delayed ACK, to the target; and, when receiving check results—SCSI Data-In—in response to the check commands from the target, sends an acknowledgement to the target. Accordingly, when the number of delayed ACKs set in the TCP in the initiator is more than one, the initiator simultaneously issues check commands to the target designating the same number of LUs as the number of delayed ACKs, and the responses will not be influenced by the delayed ACK.

Abstract: In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.

Abstract: A system-on-chip (100) includes a 16-bit DSP (102), a 16-bit data bus (202) coupled to the DSP, at least one 32-bit-only peripheral (110), a 32-bit data bus (212) coupled to the peripheral, and a bridge (108), including a write merge system (200), coupled between the 16-bit and 32-bit buses. A method of the write merge system includes pre-storing addresses of peripherals in a memory map structure (220 and 221), receiving 16-bit data and a write transaction from the DSP for modifying sixteen bits of a 32-bit data location of the peripheral; reading 32-bit contents of the data location of the peripheral; multiplexing the received 16-bit data with the read 32-bit contents; and writing a new 32-bit word, including the modified sixteen bits and an unmodified sixteen bits, to the data location of the peripheral, without any intervention from the DSP subsequent to receiving the write transaction.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.