Crossbar Patents (Class 710/317)
  • Patent number: 10915482
    Abstract: Aligning received BDIs with received data on a cross-chip link including receiving, from the cross-chip link, a control flit comprising incoming data flit information for a plurality of incoming data flits; adding the incoming data flit information to a control structure; receiving, from the cross-chip link, the plurality of incoming data flits; directing each of the plurality of incoming data flits to virtual channel queues based on the incoming data flit information at a first read pointer in the control structure; receiving a bookend flit comprising a plurality of BDIs for the plurality of data flits; and associating each of the BDIs with the plurality of data flits based on the incoming data flit information at a second read pointer in the control structure.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: James F. Mikos
  • Patent number: 10831687
    Abstract: Aligning received BDIs with received data on a cross-chip link including receiving, from the cross-chip link, a control flit comprising incoming data flit information for a plurality of incoming data flits; adding the incoming data flit information to a control structure; receiving, from the cross-chip link, the plurality of incoming data flits; directing each of the plurality of incoming data flits to virtual channel queues based on the incoming data flit information at a first read pointer in the control structure; receiving a bookend flit comprising a plurality of BDIs for the plurality of data flits; and associating each of the BDIs with the plurality of data flits based on the incoming data flit information at a second read pointer in the control structure.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventor: James F. Mikos
  • Patent number: 10789667
    Abstract: In one embodiment, a method for 3D digital watermarking for a triangular mesh using one or more key parameters is disclosed including forming a Hamiltonian path of a desired length around a selected vertex in a selected direction of a spiral; marking the selected vertex a dead end if there is a deadlock and continuing the spiral; and applying a watermark by introducing points in a path order on edges of the spiral, wherein information is encoded at a partition of adjacent triangles at one or more of the points.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 29, 2020
    Assignee: TREATSTOCK INC.
    Inventors: Arsenii Kurin, Artem Arno
  • Patent number: 10754808
    Abstract: Bridge logic is provided to receive a request from a device, where the request references an address of a secondary address space. The secondary address space corresponds to a subset of addresses in a configuration address space of a system, and the secondary address space corresponds to a first view of the configuration address space. The bridge logic uses a mapping table to translate the address into a corresponding address in the configuration address space, where addresses of the configuration address space correspond to a different second view of the configuration address space.
    Type: Grant
    Filed: December 20, 2015
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Prashant Sethi, Michael T. Klinglesmith, David J. Harriman, Reuven Rozic, Shanthanand Kutuva Rabindrananth
  • Patent number: 10757038
    Abstract: Examples relate to switching devices comprising a switch controller and a plurality of interconnected sub-switches forming an internal network of the switching device. A packet is received at a first sub-switch of the plurality of interconnected sub-switches. The packet is to be routed to a particular external output port of a second sub-switch of the plurality of interconnected sub-switches. Upon reception of the packet, the switch controller reserves a space for the packet in a queue associated to the particular external output port. Then, the switch controller routes the packet on the internal network to the particular external output to occupy the reserved space for the packet.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: August 25, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Nicholas George McDonald, Darel Neal Emmot
  • Patent number: 10691602
    Abstract: To reduce overhead for cache coherence for shared cache in multi-processor systems, adaptive granularity allows tracking shared data at a coarse granularity and unshared data at fine granularity. Processes for adaptive granularity select how large of an entry is required to track the coherence of a block based on its state. Shared blocks are tracked in coarse-grained region entries that include a sharer tracking bit vector and a bit vector that indicates which blocks are likely to be present in the system, but do not identify the owner of the block. Modified/unshared data is tracked in fine-grained entries that permit ownership tracking and exact location and invalidation of cache. Large caches where the majority of blocks are shared and not modified create less overhead by being tracked in the less costly coarse-grained region entries.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Gino Chacon, Alaa R. Alameldeen
  • Patent number: 10606782
    Abstract: Aligning received BDIs with received data on a cross-chip link including receiving, from the cross-chip link, a control flit comprising incoming data flit information for a plurality of incoming data flits; adding the incoming data flit information to a control structure; receiving, from the cross-chip link, the plurality of incoming data flits; directing each of the plurality of incoming data flits to virtual channel queues based on the incoming data flit information at a first read pointer in the control structure; receiving a bookend flit comprising a plurality of BDIs for the plurality of data flits; and associating each of the BDIs with the plurality of data flits based on the incoming data flit information at a second read pointer in the control structure.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventor: James F. Mikos
  • Patent number: 10572173
    Abstract: Elastic cloud storage (ECS) systems typically divide storage nodes into geographic or topological zones and implement various concepts that enable the system to be extremely efficient in terms of capacity management. Architectures detailed herein can improve ECS and other similar systems in terms of inter-zone data transfers and remote data caching without violating core concepts of an ECS system that enable efficient capacity management.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: February 25, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Mikhail Danilov, Grigorii Skripko
  • Patent number: 10476492
    Abstract: Embodiments herein may present an integrated circuit including a switch, where the switch together with other switches forms a network of switches to perform a sequence of operations according to a structure of a collective tree. The switch includes a first number of input ports, a second number of output ports, a configurable crossbar to selectively couple the first number of input ports to the second number of output ports, and a computation engine coupled to the first number of input ports, the second number of output ports, and the crossbar. The computation engine of the switch performs an operation corresponding to an operation represented by a node of the collective tree. The switch further includes one or more registers to selectively configure the first number of input ports and the configurable crossbar. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Ankit More, Jason M. Howard, Robert Pawlowski, Fabrizio Petrini, Shaden Smith
  • Patent number: 10474611
    Abstract: Aligning received BDIs with received data on a cross-chip link including receiving, from the cross-chip link, a control flit comprising incoming data flit information for a plurality of incoming data flits; adding the incoming data flit information to a control structure; receiving, from the cross-chip link, the plurality of incoming data flits; directing each of the plurality of incoming data flits to virtual channel queues based on the incoming data flit information at a first read pointer in the control structure; receiving a bookend flit comprising a plurality of BDIs for the plurality of data flits; and associating each of the BDIs with the plurality of data flits based on the incoming data flit information at a second read pointer in the control structure.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: November 12, 2019
    Assignee: International Business Machines Corporation
    Inventor: James F. Mikos
  • Patent number: 10468544
    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: November 5, 2019
    Assignee: Rambus Inc.
    Inventors: Yohan Frans, Simon Li, Eric Linstadt, Jun Kim
  • Patent number: 10459723
    Abstract: Systems and methods relate to performing data movement operations using single instruction multiple data (SIMD) instructions. A first SIMD instruction comprises a first input data vector having a number N of two or more data elements in corresponding N SIMD lanes and a control vector having N control elements in the corresponding N SIMD lanes. A first multi-stage cube network is controllable by the first SIMD instruction, and includes movement elements, with one movement element per SIMD lane, per stage. A movement element selects between one of two data elements based on a corresponding control element and moves the data elements across the stages of the first multi-stage cube network by a zero distance or power-of-two distance between adjacent stages to generate a first output data vector. A second multi-stage cube network can be used in conjunction to generate all possible data movement operations of the input data vector.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: October 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Eric Wayne Mahurin
  • Patent number: 10461923
    Abstract: A multivariate signature method for resisting key recovery attack, which establishes a new signature verification condition by adding additional value of signature. The verification condition implies verification of internal information x and y, thereby effectively resisting key recovery attack generated by the existence of equivalence key. Specifically, the method includes the three stages of data preprocessing, signature generation and signature verification. The invention is a signature authentication method based on polynomial equations of a plurality of variables in a finite field, which can effectively resist the key recovery attack, provide the basic technical support for the information security and the establishment of the trust system in the quantum computer era, and provide a secure digital signature option in the quantum era.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: October 29, 2019
    Inventors: Xin Wang, Bo Yang, Jian Li, Hua Wu
  • Patent number: 10372380
    Abstract: A method includes retrieving a decode threshold number of encoded data slices, wherein codecs process, in an order, a data segment and the processed data segment is encoded into a set of encoded data slices. The method further includes decoding the decode threshold number of encoded data slices to recover the processed data segment. In a reversed order to the order, applying a first codec on the processed data segment to produce a first partially processed recovered data segment. When the first codec is a verifiable codec, the method further includes separating the first partially processed recovered data segment into an initial integrity value and a processed data segment. The method further includes calculating a new integrity value from the processed data segment. When the new integrity value substantially matches the initial integrity value, the method further includes indicating that the set of encoded data slices is authentic.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, Mark D. Seaborn
  • Patent number: 10289587
    Abstract: A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: May 14, 2019
    Assignee: Arm Limited
    Inventors: Ian David Andrews, Andrew David Tune, Daniel Adam Sara, George Robert Scott Lloyd
  • Patent number: 10261914
    Abstract: A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, and a controller configured to receive a data word to be stored at an address in the array and to store, at the address in the array, the data word and a location indicia corresponding to the address. The controller can be further configured to command the array to read the data word from the address, to receive response data from the array, and to verify that a location indicia of the response data corresponds to the address. If the location indicia of the response data does not correspond to the address, the controller can be further configured to indicate an error.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Alberto Troia
  • Patent number: 10261553
    Abstract: A Data Storage Device (DSD) enclosure includes a chassis and at least one backplane mounted in the chassis. According to one aspect, each backplane includes a row of DSD slots and a switch slot located in a middle portion of the row of DSD slots. A plurality of signal traces connect the DSD slots to the switch slot.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 16, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dean Mitcham Jenkins, Robert P. Ryan
  • Patent number: 10248591
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Patent number: 10191881
    Abstract: A method, a computing system, and a non-transitory machine readable storage medium containing instructions for managing a stream processing topology are provided. In an example, the method includes receiving a first topology that communicatively couples a plurality of processing elements via a first arrangement of interconnections to perform an operation on a stream of data. A second topology is defined that communicatively couples the plurality of processing elements via a second arrangement of interconnections that is different from the first arrangement. The second topology assigns the plurality of processing elements a first set of operations. The second topology is provided to a stream processing manager and is modified during processing of the stream of data by assigning a second set of operations to the plurality of processing elements that is different from the first set of operations.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: January 29, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Wei Xiang Goh
  • Patent number: 10152376
    Abstract: A method comprising: receiving an I/O request for object data; determining one or more data fragments wherein the object data is stored; determining that one or more of the data fragments are unavailable; determining, from within the one or more unavailable data fragments, a set of slices storing the object data, each slice comprising k small data fragments and m coded fragments; for each slice, retrieving at least k small data and coded fragments within the slice from storage; and recovering a segment of the object data using the retrieved small data and coded fragments. A related system and computer program product are also described.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: December 11, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Konstantin Buinov, Andrey Fomin, Andrey Kurilov, Maxim Trusov
  • Patent number: 10140238
    Abstract: An Open Compute Project (OCP) mezzanine riser with repurposed connectivity to allow for increased PCIe card count on a motherboard server. The OCP mezzanine riser includes at least one OCP connector, where the OCP connectors are mounted on the bottom of the mezzanine riser card and mate with at least one of three OCP connection points that are mounted on a server motherboard. Further, the OCP mezzanine riser includes one or more PCIe lanes mounted on the top of the mezzanine riser card, where a PCIe card may be connected to the one or more PCIe lanes of the mezzanine riser.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: November 27, 2018
    Assignee: Dell Products L.P.
    Inventors: Kevin Warren Mundt, Scott Michael Ramsey
  • Patent number: 10083114
    Abstract: A data storage device includes a storage medium including a plurality of memory units; and a controller suitable for performing a state determination operation to first memory units in order of a write sequence until a memory unit stored with an error-correction-failed data when a power supply is restored after an abnormal power-off, skipping the state determination operation to second memory units between the memory unit storing the error-correction-failed data and a pointed memory unit, performing the state determination operation to third memory units after the pointed memory unit in order of the write sequence, and performing a garbage collection operation to the first to third memory units based on a result of the state determination operation.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: September 25, 2018
    Assignee: SK Hynix Inc.
    Inventor: Sung Kwan Hong
  • Patent number: 10061695
    Abstract: Provided herein are a memory system and an operating method thereof. A method of operating a controller for controlling a memory block including a plurality of pages includes determining whether the memory block is in an open state or a closed state, if the memory block is in the open state, reading merged metadata included in the plurality of pages, and rebuilding logical to physical (L2P) mapping data of a plurality of logical pages included in each of the plurality of pages based on the merged metadata.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 28, 2018
    Assignee: SK Hynix Inc.
    Inventors: Beom Ju Shin, Dae Hong Kim
  • Patent number: 10042708
    Abstract: A method for execution by a dispersed storage and task (DST) execution unit includes receiving a request for rebuilding dispersed error encoded data slices and determining a rate for rebuilding the data slices. The method continues by the DST receiving one or more requests for dispersed error encoded data slices not associated with rebuilding and modifying the rate of processing for the one or more requests for dispersed error encoded data slices not associated with rebuilding dispersed error encoded data slices in accordance with the rate for rebuilding dispersed error encoded data slices. When the sending rebuilding dispersed error encoded data slices has concluded the method continues by reverting the rate of processing of requests for dispersed error encoded data slices to the previous rate.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 10042566
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. For example, the computing device generates and transmits a read request for a set of encoded data slices (EDSs) of a data object to primary storage units (SUs). The data object is stored within primary and secondary SUs. The computing device then receives at least the read threshold number of EDSs from the plurality of primary SUs. The primary SUs operate selectively to provide the at least the read threshold number of EDSs to the computing device either from memory of primary SU(s) or from secondary SU(s).
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventor: Jason K. Resch
  • Patent number: 9977750
    Abstract: A data processing system includes a network of interconnected switch points having a plurality of edge switch points located at an edge of the network; a plurality of network interface controllers, wherein each edge switch point of the plurality of edge points is coupled to a corresponding network interface controller of the plurality of network interface controllers; a plurality of target controllers; and a crossbar switch coupled between the plurality of network interface controllers and the plurality of target controllers. The crossbar switch is configured to communicate read/write signals between any one of the plurality of network interface controllers and any one of the plurality of target controllers.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 22, 2018
    Assignee: NXP USA, Inc.
    Inventors: Sanjay R. Deshpande, John E. Larson
  • Patent number: 9798901
    Abstract: A device securely accesses data in a memory via an addressing unit which provides a memory interface for interfacing to a memory, a core interface for interfacing to a core processor and a first and second security interface. The device includes a security processor HSM for performing at least one security operation on the data and a remapping unit MMAP. The remapping unit enables the security processor to be accessed by the core processor via the first security interface and to access the memory device via the second security interface according to a remapping structure for making accessible processed data based on memory data. The device provides a clear view on encrypted memory data without requiring system memory for storing the clear data.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: October 24, 2017
    Assignee: NXP USA, Inc.
    Inventors: Juergen Frank, Michael Staudenmaier, Manfred Thanner
  • Patent number: 9716669
    Abstract: A system may comprise a first group of switches, each switch including a first group of inputs and outputs, and a first group of controllers, each controller being independent from one another and corresponding to a switch of the first group of switches, to selectively control the switch to connect the switch's inputs with outputs. The first group of switches and controllers may be installed in a chassis. The system may comprise a second group of switches, each switch including a second group of inputs and outputs, and a second group of controllers, each controller corresponding to a switch of the second group of switches, to selectively control the switch to connect the switch's inputs with outputs. The second group of controllers may control and connect, via a group of control links, to the first group of controllers.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 25, 2017
    Assignee: Juniper Networks, Inc.
    Inventors: Sunil Mekad, Satish D. Deo
  • Patent number: 9715425
    Abstract: A method includes receiving a plurality of streams of data from a plurality of data sources. During a first time interval of receiving the streams of data, the method further includes dividing each of the plurality of streams into a first time-aligned data segment to produce a set of first time-aligned data segments. The method further includes generating a first data matrix from data blocks of the set of first time-aligned data segments. The method further includes encoding the first data matrix using an encoding matrix to produce a first coded matrix. The method further includes slicing the first coded matrix into a first set of encoded data slices based on the first orientation. The method further includes outputting a first set of encoded data slices of the first coded matrix.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 9674071
    Abstract: A method for generating a high-precision packet train includes configuring an initial packet generation flow of duration T in a network node and sending a packet to a loopback port to initiate the initial packet generation flow in the network node, where the loopback port loops packets back to the network node or recirculates packets within the network node, and where the loopback port is configured for traffic shaping that establishes a pre-determined inter-packet gap for packets output by the loopback port. The method further includes configuring a main packet generation flow having a duration t1 that commences on expiration of the duration T. Looped back packets in the network node are sent to the loopback port for the entirety of durations T and t1, while one copy of each looped back packet in the network node is sent to a network port during the duration t1.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: June 6, 2017
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Prashant Anand, Vinayak Joshi, Vivek Srivastava
  • Patent number: 9632862
    Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.
    Type: Grant
    Filed: December 20, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Brian S. Morris, Bill Nale, Robert G. Blankenship, Eric L. Hendrickson
  • Patent number: 9569591
    Abstract: Configurable user interface systems for a patient support structure are disclosed. As described a control interface comprises the capability to allow limited impact on processes deemed important when other applications and programs are run. The configurable user interface systems described herein allow for customized display of information and display options available to a user in various environments.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: February 14, 2017
    Assignee: Hill-Rom Services, Inc.
    Inventor: Irvin J. Vanderpohl, III
  • Patent number: 9515204
    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 6, 2016
    Assignee: Rambus Inc.
    Inventors: Yohan Frans, Simon Li, Eric Lindstadt, Jun Kim
  • Patent number: 9424215
    Abstract: In a virtualized desktop system an interfacing module is coupled to peripheral ports of a target device. The interfacing module is connected to a network. A digital user station is connected to the network. The digital user station is configured to be coupled to peripherals. The interfacing module and digital user station use respective hardware engines to communicate via said network.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: August 23, 2016
    Assignee: Avocent Huntsville Corporation
    Inventors: John Hickey, Ken Power, Martin McDonell, Paul Hough, Vincent Carr, Tom Gibbs, John Browne, Aidan Quinn, Iain Campbell, Mark Leyden
  • Patent number: 9335934
    Abstract: Disclosed herein are a shared memory controller and a method of controlling a shared memory. An embodiment method of controlling a shared memory includes concurrently scanning-in a plurality of read/write commands for respective transactions. Each of the plurality of read/write commands includes respective addresses and respective priorities. Additionally, each of the respective transactions is divisible into at least one beat and at least one of the respective transactions is divisible into multiple beats. The method also includes dividing the plurality of read/write commands into respective beat-level read/write commands and concurrently arbitrating the respective beat-level read/write commands according to the respective addresses and the respective priorities. Concurrently arbitrating yields respective sequences of beat-level read/write commands corresponding to the respective addresses.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: May 10, 2016
    Assignee: Futurewei Technologies, Inc.
    Inventors: Hao Luan, Alan Gatherer, Yan Bei, Jun Ying
  • Patent number: 9286959
    Abstract: A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled to the bank of a non-volatile memory array, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets. Moreover, the memory comprises banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Alexandre P. Ferreira, Jente B. Kuang, Janani Mukundan, Karthick Rajamani
  • Patent number: 9286257
    Abstract: Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: March 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Gerard Hofmann, Jaya Prakash Subramaniam Ganasan, Brandon Wayne Lewis
  • Patent number: 9286256
    Abstract: The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the client subsystems. Similarly, data associated with write data requests is transmitted from the client subsystems to the cache memory. To allow for the transmission of both read and write data on the crossbar unit, an arbiter is configured to schedule the crossbar unit transmissions as well and arbitrate between data requests received from the client subsystems.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: March 15, 2016
    Assignee: NVIDIA Corporation
    Inventors: Alexander L. Minkin, Steven J. Heinrich, Rajeshwaran Selvanesan, Stewart Glenn Carlton, John R. Nickolls
  • Patent number: 9201828
    Abstract: The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 1, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Kaushal Sanghai, Boris Lerner, Michael G. Perkins, John L. Redford
  • Patent number: 9137005
    Abstract: Systems and methods presented herein provide for the management of link rates for connecting targets devices (e.g., storage devices) to initiators (e.g., host systems). In one embodiment, an expander includes a plurality of PHYs including a PHY having a first link rate and a PHY having a second link rate that is different than the first link rate. The expander also includes a link manager communicatively coupled to the PHYs and operable to process a connection request from an initiator for the first link rate, extract a timer from the connection request, and determine whether the first link rate is available. The link manager is also operable to start the timer when the link manager determines that the first link rate is unavailable and issue a response to the initiator to inform the initiator that the timer has started and that connection at the first link rate is delayed.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: September 15, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte Ltd
    Inventors: Jeffrey C. Weide, Reid A. Kaufmann, Charles D. Henry
  • Patent number: 9104483
    Abstract: The invention pertains to a system and method for a set of middleware components for supporting the execution of computational applications on high-performance computing platform. A specific embodiment of this invention was used to deploy a financial risk application on Blue Gene/L parallel supercomputer. The invention is relevant to any application where the input and output data are stored in external sources, such as SQL databases, where the automatic pre-staging and post-staging of the data between the external data sources and the computational platform is desirable. This middleware provides a number of core features to support these applications including for example, an automated data extraction and staging gateway, a standardized high-level job specification schema, a well-defined web services (SOAP) API for interoperability with other applications, and a secure HTML/JSP web-based interface suitable for non-expert and non-privileged users.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ramesh Natarajan, Thomas Phan, Satoki Mitsumori
  • Patent number: 9098641
    Abstract: A configurable bus includes a plurality of bus segments. The configurable bus also includes two or more pluralities of input/output (I/O) ports. Each bus segment is coupled to at least one of the pluralities of I/O ports. Also coupled to the bus segments is a cross-couple unit that is configurable to selectively couple any of the bus segments together.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: August 4, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Harold Kutz, Warren S. Snyder, Timothy J. Williams, Eashwar Thiagarajan
  • Patent number: 9052840
    Abstract: An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Anand Haridass, Diyanesh B. Vidyapoornachary, Robert B. Tremaine
  • Patent number: 9047057
    Abstract: An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Anand Haridass, Diyanesh B. Vidyapoornachary, Robert B. Tremaine
  • Patent number: 9013177
    Abstract: A programmable analog filter includes a crossbar array with a number of junction elements and a filter circuit being implemented within the crossbar array. At least a portion of the junction elements form reprogrammable components within the filter circuit. A method for using a programmable analog filter is also provided.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: April 21, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: John Paul Strachan, Philip J. Kuekes, Gilberto Medeiros Ribeiro
  • Patent number: 8984206
    Abstract: Techniques are disclosed to implement a scheduling scheme for a crossbar scheduler that provides distributed request-grant-accept arbitration between input group arbiters and output group arbiters in a distributed switch. Input and output ports are grouped and assigned a respective arbiter. The input group arbiters communicate requests indicating a count of respective ports having data packets to be transmitted via one of the output ports. The output group arbiter attempts to accommodate the requests for each member of an input group before proceeding to a next input group.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Chrysos, Girish Gopala Kurup, Cyriel J. Minkenberg, Anil Pothireddy, Vibhor K. Srivastava, Brian T. Vanderpool
  • Publication number: 20150067229
    Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Inventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
  • Patent number: 8959276
    Abstract: Exemplary embodiments of the present invention disclose a method and system for executing data permute and data shift instructions. In a step, an exemplary embodiment encodes a control index value using the recoding logic into a 1-hot-of-n control for at least one of a plurality of datum positions in the one or more target registers. In another step, an exemplary embodiment conditions the 1-hot-of-n control by a gate-free logic configured for at least one of the plurality of datum positions in the one or more target registers for each of the data permute instructions and the at least one data shift instruction. In another step, an exemplary embodiment selects the 1-hot-of-n control or the conditioned 1-hot-of-n control based on a current instruction mode. In another step, an exemplary embodiment transforms the selected 1-hot-of-n control into a format applicable for the crossbar switch.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Markus Kaltenbach, Jens Leenstra, Philipp Panitz, Christoph Wandel
  • Patent number: 8959269
    Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: February 17, 2015
    Assignee: Synopsys, Inc.
    Inventor: David Latta
  • Patent number: 8959275
    Abstract: Exemplary embodiments of the present invention disclose a method and system for executing data permute and data shift instructions. In a step, an exemplary embodiment encodes a control index value using the recoding logic into a 1-hot-of-n control for at least one of a plurality of datum positions in the one or more target registers. In another step, an exemplary embodiment conditions the 1-hot-of-n control by a gate-free logic configured for at least one of the plurality of datum positions in the one or more target registers for each of the data permute instructions and the at least one data shift instruction. In another step, an exemplary embodiment selects the 1-hot-of-n control or the conditioned 1-hot-of-n control based on a current instruction mode. In another step, an exemplary embodiment transforms the selected 1-hot-of-n control into a format applicable for the crossbar switch.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Markus Kaltenbach, Jens Leenstra, Philipp Panitz, Christoph Wandel