Abstract: Techniques are generally described related to a multi-channel storage system. One example multi-channel storage system may include a plurality of memory-controllers, each memory-controller configured to control one or more storage units. The multi-channel storage system may further include a multi-channel interface having a plurality of input-output (IO) channels; and a channel-controller switch configured to support data communications between any one of the plurality of IO channels and any one of the plurality of memory-controllers. Upon receiving a request instructing using at least two of the plurality of IO channels and at least two of the plurality of memory-controllers, the multi-channel interface of the multi-channel storage system is configured to utilize the channel-controller switch to concurrently transfer data via the at least two of the plurality of IO channels or the at least two of the plurality of memory-controllers.

Abstract: In order to provide an inexpensive way to share an I/O device loaded in an I/O drawer among a plurality of blades, in a server system including a plurality of servers, a PCI device, and a manager for initializing a PCI switch, the PCI device has a plurality of virtual functions (VFs). The PCI switch, which has VF allocation information which indicates association between the servers and the VFs, is configured to: receive a transaction from one of the servers or from the PCI device; when the received transaction is a transaction sent from the one of the servers, remove a server identifier with which a sender server is identified and transfer the received transaction to the PCI device; and when the received transaction is a transaction sent from the PCI device, attach a server identifier that is determined based on the VF allocation information.

Abstract: Techniques are disclosed to implement a scheduling scheme for a crossbar scheduler that provides distributed request-grant-accept arbitration between input group arbiters and output group arbiters in a distributed switch. Input and output ports are grouped and assigned a respective arbiter. The input group arbiters communicate requests indicating a count of respective ports having data packets to be transmitted via one of the output ports. The output group arbiter attempts to accommodate the requests for each member of an input group before proceeding to a next input group.

Abstract: The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network.

Abstract: Exemplary embodiments of the present invention disclose a method and system for executing data permute and data shift instructions. In a step, an exemplary embodiment encodes a control index value using the recoding logic into a 1-hot-of-n control for at least one of a plurality of datum positions in the one or more target registers. In another step, an exemplary embodiment conditions the 1-hot-of-n control by a gate-free logic configured for at least one of the plurality of datum positions in the one or more target registers for each of the data permute instructions and the at least one data shift instruction. In another step, an exemplary embodiment selects the 1-hot-of-n control or the conditioned 1-hot-of-n control based on a current instruction mode. In another step, an exemplary embodiment transforms the selected 1-hot-of-n control into a format applicable for the crossbar switch.

Abstract: A crosspoint selector switch for simultaneously supporting multiple data formats having different switch reconfiguration timing requirements, comprising; a configurable switch section for selectively connecting outputs thereof to receive data from respective inputs thereof in response to operational switch data; and a configuration section operatively connected to provide the operational switch data to the switch section, the configuration section storing switch configuration data supporting multiple different configurations of the switch section, the configuration section being operative to receive different operational update commands each associated with a different configuration for the switch section and update the operational switch data from the stored switch configuration data to reconfigure the switch section in dependence on which of the different operational update commands is received.

Abstract: A network device includes a hybrid switch fabric configured for switching packets and circuits that includes a packet switching portion that distributes packets across a plurality of packet ports of fabric chips within the hybrid switch fabric and operates in accordance with packet switching behavior requirements, and a circuit switching portion for switching circuits, wherein the circuit switching portion of the hybrid switch fabric directly connects a single input of the hybrid switch fabric to a single output of the hybrid switch fabric via a pre-determined path through the fabric chips and operates in accordance with circuit switching behavior requirements. The packet switching portion and the circuit switching portion include one or more fabric chips, wherein the fabric chips each include a plurality of ports each dynamically configurable as one of a packet port for receiving and outputting packet-switched data and a circuit port for receiving and outputting circuit-switched data.

Abstract: A system-on-a-chip (SOC) bridge is described that applies an adapted delay, or latency, to data transfers across the bridge to avoid data corruption without reducing data transfer performance. The adapted delay assures that a source SOC service device transferring data to a destination SOC service device via the bridge and an SOC crossbar bus does not prematurely assume that the data transfer is complete upon transferring the data to the bridge. The bridge causes wait states to be inserted into the transfer between the source SOC service device and the SOC bridge until the SOC bridge receives confirmation that the data has arrived at the destination SOC service device. The adapted delay assures that subsequent operations are not prematurely initiated by the source SOC service device and/or the SOC CPU that may interfere with the data transfer from the SOC bridge to the destination SOC service device, causing corrupted data.

Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

Abstract: An access system includes line cards. The line cards include first and second line cards. The first line card receives a first packet and includes a first interface control module that generates a first request signal to transfer the first packet. The first request signal includes an identifier of a second interface control module in the second line card. Crossbar modules are separate from the line cards and include first and second crossbar modules. The first crossbar module includes a first scheduler module. The second crossbar module transfers packets between a pair of the line cards. The packets include the first packet. The first scheduler module is separate from the line cards and, based on the first request signal, schedules the transfer of the packets from the first interface control module, through the second crossbar module, and to the second interface control module.

Abstract: A parallel computer system includes a plurality of processors including a first processor and a plurality of second processors; and a crossbar switch provided with a plurality of ports; wherein the first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, and the first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors.

Abstract: Reconfigurable crossbar networks, and devices, systems and methods, including hardware in the form of logic (e.g. application specific integrated circuits (ASICS)), and software in the form of machine readable instructions stored on machine readable media (e.g., flash, non-volatile memory, etc.), which implement the same, are provided. An example of a reconfigurable crossbar network includes a crossbar. A plurality of endpoints is coupled to the crossbar. The plurality of endpoints is grouped into regions at design time of the crossbar network. A plurality of regional interconnects are provided. Each regional interconnect connects a group of endpoints within a given region.

Abstract: Described herein is a detachable multi-host computing system (100) having multiple host processors running different operating systems. In one implementation, the multi-host computing system (100) includes a detachable unit (102) and a base unit (104). Each of the detachable unit (102) and the base unit (104) includes an MR-IOV switch and a MR-PCIM for controlling the MR-IOV switch. In one embodiment, the MR-PCIM for both the detachable unit (102) and the base unit (104) is configured such that a single MR-PCIM switch may be used for enumerating peripheral devices connected to the detachable unit (102) and the base unit (104) when the detachable unit (102) and the base unit (104) are in an attached mode.

Abstract: According to an aspect of an embodiment, a server system includes a service processor, a plurality of system boards and a plurality of crossbar boards connecting the system boards. The service processor includes a first notifier that notifies each of the crossbar boards of a crossbar board subjected to maintenance. The crossbar boards each include a first transmitter that, when notified by the service processor that the crossbar board subjected to maintenance is another crossbar board, generates a suspension packet for suspending packet transmission to the another crossbar board and transmits the suspension packet to each of the system boards. The system boards each include a suspender that, when receiving the suspension packet from the crossbar board, suspends packet transmission to the crossbar board subjected to maintenance.

Abstract: A television includes at least two ports (e.g. HDMI ports). The television polls the ports before presenting a user interface that displays some or all of the ports and before toggling between any two of the ports. The polling ascertains whether a device is connected to each of the ports and whether the device is powered. The television modifies the display and/or toggling based on the current state of each port. For example, in toggling, ports that are not connected and ports that are connected to inactive devices are skipped. In another example, when displaying a list of ports, only those ports that are connected to devices appear in the list.

Abstract: An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is op

Abstract: A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid.

Abstract: Described is a data switching device comprising a plurality of input ports, a plurality of output ports, a plurality of first conductive connectors, a plurality of second conductive connectors, a plurality of crosspoint regions, and a memory device at each crosspoint region. The first conductive connectors are in communication with the input ports. The second conductive connectors are in communication with the output ports. Each crosspoint region includes a first conductive connector and a second conductive connector. The memory device is coupled between the first conductive connector and the second conductive connector for exchanging data between the input ports and the output ports.

Abstract: Integrated circuit devices are disclosed with receive ports having mapping circuits automatically configurable to change a logical mapping of data received on receive-data connections. Automatic configuration can be based on a data value included within a received data set. Corresponding systems and methods are also described.

Abstract: The invention is directed to a switching device (Sij) adapted to connects parts of a computer interconnection network, having N input ports (Ia-Ih) and N output ports (Oa-Oh), the device adapted for routing data packets by means of direct crosspoints (CPxy), the direct crosspoints configured for enabling direct connectivity between each of the N input ports to a subset m<N of the output ports only, in accordance with connectivity needs of the computer interconnection network. Preferably, it furelm.) they comprises an additional circuitry (L) and additional crosspoints (APx,L, APL,y) configured such that at least some of the input ports of the switching device can be indirectly connected to at least some of the output ports of the switching device, through the additional circuitry. The invention further concerns an interconnection network and a method for routing data.

Abstract: A data transfer controlling apparatus includes a first controlling unit that performs a broadcast transfer to a plurality of nodes connected to a first route switching device, and requests a second node representing nodes connected to a second route switching device that is connected to the first route switching device to perform a broadcast transfer when the first controlling unit receives a request of the broadcast transfer from a first node connected to the first route switching device, and a second controlling unit that performs the broadcast transfer to all of nodes connected to the first route switching device when the second controlling unit receives a request of a broadcast transfer from the second node.

Abstract: A network system includes a crossbar switch, and a plurality of crossbar interfaces having ports connected to the crossbar switch. A bypass route directly connects crossbar interfaces forming a group in which a frequency of use of the ports is greater than or equal to a predetermined value amongst the plurality of crossbar interfaces.

Abstract: An integrated circuit (IC) having an on-die data network is disclosed. The IC includes a first bus and second buses configured to convey signals in first and second directions, respectively, along a first axis. The second direction is opposite the first. The IC further includes third and fourth buses configured to convey signals in third and fourth directions, respectively, along a second axis perpendicular to the first axis. The fourth direction is opposite the third. Each bus is N-bits wide and unidirectional. Signal lines of two different buses having equal bit significance and opposite direction are arranged adjacent to one another. A crossbar unit having N crossbar switching circuits is configured to couple signal lines of a selected one of the buses to a corresponding signal line of another selected one of the buses. The signal lines of the buses are implemented on different metal layers than the crossbar switching circuits.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: An automatic addressing bus system and method of communication comprising a main and an end device, wherein the respective bus controllers used in the main and end devices comprise multi-master capability. The main controlling device has an address known to the end device to be connected, the end device is able to actively initiate the address allocation procedure, without the need for user interaction. The method and system of the present system may be implemented using such known bus systems such as 2-wire serial buses, in particular I2C, and enables both automatic and dynamic address allocation.

Abstract: The invention provides hardware based techniques for switching processing tasks of software programs for execution on a multi-core processor. Invented techniques involve a hardware logic based controller for assigning, adaptive to program processing loads, tasks for processing by cores of a multi-core fabric as well as configuring a set of multiplexers to appropriately interconnect cores of the fabric and program task specific segments at fabric memories, to arrange efficient inter-task communication as well as transferring of activating and de-activating task memory images among the multi-core fabric. The invention thereby provides an efficient, hardware-automated runtime operating system for multi-core processors, minimizing any need to use processing capacity of the cores for traditional operating system software functions.

Abstract: A data processing apparatus includes a plurality of computation devices connected to each other by a communication path. Each of the computation devices includes: a switching section provided to each of terminals and switchable between an upper layer use state in which communication is performed by a communication section between a given terminal of a plurality of terminals and a corresponding internal path and there is no connection performed by a bypass section between a corresponding pair of the plurality of the terminals, and an upper layer non-use state in which communication is not performed by a communication section between the given terminal of the plurality of the terminals and the corresponding internal path and connection is performed by the bypass section between the corresponding pair of the plurality of the terminals.

Abstract: Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme.

Abstract: A system and method are disclosed to prevent a reduction in the number of I/O devices which can be connected when building a PCIe topology by connecting I/O devices to a computer via a PCIe switch. A switch with which a computer and I/O devices are connected includes: a first PCI-PCI bridge which is positioned on the computer side; a second PCI-PCI bridge which is positioned on the I/O device side; trapper units which trap packet data which is inputted into the switch; a packet routing unit which transfers packet data to the I/O devices; and a management processor which is connected to the trapper units and provides the computer a virtual PCI-PCI bridge and a virtual link by execution of a program. The trapper units adjudicate the destination of the packet data which is transferred from the computer.

Abstract: The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit.

Abstract: A processing system on an integrated circuit includes a group of processing cores. A group of dedicated random access memories are severally coupled to one of the group of processing cores or shared among the group. A star bus couples the group of processing cores and random access memories. Additional layer(s) of star bus may couple many such clusters to each other and to an off-chip environment.

Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.

Abstract: In a method for controlling a data exchange between at least one set of data sinks and at least one set of data sources in circuit configurations and circuit sequences, which circuit configurations have at least one arbitration unit, the arbitration unit selects a first data sink (data sink arbitration) and a first data source (data source arbitration) according to a predefined sequence, and outputs an address of a first data source and a request signal and an address of a first data sink and a validity signal. Data of the first data source are stored in the first data sink.

Abstract: A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

Abstract: A system on a chip (SOC) includes a physical interface having first and second sets of interface pads. Interface pads from the first set are interleaved with interface pads from the second set. Additionally, the SOC is arranged for operation with a superset die having first and second personalities and has a physical interface with interface pads. The SOC uses a first number of interface pads in the first personality and a second number of interface pads in the second personality, where the first number is greater than the second number. A switch switches signals between the superset die and the physical interface and, in the second personality, switches signals to the physical interface so that interface pads in the second number of interface pads are interleaved with interface pads not in use in the second personality.

Abstract: In aspects of serial interface for FPGA prototyping, an advanced crossbar interconnect (AXI) bridge structure enables serial data communication between field programmable gate arrays (FPGA) in a system-on-chip (SoC). The AXI bridge structure includes a parallel interface configured to receive AXI data signals from an AXI component implemented at a first FPGA. A transmit (TX) engine is configured to packetize the AXI data signals into an AXI data packet, and transmit the AXI data packet to a second FPGA via a serial link. The AXI bridge structure also includes a receive (RX) engine configured to receive an additional AXI data packet from the second FPGA via the serial link, and extract AXI data signals from the additional AXI data packet. The parallel interface is further configured to provide the additional AXI data signals to the AXI component.

Abstract: A computer for charging an electronic device includes a computer, a power supply module, a motherboard and a USB interface module. The power supply module outputs electrical power when the computer is powered down. The USB interface module includes a USB interface and a switch. The USB interface is connected to the power supply and the motherboard and capable of charging the electronic device. The switch is set between the USB interface and the motherboard and controls a communication between the motherboard and the electronic device.

Abstract: An apparatus and method for scheduling within a switch is described. A set of input signals is received from input ports. The set of input signals is associated with a set of packets at the input ports. A request for each packet from the set of packets is generated based on the set of input signals. Each request has an input-port indicator, an output-port indicator and a service-level indicator. The packets are scheduled based on the service-level indicator.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Abstract: A connection expansion device connected to devices includes a plurality of ports to which devices are connected, a storage unit configured to record device information obtained from each port, and a processing unit configured to specify, based on the device information, a port in which an abnormal device exists, invalidate device information belonging to the port, and cause the storage unit to hold device information of a normal device.

Abstract: According to an aspect of the embodiment, a system control apparatus includes a control signal transmitting unit which transmits a control signal to control circuits via first signal line. The control signal includes a command for performing a control setting on other control circuits other than own control circuit or to all control circuits. Each control circuit includes a signal receiving unit which receives the control signal transmitted from the control signal transmitting unit via the first signal line, a signal transfer unit which transfers the command included in the received control signal via second signal lines to the control circuit, and a control setting unit which performs the control setting on the own control circuit according to the command included in the received control signal or a command transferred from the other control circuits other than the own control circuit.

Abstract: An embodiment of a multichip module is disclosed. For this embodiment of the multichip module, a transceiver die has transceivers. A crossbar switch die has at least one crossbar switch. A protocol logic blocks die has protocol logic blocks. The transceiver die, the crossbar switch die, and the protocol logic blocks die are all coupled to an interposer. The interposer interconnects the transceivers and the protocol logic blocks to one another and interconnects the protocol logic blocks and the at least one crossbar switch to one another.

Abstract: An interconnection network with m first electronic circuits and n second electronic circuits, comprising m interconnection sub-networks, each interconnection sub-network including: at least one addressing bus and one information transfer bus connecting one of the m first circuits to all the n second circuits, the information transfer bus comprising a plurality of portions of signal transmission lines connected to each other through signal repeater devices, and a controller device that controls the signal repeater devices, at least one of the signal repeater devices is controlled to be active depending on a value of an addressing signal to be sent to the addressing bus by said one of the m first circuits to the controller device, where m and n are integer numbers greater than 1.

Abstract: A programmable controlled computer switch is disclosed. Console devices and universal serial bus devices of the computer switch can be switched as having a controlling function or a hub function. The computer switch includes a console port interface having console ports for connecting console devices, which initially have a controlling function; a universal serial bus hub port interface having hub ports for connecting universal serial bus devices, which initially have a hub function; plural computer interfaces having a computer port respectively for connecting a computer device; a matrix switching circuit connected to the console port interface, the universal serial bus hub port interface and the plural computer interfaces; and a main controlling circuit connected between the matrix switching circuit and the plural computer interfaces.

Abstract: A programmable channel circuit can include a control circuit having at least one bidirectional I/O terminal, at least one programming terminal, and one or more processing elements, and an interface circuit having first and second field terminals. The interface circuit is coupled to the control circuit via the processing elements. The control circuit can be operable to respond to a programming signal on the programming terminal for automatically selecting one of a plurality of communications modes. The selection couples the bidirectional I/O terminal to the first terminal via one of the processing elements associated with the selected communications mode.

Abstract: According to an aspect of the embodiment, an input/output device transmits a message to a first node controller of a parent node which is set in advance via a cross bar. At this point, the cross bar generates information based on node information of the input/output device, and adds the generated information to the message. The first node controller transmits, via the cross bar, the message to a second node controller of a parent node corresponding to an input/output device that is to receive the message. The second node controller transmits, via the cross bar, the message to an input/output device that is to receive the message. At this point, the cross bar transmits the message restored by deleting the generated information from the message to the input/output device which is set as a destination.

Abstract: Embodiments include a system and method for an interrupt controller that propagates interrupts to a subsystem in a system-on-a-chip (SOC). Interrupts are provided to an interrupt controller that controls access of interrupts to a particular subsystem in the SOC that includes multiple subsystems. Each subsystem in the SOC generates multiple interrupts to other subsystems in the SOC. The interrupt controller processes multiple interrupts and generates an interrupt output. The interrupt output is then transmitted to a particular subsystem.

Abstract: The disclosure is directed at a fibre adapter for use with small form factor pluggable (SFP) devices comprising a set of cages for receiving the SFP devices and a switch for interconnecting inputs and outputs of the set of cages.

Abstract: A data bus line control circuit prevents a problem of a data access operation on a global data bus (GDB) line although two blocks are simultaneously selected. The data bus line control circuit includes: a global data bus line which is arranged between memory units adjacent to each other as two pairs, and transmits a data from a local data bus line positioned between adjacent sub blocks; and transmission means which is connected between the local data bus line and the global data bus line, and transmits bit line signals of two sub blocks to one pair of global data bus lines different from each other through the local data bus line, when the two sub blocks are simultaneously selected by a block isolation selection signal. As a result, a circuit arrangement and a layout design become simplified, and two operations of 8K refresh and 4K refresh are possible in one chip, therefore, two kinds of effects can be achieved by one chip.