Access Request Queuing Patents (Class 710/39)
  • Patent number: 10423568
    Abstract: A method and system for transferring NVMe data over a network comprises using a discrete buffer memory device to generate a write command from an NVMe-over-RDMA write command request, store the user data from a client host of the network, and send an interrupt signal to a NVMe storage device of the network. The NVMe storage device retrieves the write command from the discrete buffer memory device and performs a direct memory access transfer of the stored user data from the discrete buffer memory device to the NVMe storage device. The discrete buffer memory device comprises a controller and a random access memory for generating commands and storing the commands in a submission queue of the random access memory. The controller can clear commands from the submission queue based on completion commands received in a completion queue of the random access memory.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: September 24, 2019
    Assignee: Microsemi Solutions (U.S.), Inc.
    Inventors: Oren Berman, Stephen Bates
  • Patent number: 10379770
    Abstract: A storage system according to the present invention includes: a plurality of storage devices, wherein each of a plurality of the storage devices including: a control unit; and a storage unit that stores data, wherein the control unit of the storage device that receives a request specifies the storage device that includes the storage unit in that target data targeted by the request is stored among a plurality of the storage devices, and the control unit of the storage device that is specified transmits, as a response to the request, the target data and header information in that a destination identifier indicating a destination of the request is set to a source identifier of the response, and a source identifier indicating a source of the request is set to a destination identifier of the response.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: August 13, 2019
    Assignee: NEC CORPORATION
    Inventor: Yuko Chinone
  • Patent number: 10379595
    Abstract: In various embodiments and/or usage scenarios, device power control, such as relating to one or more power control commands, requests to transition operation to a specific power mode, and/or device power management commands, is advantageous and improves one or more of: performance, reliability, unit cost, and development cost of one or more devices, such as storage devices (e.g. a Solid-State Disk (SSD)) or systems including same.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 13, 2019
    Assignee: Seagate Technology LLC
    Inventor: Ross John Stenfort
  • Patent number: 10372378
    Abstract: Technology is described herein for operating non-volatile storage. In one aspect, a memory controller replaces an original data buffer pointer(s) to a host memory data buffer(s) with a replacement data buffer pointer(s) to a different data buffer(s) in the host memory. The original data buffer pointer(s) may be associated with a specific read command. For example, the original data buffer pointer(s) may point to data buffer(s) to which data for some range of logical addresses (which may be read from the non-volatile storage) is to be transferred by a memory controller of the non-volatile storage. The replacement data buffer pointer(s) could be associated with a different read command. However, it is not required for the replacement data buffer pointer(s) to be associated with a read command. The replacement data buffer pointer(s) may point to a region of memory that is allocated for exclusive use of the memory controller.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: August 6, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Judah Gamliel Hahn, Alon Marcu, Ariel Navon, Alexander Bazarsky
  • Patent number: 10289516
    Abstract: A processor core includes a decode circuit to decode an instruction, where the instruction specifies an address to be monitored. The processor core further includes a monitor circuit, where the monitor circuit includes a data structure to store a plurality of entries for addresses that are being monitored by the monitor circuit and a triggered queue, where the monitor circuit is to enqueue an address being monitored by the monitor circuit into the triggered queue in response to a determination that a triggering event for the address being monitored by the monitor circuit occurred. The processor core further includes an execution circuit to execute the decoded instruction to add an entry for the specified address to be monitored into the data structure and ensure, using a cache coherence protocol, that a coherency status of a cache line corresponding to the specified address to be monitored is in a shared state.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: May 14, 2019
    Assignee: INTEL CORPORATION
    Inventors: Wim Heirman, Yves Vandriessche
  • Patent number: 10270713
    Abstract: A system for communicating a multi-destination packet through a network switch fabric with a plurality of input and output ports is described. This system receives the multi-destination packet at an input port, wherein the multi-destination packet includes a multicast packet or a broadcast packet that is directed to multiple output ports, and wherein the network switch fabric maintains a separate virtual output queue (VOQ) for each output port. Next, the system sends the multi-destination packet from the input port to the multiple output ports by inserting the multi-destination packet into VOQs associated with the multiple output ports. The multi-destination packet is inserted into one VOQ at a time, so that after the multi-destination packet is read out of a VOQ and is sent to a corresponding output port, the multi-destination packet is inserted in another VOQ until the multi-destination packet is sent to all of the multiple output ports.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 23, 2019
    Assignee: Oracle International Corporation
    Inventors: Arvind Srinivasan, Shimon Muller
  • Patent number: 10228873
    Abstract: A method for swapping out tape cartridges in tape libraries is disclosed. In one embodiment, such a method includes maintaining, in a tape library, old tape cartridges backing up data in a primary storage system. The method adds, to the tape library, new tape cartridges to replace the old tape cartridges. The method then initiates a data transfer process to move active data to the new tape cartridges. This data transfer process first moves active data in less frequently accessed storage elements, followed by active data in more frequently accessed storage elements. During the data transfer process, the method backs up updates to data in the primary storage system to the new tape cartridges. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joshua J. Crawford, Paul A. Jennas, II, Jason L. Peipelman, Matthew J. Ward
  • Patent number: 10223032
    Abstract: A memory controller is provided for accessing shared memory objects by read and write requests made to a memory. The memory controller includes a list for registering address locations of the shared objects in the memory, and having slots for a lock bit. The memory controller includes a read wait queue and a write wait queue for selectively inputting, outputting, holding, and purging requests. The memory controller includes a read initiated queue and a write initiated queue for selectively inputting and purging requests transferred from the read wait queue and the write wait queue, respectively, upon memory access initiation and completion. The memory controller includes a controller for controlling the wait queues using policies by determining which requests to output, hold, and purge, based on a list entry, a lock bit and TTL information set to each request upon a hold being applied thereto and decremented in each cycle.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventor: Yasunao Katayama
  • Patent number: 10209925
    Abstract: A memory controller is provided for accessing shared memory objects by read and write requests made to a memory. The memory controller includes a list for registering address locations of the shared objects in the memory, and having slots for a lock bit. The memory controller includes a read wait queue and a write wait queue for selectively inputting, outputting, holding, and purging requests. The memory controller includes a read initiated queue and a write initiated queue for selectively inputting and purging requests transferred from the read wait queue and the write wait queue, respectively, upon memory access initiation and completion. The memory controller includes a controller for controlling the wait queues using policies by determining which requests to output, hold, and purge, based on a list entry, a lock bit and TTL information set to each request upon a hold being applied thereto and decremented in each cycle.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventor: Yasunao Katayama
  • Patent number: 10204047
    Abstract: An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Israel Diamand, Nir Misgav, Aravindh Anantaraman, Zvika Greenfield
  • Patent number: 10175897
    Abstract: A data server, method and computer readable storage medium for receiving a current request relating to a data archive, determining a number of queued requests relating to the data archive present in a request queue, determining a waiting time for the current request based on the number of queued requests and adding the current request to the request queue after the waiting time has elapsed.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 8, 2019
    Assignee: VIACOM INTERNATIONAL INC.
    Inventor: Richard Torpey
  • Patent number: 10169272
    Abstract: A data processing apparatus is provided, which includes: a plurality of processor cores; a shared processor cache, the shared processor cache being connected to each of the processor cores and to a main memory; a bus controller, the bus controller being connected to the shared processor cache and performing, in response to receiving a descriptor sent by one of the processor cores, a transfer of requested data indicated by the descriptor from the shared processor cache to an input/output (I/O) device; a bus unit, the bus unit being connected to the bus controller and transferring data to/from the I/O device; wherein the shared processor cache includes means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access in response to receiving a descriptor from the one of the processor cores.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekaterina M. Ambroladze, Norbert Hagspiel, Sascha Junghans, Matthias Klein, Jeorg Walter
  • Patent number: 10146293
    Abstract: Systems, methods, and firmware for power control of data storage devices are provided herein. In one example, a data storage device is presented. The data storage device includes a storage control system to identify a power threshold for the data storage device. The data storage device determines power consumption characteristics for the data storage device and enters into a power controlled mode for the data storage device that adjusts at least a storage transaction queue depth in the data storage device to establish the power consumption characteristics as below the power threshold for the data storage device.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: December 4, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohammed Ghiath Khatib, Damien Cyril Daniel Le Moal
  • Patent number: 10142231
    Abstract: Technologies for accelerating non-uniform network input/output accesses include a multi-home network interface controller (NIC) of a network computing device communicatively coupled to a plurality of non-uniform memory access (NUMA) nodes, each of which include an allocated number of processor cores of a physical processor package and an allocated portion of a main memory directly linked to the physical processor package. The multi-home NIC includes a logical switch communicatively coupled to a plurality of logical NICs, each of which is communicatively coupled to a corresponding NUMA node. The multi-home NIC is configured to facilitate the ingress and egress of network packets by determining a logical path for each network packet received at the multi-home NIC based on a relationship between one of the NUMA nodes and/or a logical NIC (e.g., to forward the network packet from the multi-home NIC) coupled to the one of the NUMA nodes. Other embodiments are described herein.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventor: Anil Vasudevan
  • Patent number: 10116732
    Abstract: A provider network hosting multiple network-based services that implement different resources for a client may provide automated management of resource attributes across the multiple network-based services. A client may send a request to a resource attribute service implemented at the provider network to add a resource attribute to different resources implemented among different network-based services that satisfy resource metadata selection criteria. In response to receiving the request, resource metadata maintained for the different resources implemented among the different network-based resources, which may include one or more previously applied resource attributes, may be evaluated to identify those resources that satisfy the resource metadata selection criteria. For those resources that satisfy the resource metadata selection criteria, the resource attribute may be added to the resource metadata maintained for the different resources.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: October 30, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Jeffrey Cicero Canton, William Frederick Hingle Kruse
  • Patent number: 9946496
    Abstract: A computing system includes a storage device and a host. The storage device includes a volatile memory and a non-volatile memory, and is configured to receive data for storage in the non-volatile memory, to buffer at least some of the received data temporarily in the volatile memory, and to guarantee that any data, which is not part of a predefined amount of data that was most recently received, has been committed to the non-volatile memory. The host is configured to send the data for storage in the storage device, and, in response to a need to commit given data to the non-volatile memory, to send the given data to the storage device followed by at least the predefined amount of additional data.
    Type: Grant
    Filed: March 20, 2016
    Date of Patent: April 17, 2018
    Assignee: Elastifile Ltd.
    Inventors: Eyal Lotem, Avraham Meir, Shahar Frank
  • Patent number: 9928179
    Abstract: Cache replacement policy. In accordance with a first embodiment of the present invention, an apparatus comprises a queue memory structure configured to queue cache requests that miss a second cache after missing a first cache. The apparatus comprises additional memory associated with the queue memory structure is configured to record an evict way of the cache requests for the cache. The apparatus may be further configured to lock the evict way recorded in the additional memory, for example, to prevent reuse of the evict way. The apparatus may be further configured to unlock the evict way responsive to a fill from the second cache to the cache. The additional memory may be a component of a higher level cache.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Patent number: 9922107
    Abstract: A processing platform integrates ETL (extract, transform, and load), real time stream processing, and “big data” data stores into a high performance analytic system that runs in a public or private cloud. The platform performs real time pre-storage enrichment of data records to form a single comprehensive record usable for analytics, searching and alerting. The platform further supports sharing of components and plug-ins and performs automatic scaling of resources based on real time resource monitoring and analysis.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: March 20, 2018
    Assignee: Leidos, Inc.
    Inventors: Thomas James Cannaliato, Joshua A. Decker, Matthew William Vahlberg
  • Patent number: 9846549
    Abstract: A data server, method and computer readable storage medium for receiving a current request relating to a data archive, determining a number of queued requests relating to the data archive present in a request queue, determining a waiting time for the current request based on the number of queued requests and adding the current request to the request queue after the waiting time has elapsed.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: December 19, 2017
    Assignee: VIACOM INTERNATIONAL INC.
    Inventor: Richard Torpey
  • Patent number: 9753734
    Abstract: A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Mohammad A. Abdallah, Mandeep Singh
  • Patent number: 9747044
    Abstract: In an all-flash storage array, write requests can take about 9 to 10 times longer than a read request of the same size. There could be several problems when reading or writing from all-flash storage, such as a large write request slowing down small read requests, or other write requests. Also, a large read request may slow down smaller read requests by filling the incoming requests queue. In one implementation, a determination is made on what is the maximum size of a request to flash storage that improves the throughput of a flash chip (e.g., write requests beyond a certain size do not improve throughput). A chunklet is defined as a block of data having the calculated maximum size. As write requests come in, the write requests are broken into chunklets, and then the chunklets are queued for processing by the flash chip. One chunklet is processed at a time per write request.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 29, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Anil Kumar Nanduri, Murali Krishna Vishnumolakala
  • Patent number: 9742683
    Abstract: A method is provided in one example embodiment and includes determining whether a packet received at a network node in a communications network is a high priority packet; determining whether a low priority queue of the network node has been deemed to be starving; if the packet is a high priority packet and the low priority queue has not been deemed to be starving, adding the packet to a high priority queue, wherein the high priority queue has strict priority over the low priority queue; and if the packet is a high priority packet and the low priority queue has been deemed to be starving, adding the packet to the low priority queue.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 22, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Erico Vanini, Rong Pan, Thomas J. Edsall
  • Patent number: 9734101
    Abstract: A method, system, and computer program product identify extraneous input/output interrupts for a queued input/output device architecture. At least one interrupt is determined to have been generated for at least one queue in a plurality of queues of a queued input/output device architecture. The interrupt is identified as an extraneous interrupt in response to the determining one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and that the queue fails to include at least one pending reply for a previously received unprocessed interrupt.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventor: Louis P. Gomes
  • Patent number: 9727364
    Abstract: A hypervisor retrieves a packet written by a guest operating system of a virtual machine from hypervisor memory accessible to the guest operating system. The Hypervisor then adds the packet of the guest operating system to at least one receive queue associated with a virtual device. The hypervisor pauses the retrieving of additional packets from the guest upon determining that the at least one receive queue size has met a first predetermined threshold condition. The hypervisor processes queued packets from the at least one receive queue sequentially. The hypervisor restarts the retrieving of the additional packets from the guest upon determining that the at least one receive queue size has met a second predetermined threshold condition.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: August 8, 2017
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 9665719
    Abstract: A system and method can support controlled and secure firmware upgrade in a middleware machine environment. The system can provide a boot image of an operating system (OS) in a host node, wherein the host node connects to a shared resource, such as a network fabric, via an input/out (I/O) device. The boot image can receive at least one of a firmware image and a firmware update from the host node, and upgrade firmware in the I/O device associated with the host node. Furthermore, the host-based firmware upgrade can be based on a special boot image that is prevented from accessing local information on the host node, or a normal boot image that is prevented from controlling the I/O device.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: May 30, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Bjørn Dag Johnsen, Martin Paul Mayhead
  • Patent number: 9658968
    Abstract: A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The controller manages write cache data and metadata with minimum or no firmware involvement for greatly enhancing performance.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: May 23, 2017
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Bakke, Joseph R. Edwards, Robert E. Galbraith, Adrian C. Gerhard, Daniel F. Moertl, Gowrisankar Radhakrishnan, Rick A. Weckwerth
  • Patent number: 9652385
    Abstract: An apparatus and method are provided for handling atomic update operations. The apparatus has a cache storage to store data for access by processing circuitry, the cache storage having a plurality of cache lines. Atomic update handling circuitry is used to handle performance of an atomic update operation in respect of data at a specified address. When data at the specified address is determined to be stored within a cache line of the cache storage, the atomic update handling circuitry performs the atomic update operation on the data from that cache line. Hazard detection circuitry is used to trigger deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage is pending that will cause a chosen cache line to be populated with data that includes data at the specified address. The linefill operation causes the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: May 16, 2017
    Assignee: ARM Limited
    Inventors: Gregory Andrew Chadwick, Adnan Khan
  • Patent number: 9588913
    Abstract: Embodiments of the present invention provide systems, methods, and computer program products for managing computing devices to handle an input/output (I/O) request. In one embodiment, the I/O request may eligible for performance throttling based, at least in part, on the associated importance level for performing the received I/O request and one or more characteristics of the received I/O request. Embodiments of the present invention provide systems, methods, and computer program products for throttling the I/O request and transmitting the I/O request to a storage controller.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Susan K. Candelaria, Scott B. Compton, Deborah A. Furman, Ilene A. Goldman, Matthew J. Kalos, John R. Paveza, Beth A. Peterson, Dale F. Riedy, David M. Shackelford, Harry M. Yudenfriend
  • Patent number: 9557920
    Abstract: A data server, method and computer readable storage medium for receiving a current request relating to a data archive, determining a number of queued requests relating to the data archive present in a request queue, determining a waiting time for the current request based on the number of queued requests and adding the current request to the request queue after the waiting time has elapsed.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: January 31, 2017
    Assignee: VIACOM INTERNATIONAL INC.
    Inventor: Richard Torpey
  • Patent number: 9558149
    Abstract: A dual system according to the present invention includes: a memory copying unit configured to, when an arithmetic device of a first computer module is installed into the dual system, execute a memory copy process of copying data in a memory region of a second computer module into a memory region of the first computer module; a substitute processing unit configured to execute a service substitute process that is executed by a different arithmetic device from an arithmetic device executing the memory copy process and that is part of processes involved in the information processing service by the dual system; and a shared memory that stores data of the service substitute process by the substitute processing unit. The shared memory is excluded from the target of the memory copy process.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 31, 2017
    Assignee: NEC CORPORATION
    Inventor: Sayuri Fuse
  • Patent number: 9557935
    Abstract: Provided is a method of writing data of a storage system. The method includes causing a host to issue a first writing command; causing the host, when a queue depth of the first writing command is a first value, to store the first writing command in an entry which is assigned in advance and is included in a cache; causing the host to generate a writing completion signal for the first writing command; and causing the host to issue a second writing command.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: January 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pradeep Bisht, Jiurong Cheng, Jong-tae Park, Sung-chul Kim, Seung-yeun Jeong, Sang-jin Oh, Jung-ho Kim
  • Patent number: 9535864
    Abstract: The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: January 3, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Shintaro Kudo, Yusuke Nonaka
  • Patent number: 9514072
    Abstract: An input/output (I/O) request is received that indicates a priority for performing the received I/O request by a storage controller. If a base device is not available to handle the received I/O request, whether the received I/O request is eligible for performance throttling is determined. The received I/O request is transmitted to the storage controller indicating whether the received I/O request is eligible for performance throttling. An alias device is allocated to the base device based on the priority for performing the received I/O request. If the throttling information received from the storage controller for the previous I/O request indicates that a request type of the received I/O request is not being throttled, and it is determined that the received I/O request is a new request, then a control block is representing the base device is flagged, indicating that the received I/O request is eligible for performance throttling.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Susan K. Candelaria, Scott B. Compton, Deborah A. Furman, Ilene A. Goldman, Matthew J. Kalos, John R. Paveza, Beth A. Peterson, Dale F. Riedy, David M. Shackelford, Harry M. Yudenfriend
  • Patent number: 9501535
    Abstract: A processing platform integrates ETL (extract, transform, and load), real time stream processing, and “big data” data stores into a high performance analytic system that runs in a public or private cloud. The platform performs real time pre-storage enrichment of data records to form a single comprehensive record usable for analytics, searching and alerting. The platform further supports sharing of components and plug-ins and performs automatic scaling of resources based on real time resource monitoring and analysis.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 22, 2016
    Assignee: Leidos, Inc.
    Inventors: Thomas James Cannaliato, Joshua A. Decker, Matthew William Vahlberg
  • Patent number: 9489141
    Abstract: In an all-flash storage array, write requests can take about 9 to 10 times longer than a read request of the same size. There could be several problems when reading or writing from all-flash storage, such as a large write request slowing down small read requests, or other write requests. Also, a large read request may slow down smaller read requests by filling the incoming requests queue. In one implementation, a determination is made on what is the maximum size of a request to flash storage that improves the throughput of a flash chip (e.g., write requests beyond a certain size do not improve throughput). A chunklet is defined as a block of data having the calculated maximum size. As write requests come in, the write requests are broken into chunklets, and then the chunklets are queued for processing by the flash chip. One chunklet is processed at a time per write request.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 8, 2016
    Assignee: Nimble Storage, Inc.
    Inventors: Anil Kumar Nanduri, Murali Krishna Vishnumolakala
  • Patent number: 9477618
    Abstract: An information processing device, comprising: a memory; and one or more central processing units coupled to the memory and configured to: control accesses to a device based on requests from users, record a start time of each access to the device and an end time of the access to the device, determine a load state of the device based on an elapsed time period from the start time to the end time, and limit, based on the load state of the device, a number of threads for one of the users, the threads being concurrently executed to access the device based on access requests to the device from the one of the users.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: October 25, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Hideki Takakura
  • Patent number: 9477516
    Abstract: A method includes allocating a first memory location in a non-transitory data store in communication with a computing device and writing data to the first memory location when a first write transaction executes on the non-transitory data store. The method further includes executing one or more read transactions on the first memory location after completion of the first write transaction and incrementing a first pointer counter upon completion of the first write transaction and for each read transaction executing on the first memory location. The method allocates a second memory location in the non-transitory data store and writes updated data to the second memory location when a second write transaction executes on the non-transitory data store to update the data. The first pointer counter decrements and the second pointer counter increments upon completion of the second write transaction. The first memory location de-allocates when the first pointer counter is zero.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: October 25, 2016
    Assignee: Google Inc.
    Inventors: Timothe Hockin, Jakub Onufry Wojtaszczyk, Jaroslaw Przybylowicz, Erik Christian Haugen, Xiaohui Chen
  • Patent number: 9448740
    Abstract: Proposed are a storage apparatus and a hierarchy control method capable of reducing the workload of system operation and the workload of performance investigation. An access frequency of each of a plurality of measurement cycles for each unit area in a virtual volume is measured in a storage apparatus loaded with a hierarchy control function, the storage hierarchy which is proper as a placement destination of data written in each of the unit areas of the virtual volume is determined based on a measurement result, and the data written in a necessary unit area in the virtual volume is relocated to the storage area to which belongs the storage hierarchy that was determined as being proper based on a determination result.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: September 20, 2016
    Assignee: HITACHI, LTD.
    Inventors: Hiromichi Aiura, Hiroshi Koizumi
  • Patent number: 9438482
    Abstract: A server in a distributed environment includes a process that manages incoming client requests and selectively forwards service requests to other servers in the network. The server includes storage in which at least one forwarding queue is established. The server includes code for aggregating service requests in the forwarding queue and then selectively releasing the requests, or some of them, to another server. The queuing mechanism preferably is managed by metadata, which, for example, controls how many service requests may be placed in the queue, how long a given service request may remain in the queue, what action to take in response to a client request if the forwarding queue's capacity is reached, etc. In one embodiment, the server generates an estimate of a current load on an origin server (to which it is sending forwarding requests) and instantiates the forward request queuing when that current load is reached.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: September 6, 2016
    Assignee: Akamai Technologies, Inc.
    Inventors: William E. Weihl, Gene Shekhtman
  • Patent number: 9389866
    Abstract: Disclosed is a method of analysis of a computer program instruction for use in a central processing unit having a decoding unit. The method comprises receiving an address of an instruction to be analysed, fetching said instruction stored at said address, decoding by a decoding unit associated with the central processing unit, the fetched instruction; and returning the results of said decoding of said fetched instruction. The decoded results are returned as a data block stored in memory associated with the central processing unit or in one or more registers of the central processing unit. The decoded results include the type of the instruction and/or the instruction length. The method optionally further comprises analysing the decoded results to determine whether the instruction may be replaced with one of a trap or a break point. Also disclosed is a system and computer program for analysis of a computer program instruction for use in a central processing unit having a decoding unit.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: July 12, 2016
    Assignee: International Business Machines Corporation
    Inventor: David A. Gilbert
  • Patent number: 9298393
    Abstract: An intelligent write command routine improves the operational efficiency of a data storage device (DSD) by avoiding media access of the disk when a logical block address (LBA) and the physical sector are unaligned, thus reducing write time. When a write command is received by the DSD from the host, the intelligent write command routine maintains the read data of the read buffer, instead of clearing the read buffer and performing a read of the target sector on the disk per standard protocol. The intelligent write command copies the necessary adjacent sector data from the read buffer as a data patch to the write buffer to splice around the write data received with the write command. Following each write command, the data written to the disk in the write buffer is copied to the read buffer. The read buffer is maintained with the most current data on the disk and does not need to be flushed unless the LBA of the write command is beyond the data ranges stored in the read buffer.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: March 29, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: KokChoon See, Wesley Chan, CheeSeng Toh, PohGuat Bay, ChweeFern Ee, YongPeng Chng
  • Patent number: 9122401
    Abstract: A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: September 1, 2015
    Assignee: Apple Inc.
    Inventors: Etai Zaltsman, Oren Golov, Ori Moshe Stern, Shai Ojalvo
  • Patent number: 9122413
    Abstract: A method and controller for implementing hardware auto device op initiator in a data storage system, and a design structure on which a subject controller circuit resides are provided. The controller includes an inline hardware engine receiving host commands, and assessing a received command for starting without firmware involvement. The inline hardware engine builds one or more chains of hardware command blocks to perform the received command and starts executing the chain or chains for the received command.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Bakke, Adrian C. Gerhard, Daniel F. Moertl, Rick A. Weckwerth
  • Patent number: 9110878
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 18, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 9098358
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 4, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 9092502
    Abstract: A processing platform integrates ETL (extract, transform, and load), real time stream processing, and “big data” data stores into a high performance analytic system that runs in a public or private cloud. The platform performs real time pre-storage enrichment of data records to form a single comprehensive record usable for analytics, searching and alerting. The platform further supports sharing of components and plug-ins and performs automatic scaling of resources based on real time resource monitoring and analysis.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 28, 2015
    Assignee: Leidos, Inc.
    Inventors: Thomas James Cannaliato, Joshua A. Decker, Matthew William Vahlberg
  • Patent number: 9047311
    Abstract: Approaches for retrieving files from a replicated file system. A component receives, from a requestor, a request for a copy of a data unit. The component identifies a plurality of storage nodes that each stores a complete copy of the data unit. The component sends, to the plurality of storage nodes, an instruction to retrieve a copy of the data unit within a specified period of time. At each storage node receiving an instruction, a determination of whether the copy of the data unit may be retrieved within the specified period of time is made, and if so, the copy of the data unit is provided to the component only if the copy of the data unit was actually retrieved within the specified period. The component provides the first copy of the data unit it receives to the requestor and discards any subsequently received copies of the data unit.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: June 2, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Zvonimir Bandic, Filip Blagojevic, Cyril Guyot, Timothy Tsai, Qingbo Wang
  • Patent number: 9043512
    Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: May 26, 2015
    Assignee: Google Inc.
    Inventor: Arif Merchant
  • Patent number: 9032174
    Abstract: A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventor: Naoki Nishiguchi
  • Patent number: 9021158
    Abstract: A memory device includes a memory array with a plurality of memory elements. Each memory element is configured to store data. The device includes an input/output (I/O) buffer coupled to the memory array. The I/O buffer is configured to receive data from an I/O interface of a memory device controller and write the data to the memory array. The device includes a memory control manager coupled to the memory array. The memory control manager is configured to pause a program operation to the memory array in response to receiving a pause command. The memory control manager is also configured to resume the program operation in response to receiving a resume command.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 28, 2015
    Assignee: SanDisk Technologies, Inc.
    Inventors: Jea Woong Hyun, Mark Brinicombe, Hairong Sun, Hao Zhong, John Strasser, Robert Wood