Abstract: A memory controller may calculate a sum of a first number of entries stored in a read buffer and a second number of entries stored in a write buffer. If the sum is less than a first threshold and the read/write buffer is not full of entries, then the memory controller can request read/write commands from a host computing device. If the sum is not less than the first threshold or the read/write buffer is full of entries, then the memory controller can assert backpressure to stop the incoming flow newly incoming read/write commands from the host computing device. Additionally, or alternatively, the memory controller may dequeue a write command entry only if a number of write command entries stored in a write command FIFO memory is greater than a second threshold.

Abstract: A L2 set associative cache that is inclusive of an L1 cache. Each entry of a load queue holds a load physical address proxy (PAP) for a load physical memory line address (PMLA) rather than the load PMLA itself. The load PAP comprises the set index and the way that uniquely identifies the L2 entry that holds a memory line specified by the load PMLA. Each load queue entry indicates whether the load instruction has completed execution. The microprocessor removes a memory line at a removal PMLA from an L2 entry and forms a removal PAP as a proxy for the removal PMLA. The removal PAP comprises a set index and a way that uniquely identifies the removed entry. The microprocessor snoops the load queue with the removal PAP to determine whether the removal PAP matches one or more load PAPs in one or more load queue entries associated with one or more load instructions that have completed execution and, if so, signals an abort request.

Abstract: Provided is a method of packet processing, the method including receiving an input/output (IO) request from a host, selecting a drive corresponding to the IO request using a hashing algorithm or a round-robin technique, and establishing a connection between the host and the drive.

Abstract: Compact and scalable mutual exclusion techniques are implemented for multiple executing threads. A thread may acquire a lock by swapping a pointer to the thread into a tail field of a lock data structure. If the swap operation returned a null value, then the lock is acquired. If the swap operation does not return a null value, then the thread may wait to obtain the lock from a predecessor thread. The thread may wait until a grant field in a data structure for the predecessor thread stores a pointer to the lock, signaling to the thread that the thread may acquire the lock.

Abstract: A memory controller includes a request queue and associated logic for efficiently managing the request queue based on various timing constraints of the memory device. A single request queue for the memory device stores read and write requests spanning different banks of the memory device. In each memory controller cycle, selection logic may select both a row request and a column request (relating to a different bank than the row request) for issuing to the memory device based on a set of timing status bits. Following issuance of requests, the memory controller updates the queue to maintain the queued requests in a time-ordered, compressed sequence. The memory controller furthermore updates the timing status bits that are used by the selection logic to select requests from the queue based on a history of past memory requests.

Abstract: A memory system provides deduplication of user data in the physical memory space of the system for user data that is duplicated in the virtual memory space of a host system. A transaction manager (TM) uses a transaction table to maintain data coherency and data concurrency for the virtual memory space. A write data engine manager (WDEM) uses an outstanding bucket number and command queues to maintain data coherency and data concurrency for the physical memory space. The WDEM receives data write requests from the TM and sends a corresponding write command to a selected command queue. A write data engine responds to a write command in a command queue by storing the data in an overflow memory region if the data is not duplicated in the virtual memory space, or by incrementing a reference counter for the data if the data is duplicated in the virtual memory space.

Abstract: The disclosed computer-implemented method for tracking miss requests using data cache tags can include generating a data cache miss request associated with data requested in connection with a cacheline and allocating a miss address buffer entry for the miss request. Additionally, the method can include, setting a fill-pending flag associated with the cacheline in response to the data associated with the data cache miss request being absent from a first data cache, and de-allocating the miss address buffer entry. In the event that another load or store operation requests the same data associated with the cacheline while the fill-pending flag is set, the method can include monitoring for a fill response associated with the miss request until the fill response is received. Upon receipt of the fill response, the method can include re-setting the fill-pending flag associated with the cacheline.

Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.

Abstract: A storage system in which a controller has an encryption-related function is provided. There is provided a storage system including an interface section coupled to one or more storages and a controller that carries out reading and writing processes on the storages via the interface section. The controller includes an arithmetic processing section, a memory, and an encryption processing section. The arithmetic processing section causes the memory to hold data before processing and data after processing by the encryption processing section, and limits the access destination from the storages to the memory. The configuration and actions described above allow the storage system to avoid occurrence of deadlock and the controller to have an encryption-related function.

Abstract: Methods, systems, and devices for techniques for storing journaling information are described. A memory device may receive a first command to configure a circular buffer using memory cells of a nonvolatile memory device. The first command may include one or more labels associated with the circular buffer. The memory device may configure the circular buffer based at least in part on receiving the first command. The memory device may receive a second command to write journaling data to the nonvolatile memory device based at least in part on configuring the circular buffer. The second command may specify a label of the one or more labels. The memory device may generate an entry at a physical address indicated by a pointer of the circular buffer available to store the journaling data in the circular buffer based at least in part on the label specified by the second command.

Abstract: A memory controller is capable of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM. The memory controller comprises a receiving unit configured to receive a request to the DRAM from a bus; a determining unit configured to determine whether a command that is after the second write command when a reception sequence of a request is observed is issuable in a period until the second write command is issued after a preceding command is issued; and an issuing unit configured to issue a command determined to be issuable before the second write command.

Abstract: Provided is a server delay control system for performing, on a server including a Host OS, packet transfer between a physical NIC connected to the Host OS and an application deployed in a user space. A server delay control device configured to perform polling for packet transfer on behalf of the application is deployed in the user space. The server delay control device creates, between the application and the physical NIC, a communication path for communication via socket communication. The communication path includes a first queue and a second queue. The server delay control device includes: a packet dequeuer configured to poll whether a packet has been enqueued into the first queue and to dequeue the enqueued packet from the first queue; and a packet enqueuer configured to enqueue the dequeued packet into the second queue in the same context as the polling and dequeuing without causing a context switch.

Abstract: A memory anomaly processing method and system, an electronic device, and a storage medium. The method includes: reading a memory error quantity of a target memory bank from a memory error register; when the memory error quantity is greater than a preset value, executing a hot-removal operation on the target memory bank; calculating a memory delay parameter, and writing the memory delay parameter into a memory controller, wherein the memory delay parameter is waiting time after the memory controller controls the target memory bank to receive a read/write command; and executing a hot-addition operation on the target memory bank, whereby the memory controller continues to execute a read/write operation on the target memory bank based on the memory delay parameter. It can be seen that, according to the present application, the memory read/write error rate may be reduced.

Abstract: Detecting a trend in latency for storage underlying a deduplicated file system includes generating a set of data points by recording when input/output (IO) requests were issued to the storage and recording time required to receive success responses from the storage. Least squares regression is performed on the data points to find a best-fit line through the data points. A slope of the best-fit line is calculated. A determination is made as to whether the slope is positive, a positive slope thereby indicating a trend of increasing latency of the storage. When the slope is determined to be positive, clients accessing the deduplicated file system are throttled.

Abstract: Storage devices are configured to be utilized in a variety of blockchain related activities that rely on a proof of space consensus model. These storage devices are required to process a lot of read and write cycles on their memory devices to generate the desired proof of space consensus data. The generation and storing of this generated data requires very different types of memory device usage. Storage devices may be configured to optimize these different usage types upon detecting these proof of space blockchain activities. These optimizations can include suspending one or more background or other garbage collection activities. Additional optimizations can further include configuring partitions or namespaces to comprise single-level-cell majority or single-level-cell only memory devices to increase writing speeds. Further optimizations can include interleaving or extending the length of error correction codes.

Abstract: A method includes calculating, by a data storage device processor, at least one access trajectory from a first disc surface location to at least one second disc surface location at which at least one primary data access operation is to be carried out. The method also includes determining, by the data storage device controller, whether an opportunity to commence at least one secondary data access operation exists along or proximate to the at least one access trajectory from the first disc surface location to the at least one second disc surface location.

Abstract: Provided are a method, an apparatus, and a memory controller coupled to a plurality of storage dies, wherein the memory controller implements logic to perform operations with respect to the storage dies, the operations comprising: maintaining a calendar based scheduling mechanism that is programmed by a firmware to support a quality of service scheduling in a solid state drive in which the memory controller is included; and determining, by a flash command scheduler, from the calendar based scheduling mechanism, which traffic class to service.

Abstract: According to one embodiment, a magnetic disk device includes a first head which writes and reads to the first disk, a second head which writes data and reads data to the second disk, a first actuator including the first head, a second actuator including the second head, and a controller which performs a first reordering process for a command scored in a first queue corresponding to the first actuator and performs a second reordering process for a command stored in a second queue corresponding to the second actuator, wherein the controller selects a first command to be executed next by the first actuator based on current and future operating states of the second actuator, and executes the first command.

Abstract: Described apparatuses and methods enable a receiver of requests, such as a memory device, to modulate the arrival of future requests using a credit-based communication protocol. A transmitter of requests can be authorized to transmit a request responsive to possession of a credit corresponding to the communication request. In these situations, if the transmitter has exhausted a supply of credits, the transmitter waits until a credit is returned before transmitting another request. The receiver of the requests can manage credit returns based on whether a request queue has space to receive another request. Further, the receiver can delay a credit return based on how many requests are pending at the receiver, even if space is available in the request queue. This delay can prevent an oversupply of requests from developing downstream of the request queue. Latency, for instance, can be improved by managing the presence of requests that are downstream.

Abstract: In some embodiments, a method stores a plurality of requests for routes in a queue based on respective priorities for the routes. The plurality of requests are for programming destinations and next hops for the destinations in a route table that is used by a device in a network to route packets. The method selects a request for a route from the queue based on a respective priority for the queue. Then, the request for the route is sent to an entity to program the route in the route table.

Abstract: A storage product manufactured as a computer component to facilitate network storage services. The storage product has a bus connector, a network interface, and a local storage device. A message selection configuration can be written into the storage product to control separation of incoming messages received in the network interface into first messages and third messages. The first messages are sent through the bus connector for processing by a local host system to generate second messages. The second messages and the third messages are sent to the local storage device. The local storage device processes the second messages and the third messages to implement the network storage services.

Abstract: A method and system for streaming data from portable storage devices. Specifically, the disclosed method and system implement iterative data streaming from a portable storage device for remote storage operations, while requiring zero over-provisioning storage space for buffering incoming write operations to the portable storage device.

Abstract: A multiple function storage device is disclosed. The multiple function storage device may include an enclosure, a storage device associated with the enclosure, and an bridging device associated with the enclosure. The storage device may include a connector to receive a first message using a first protocol originating at a host, a physical function (PF) and a virtual function (VF) exposed by the storage device via the connector, storage for data relating to the first message, and a controller to manage writing a write data to the storage and reading a read data from the storage.

Abstract: Systems and methods for automated tuning of Quality of Service (QoS) settings of volumes in a distributed storage system are provided. According to one embodiment, responsive to a predetermined event, information regarding a multiple QoS settings assigned to a volume of a distributed storage system that is being utilized by a client are obtained. A difference between a first QoS setting of the multiple QoS settings and a second QoS setting of the multiple QoS settings is determined. Responsive to determining the difference is less than a threshold a new value of the first QoS setting or a third QoS setting of the multiple QoS settings that is greater than a respective current value of the first QoS setting or the third QoS setting is determined and assigned to the volume for the client.

Abstract: A memory controller includes an arbiter for selecting memory requests from a command queue for transmission to a dynamic random access memory (DRAM) memory. The arbiter includes a bank group tracking circuit that tracks bank group numbers of three or more prior write requests selected by the arbiter. The arbiter also includes a selection circuit that selects requests to be issued from the command queue, and prevents selection of write requests and associated activate commands to the tracked bank group numbers unless no other write request is eligible in the command queue. The bank group tracking circuit indicates that a prior write request and the associated activate commands are eligible to be issued after a number of clock cycles has passed corresponding to a minimum write-to-write timing period for a bank group of the prior write request.

Abstract: This application discloses a data prefetching method, including: receiving, by a home node, a write request sent by a first cache node after the first cache node processes received data; performing, by the home node, an action of determining whether the second cache node needs to perform a data prefetching operation on the to-be-written data; and when determining that the second cache node needs to perform a data prefetching operation on the to-be-written data, sending, by the home node, the to-be-written data to the second cache node. Embodiments of this application help improve accuracy and certainty of a data prefetching time point, and reduce a data prefetching delay.

Abstract: A method begins by a processing module of a storage network analyzing storage network memory for a level of usability and based on the analyzing, selecting alternative memory available for receipt of encoded data slices stored in current memory, where a data object is segmented into a plurality of data segments and a data segment of the plurality of data segments is dispersed error encoded in accordance with dispersed error encoding parameters to produce a set of encoded data slices. The method continues with the processing module determining whether to move encoded data slices from current memory to alternative memory and based on a determination to move slices, allocating alternative memory. Finally, the processing module moves at least some encoded data slices from a current memory to alternate memory and updates a memory assignment mechanism for the at least some encoded data slices.

Abstract: The present invention relates to systems and methods for controlling real-time traffic surge at a server [102]. An Application Programming Interface (API) gateway [104] receives at least one service request from at least one application device [106] for availing at least one service from a server [102], and enables at least one part of the server [102] based on a count of the received requests determined by a load counter. A throttling parameter, including one of a static throttling parameter and a dynamic throttling parameter, is determined by a throttling parameter module [204] for the enabled at least one part of the server [102]. The API gateway [104] validates the at least one service request based on the count and the throttling parameter. Thereafter, the at least one part of the server [102] provides at least one service to the validated at least one application device [106].

Abstract: A storage device includes a nonvolatile memory device that includes a first region including memory cells configured to store n-bit data and a second region including memory cells configured to store m-bit data and a memory controller, where n and m are natural numbers and n is less than m. The first region includes a first area and a second area, and the second region includes a third area. The memory controller is configured to perform one of a turbo write operation on the first area or the second area and a normal write operation on the third area, and configured to perform one of a turbo read operation on the first area or the second area and a normal read operation on the third area.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

Abstract: An apparatus comprises a host device that includes a multi-path input-output (MPIO) driver configured to control delivery of input-output (IO) operations from the host device to first and second storage systems over selected paths through a network. The MPIO driver is further configured to identify a connectivity failure between the host device and a given one of the first and second storage systems, to generate a message comprising one or more details of the connectivity failure, and to send the message to a remaining one of the first and second storage systems over at least one path of a plurality of paths between the host device and the remaining one of the storage systems. The first and second storage systems in some embodiments are arranged in an active-active configuration relative to one another, with one being designated as a non-bias and the other as a bias storage system.

Abstract: An adaptation method between PCIE and SPI realized based on FPGA, comprising following steps: S01: a PCIE equipment sends PCIE information to a mapping module through a PCIE module; S02: the mapping module extracts SPI information from the PCIE information and transmits the SPI information to a SPI equipment through an SPI module; all of the PCIE module, the mapping module and the SPI module are located on a FPGA chip; S03: the SPI equipment performs a read/write operation according to the SPI information, and feeds back SPI operation information subjected to the read/write operation to the mapping module; S04: the mapping module modifies PCIE information according to the SPI operation information to obtain PCIE feedback information; S05: the PCIE equipment reads the PCIE feedback information through the PCIE module.

Abstract: A method for communication includes receiving in a network device work requests posted by a host processor to perform a series of communication transactions, including at least a first transaction and a second transaction comprising first and second operations to be executed in a sequential order in response to corresponding first and work requests posted by the host processor. In response to the work requests, data packets are transmitted over a network from the network device to a destination node and corresponding responses are received from the destination node. Based on the received responses, completion of the first operations in the first transaction is reported from the network device to the host processor according to the sequential order, and completion of the second operation in the second transaction is reported from the network device to the host processor regardless of whether the first transaction has been completed.

Abstract: This disclosure relates to high-performance computing, and more particularly to techniques for kernel-assisted device polling of user-space devices. A common kernel-based polling mechanism is provided for concurrently handling both kernel-based polling for kernel-space devices such as network interfaces (e.g., network NICs) and kernel-based polling for user-space devices such as remote direct memory access devices (e.g., RDMA NICs). Embodiments perform kernel-based polling on a first device that has a corresponding device driver in an operating system kernel. Using the same polling mechanism, the kernel-based polling is performed on a second device, the second device being a user-space device wherein the kernel-based polling on the second device is configured by creating a second device file descriptor that is not associated with a corresponding device driver in the operating system kernel.

Abstract: Methods, systems, and devices for techniques for command sequence adjustment are described. A memory system or a host system may adjust an order of a set commands in a queue if the memory system or host system determines that a subset of the commands in the queue are part of a test mode, for example by determining whether each command of the subset corresponds to a same size of data. The set of commands may be reordered such that the subset of commands associated with the test mode are continuous or back-to-back. In some cases, the subset of commands associated with test mode may be reordered such that logical addresses (e.g., logical block addresses) of the subset of commands are continuous.

Abstract: A communications device that includes a requester and a responder may support multiple transaction classes, including an ordered transaction class, while maintaining a bifurcated requester/responder architecture. Before a responder has a non-posted transaction response to transmit on an interconnect, it receives an indication from the requester that there is not a pending posted transaction on the interconnect.

Abstract: Systems, methods and instruction sets are provided for performing operations with respect to analyzing firmware. A firmware event tracker creates a tracker event log including event-items pertaining to events occurring during execution of the firmware; classifies each of the events as a first class event or a second class event; and stores the first and second class events in separate pools in a tracker storage.

Abstract: A security solution having a system, a method, or a computer program for protecting contents in a target storage device that is arranged to be removable from a storage system having a unique combination of a system complex key (SCK) and a system identification (SID). The solution includes receiving a request to remove the target storage device from the storage system, where the storage system may have a plurality of storage devices each containing the identical combination of system complex key (SCK) and system identification (SID), and receiving a system complex key password (SCKP). The solution includes comparing the system complex key password (SCKP) to the system complex key (SCK) in the storage system, determining whether the system complex key password (SCKP) matches the system complex key (SCK) in the storage system, and suspending all read or write operations to the target storage device when the system complex key password (SCKP) matches the system complex key (SCK) in the storage system.

Abstract: In one aspect of write sort management in accordance with the present disclosure, a sort/no-sort determination is made prior to issuing to a write command to a target storage controller. The write command identifies a write data unit such track write data, for example, of a first write list of write data units to be written to storage locations of storage. The write command further identifies the storage location at which the write data unit of the first write list is to be stored. In one embodiment, the sort/no-sort determination determines whether an insertion point for an entry in a target write list is to be determined as a function of a write list search such as a logarithmic time search for a write list sort. As a result, the write list search for a write list sort, may be selectively either performed or bypassed for insertion of the target write list entry as a function of the sort/no-sort determination Other aspects and advantages are provided, depending upon the particular application.

Abstract: A storage controller includes a processing device to send a Non-Volatile Memory Express over Fibre Channel (NVMe/FC) command to a submission queue without routing the NVMe/FC command through a kernel space, the submission queue being reserved for direct access by an initiator device to a user space of the storage controller.

Abstract: Technology is disclosed for allocating PCIe bus bandwidth to storage commands in a peer-to-peer environment. A non-volatile storage system has a peer-to-peer connection with a host system and a target device, such as a GPU. A memory controller in the storage system monitors latency of PCIe transactions that are performed over a PCIe bus in order to transfer data for NVMe commands. The PCIe transactions may involve direct memory access (DMA) of memory in the host system or target device. There could be a significant difference in transaction latency depending on what memory is being accessed and/or what communication link is used to access the memory. The memory controller allocates bandwidth on a PCIe bus to the NVMe commands based on the latencies of the PCIe transactions. In an aspect, the memory controller groups the PCIe addresses based on the latencies of the PCIe transactions.

Abstract: Systems and methods for managing queue limit overflow for data storage device arrays are described. Host storage connections are allocated by host connection identifier and storage device processing queues are allocated by completion connection identifier through a connection virtualization layer. Storage commands may be directed to a processing queue based on the host connection identifier. Responsive to determining that the processing queue has reached its queue depth limit, another processing queue is determined for receiving the storage command without indicating processing queue overflow to the host device.

Abstract: Embodiments are directed to managing communication over one or more networks. A monitoring engine may be instantiated to perform actions including receiving network traffic from a physical network that may be associated with network addresses of the physical network. The monitoring engine may analyze the network traffic to associate activity with gateway identifiers (GIDs) associated with gateway computers in an overlay network such that the GIDs are separate from the network addresses. The monitoring engine may be arranged to monitor the network traffic based on monitoring rules. The monitoring engine may provide metrics associated with the gateway computers based on the monitoring of the network traffic. The monitoring engine may compare the metrics to event rules. The monitoring engine may generate events based on affirmative results of the comparison. The events may be mapped to actions based on characteristics of the events and executed.

Abstract: Techniques for managing memory involve: determining a set of weights corresponding to a plurality of command queues in the memory, each weight indicating the number of commands allowed to be transmitted in a corresponding command queue; detecting whether a transmission delay occurs in the plurality of command queues; and adjusting the set of weights based on a result of the detection. Accordingly, transmission and processing efficiencies of commands in a command queue can be improved, and transmission bandwidth can be used more efficiently.

Abstract: Performing refresh operation in a memory device is provided. A refresh operation without address rotation is performed in a cell array of the memory device. Performing the refresh operation without address rotation is repeated for a predetermined number of times. After repeating performing the refresh operation with address rotation for the predetermined number of times, a refresh operation with address rotation is performed in the cell array.

Abstract: A storage device includes a memory and a controller. The controller controls the memory such that, in response to a request for a first read operation on the memory while a first write operation is performed on the memory, the first write operation is suspended, and the first read operation is performed, the suspended first write operation is resumed after the first read operation is completed, and second write operation subsequent to the first write operation is performed on the memory after the resumed first write operation is completed. The controller throttles an amount of data communicated to the memory device for the second write operation or for a second read operation subsequent to the first read operation, based on a frequency that the first write operation is suspended.

Abstract: There is provided with an interface apparatus. The interface apparatus provides a shared cache for a plurality of processing units. A first port acquires data from a first processing unit included in the plurality of processing units. A second port outputs the data acquired from the first processing unit to a second processing unit included in the plurality of processing units. A cache caches the data acquired from the first processing unit. A controller controls, based on information acquired from the second processing unit, whether to write back data written in the cache to a memory different from the cache.

Abstract: A request is obtained that, if fulfilled, is operable to access a computing resource, with the request including an indication to evaluate the request in a verification mode while inhibiting fulfilment of the request. Responsive to the request, a policy applicable to the request is determined, decision data that is relevant to the policy is obtained, and the request is evaluated based at least in part on the policy and the decision data to produce an evaluation result. Further responsive to the request, fulfillment of the request is inhibited, a verification report is generated based at least in part on the evaluation result, and a notification is provided indicating that the verification report is generated.

Abstract: A memory controller is capable of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM. The memory controller comprises a receiving unit configured to receive a request to the DRAM from a bus; a determining unit configured to determine whether a command that is after the second write command when a reception sequence of a request is observed is issuable in a period until the second write command is issued after a preceding command is issued; and an issuing unit configured to issue a command determined to be issuable before the second write command.

Abstract: Processing requests may include: receiving a write request from a host at a first node of a system; and servicing the write comprising assigning, by the first node, a sequence identifier to the write request, wherein the sequence identifier is included in a subsequence of identifiers only assignable by the first node, performing in parallel a first operation that stores first data written by the write request in a cache, a second operation that stores a descriptor for the write request in the cache, and a third operation that sends the descriptor (including the sequence identifier) to a peer node of the system; determining by the first node that the first, second and third operations have successfully completed; and responsive to determining the first, second and third operations have successfully completed, sending an acknowledgement from the first node to a host indicating successful completion of the write request.