Access Request Queuing Patents (Class 710/39)
  • Patent number: 9501535
    Abstract: A processing platform integrates ETL (extract, transform, and load), real time stream processing, and “big data” data stores into a high performance analytic system that runs in a public or private cloud. The platform performs real time pre-storage enrichment of data records to form a single comprehensive record usable for analytics, searching and alerting. The platform further supports sharing of components and plug-ins and performs automatic scaling of resources based on real time resource monitoring and analysis.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 22, 2016
    Assignee: Leidos, Inc.
    Inventors: Thomas James Cannaliato, Joshua A. Decker, Matthew William Vahlberg
  • Patent number: 9489141
    Abstract: In an all-flash storage array, write requests can take about 9 to 10 times longer than a read request of the same size. There could be several problems when reading or writing from all-flash storage, such as a large write request slowing down small read requests, or other write requests. Also, a large read request may slow down smaller read requests by filling the incoming requests queue. In one implementation, a determination is made on what is the maximum size of a request to flash storage that improves the throughput of a flash chip (e.g., write requests beyond a certain size do not improve throughput). A chunklet is defined as a block of data having the calculated maximum size. As write requests come in, the write requests are broken into chunklets, and then the chunklets are queued for processing by the flash chip. One chunklet is processed at a time per write request.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 8, 2016
    Assignee: Nimble Storage, Inc.
    Inventors: Anil Kumar Nanduri, Murali Krishna Vishnumolakala
  • Patent number: 9477516
    Abstract: A method includes allocating a first memory location in a non-transitory data store in communication with a computing device and writing data to the first memory location when a first write transaction executes on the non-transitory data store. The method further includes executing one or more read transactions on the first memory location after completion of the first write transaction and incrementing a first pointer counter upon completion of the first write transaction and for each read transaction executing on the first memory location. The method allocates a second memory location in the non-transitory data store and writes updated data to the second memory location when a second write transaction executes on the non-transitory data store to update the data. The first pointer counter decrements and the second pointer counter increments upon completion of the second write transaction. The first memory location de-allocates when the first pointer counter is zero.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: October 25, 2016
    Assignee: Google Inc.
    Inventors: Timothe Hockin, Jakub Onufry Wojtaszczyk, Jaroslaw Przybylowicz, Erik Christian Haugen, Xiaohui Chen
  • Patent number: 9477618
    Abstract: An information processing device, comprising: a memory; and one or more central processing units coupled to the memory and configured to: control accesses to a device based on requests from users, record a start time of each access to the device and an end time of the access to the device, determine a load state of the device based on an elapsed time period from the start time to the end time, and limit, based on the load state of the device, a number of threads for one of the users, the threads being concurrently executed to access the device based on access requests to the device from the one of the users.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: October 25, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Hideki Takakura
  • Patent number: 9448740
    Abstract: Proposed are a storage apparatus and a hierarchy control method capable of reducing the workload of system operation and the workload of performance investigation. An access frequency of each of a plurality of measurement cycles for each unit area in a virtual volume is measured in a storage apparatus loaded with a hierarchy control function, the storage hierarchy which is proper as a placement destination of data written in each of the unit areas of the virtual volume is determined based on a measurement result, and the data written in a necessary unit area in the virtual volume is relocated to the storage area to which belongs the storage hierarchy that was determined as being proper based on a determination result.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: September 20, 2016
    Assignee: HITACHI, LTD.
    Inventors: Hiromichi Aiura, Hiroshi Koizumi
  • Patent number: 9438482
    Abstract: A server in a distributed environment includes a process that manages incoming client requests and selectively forwards service requests to other servers in the network. The server includes storage in which at least one forwarding queue is established. The server includes code for aggregating service requests in the forwarding queue and then selectively releasing the requests, or some of them, to another server. The queuing mechanism preferably is managed by metadata, which, for example, controls how many service requests may be placed in the queue, how long a given service request may remain in the queue, what action to take in response to a client request if the forwarding queue's capacity is reached, etc. In one embodiment, the server generates an estimate of a current load on an origin server (to which it is sending forwarding requests) and instantiates the forward request queuing when that current load is reached.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: September 6, 2016
    Assignee: Akamai Technologies, Inc.
    Inventors: William E. Weihl, Gene Shekhtman
  • Patent number: 9389866
    Abstract: Disclosed is a method of analysis of a computer program instruction for use in a central processing unit having a decoding unit. The method comprises receiving an address of an instruction to be analysed, fetching said instruction stored at said address, decoding by a decoding unit associated with the central processing unit, the fetched instruction; and returning the results of said decoding of said fetched instruction. The decoded results are returned as a data block stored in memory associated with the central processing unit or in one or more registers of the central processing unit. The decoded results include the type of the instruction and/or the instruction length. The method optionally further comprises analysing the decoded results to determine whether the instruction may be replaced with one of a trap or a break point. Also disclosed is a system and computer program for analysis of a computer program instruction for use in a central processing unit having a decoding unit.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: July 12, 2016
    Assignee: International Business Machines Corporation
    Inventor: David A. Gilbert
  • Patent number: 9298393
    Abstract: An intelligent write command routine improves the operational efficiency of a data storage device (DSD) by avoiding media access of the disk when a logical block address (LBA) and the physical sector are unaligned, thus reducing write time. When a write command is received by the DSD from the host, the intelligent write command routine maintains the read data of the read buffer, instead of clearing the read buffer and performing a read of the target sector on the disk per standard protocol. The intelligent write command copies the necessary adjacent sector data from the read buffer as a data patch to the write buffer to splice around the write data received with the write command. Following each write command, the data written to the disk in the write buffer is copied to the read buffer. The read buffer is maintained with the most current data on the disk and does not need to be flushed unless the LBA of the write command is beyond the data ranges stored in the read buffer.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: March 29, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: KokChoon See, Wesley Chan, CheeSeng Toh, PohGuat Bay, ChweeFern Ee, YongPeng Chng
  • Patent number: 9122401
    Abstract: A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: September 1, 2015
    Assignee: Apple Inc.
    Inventors: Etai Zaltsman, Oren Golov, Ori Moshe Stern, Shai Ojalvo
  • Patent number: 9122413
    Abstract: A method and controller for implementing hardware auto device op initiator in a data storage system, and a design structure on which a subject controller circuit resides are provided. The controller includes an inline hardware engine receiving host commands, and assessing a received command for starting without firmware involvement. The inline hardware engine builds one or more chains of hardware command blocks to perform the received command and starts executing the chain or chains for the received command.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Bakke, Adrian C. Gerhard, Daniel F. Moertl, Rick A. Weckwerth
  • Patent number: 9110878
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 18, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 9098358
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 4, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 9092502
    Abstract: A processing platform integrates ETL (extract, transform, and load), real time stream processing, and “big data” data stores into a high performance analytic system that runs in a public or private cloud. The platform performs real time pre-storage enrichment of data records to form a single comprehensive record usable for analytics, searching and alerting. The platform further supports sharing of components and plug-ins and performs automatic scaling of resources based on real time resource monitoring and analysis.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 28, 2015
    Assignee: Leidos, Inc.
    Inventors: Thomas James Cannaliato, Joshua A. Decker, Matthew William Vahlberg
  • Patent number: 9047311
    Abstract: Approaches for retrieving files from a replicated file system. A component receives, from a requestor, a request for a copy of a data unit. The component identifies a plurality of storage nodes that each stores a complete copy of the data unit. The component sends, to the plurality of storage nodes, an instruction to retrieve a copy of the data unit within a specified period of time. At each storage node receiving an instruction, a determination of whether the copy of the data unit may be retrieved within the specified period of time is made, and if so, the copy of the data unit is provided to the component only if the copy of the data unit was actually retrieved within the specified period. The component provides the first copy of the data unit it receives to the requestor and discards any subsequently received copies of the data unit.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: June 2, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Zvonimir Bandic, Filip Blagojevic, Cyril Guyot, Timothy Tsai, Qingbo Wang
  • Patent number: 9043512
    Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: May 26, 2015
    Assignee: Google Inc.
    Inventor: Arif Merchant
  • Patent number: 9032174
    Abstract: A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventor: Naoki Nishiguchi
  • Patent number: 9021158
    Abstract: A memory device includes a memory array with a plurality of memory elements. Each memory element is configured to store data. The device includes an input/output (I/O) buffer coupled to the memory array. The I/O buffer is configured to receive data from an I/O interface of a memory device controller and write the data to the memory array. The device includes a memory control manager coupled to the memory array. The memory control manager is configured to pause a program operation to the memory array in response to receiving a pause command. The memory control manager is also configured to resume the program operation in response to receiving a resume command.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 28, 2015
    Assignee: SanDisk Technologies, Inc.
    Inventors: Jea Woong Hyun, Mark Brinicombe, Hairong Sun, Hao Zhong, John Strasser, Robert Wood
  • Patent number: 8996759
    Abstract: A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoiju Chung
  • Patent number: 8990456
    Abstract: A block of data may be transferred to memory through a plurality of write operations, where each write operation is preceded by a protocol request and a protocol response. A plurality of protocol requests issued in a first order may elicit a corresponding plurality of protocol responses in a second order, and the write operations may be performed in yet a third order. Chipsets implementing the data write methods are also described and claimed.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: March 24, 2015
    Assignee: Intel Corporation
    Inventors: Raman Nayyar, Kenneth C. Holland
  • Patent number: 8984183
    Abstract: One embodiment of the present invention sets forth a technique for enabling the insertion of generated tasks into a scheduling pipeline of a multiple processor system allows a compute task that is being executed to dynamically generate a dynamic task and notify a scheduling unit of the multiple processor system without intervention by a CPU. A reflected notification signal is generated in response to a write request when data for the dynamic task is written to a queue. Additional reflected notification signals are generated for other events that occur during execution of a compute task, e.g., to invalidate cache entries storing data for the compute task and to enable scheduling of another compute task.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: March 17, 2015
    Assignee: Nvidia Corporation
    Inventors: Timothy John Purcell, Lacky V. Shah, Jerome F. Duluk, Jr., Sean J. Treichler, Karim M. Abdalla, Philip Alexander Cuadra, Brian Pharris
  • Patent number: 8977823
    Abstract: Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a T_STORE operation, comparing a first address associated with the T_STORE operation with a plurality of addresses associated with previous T_STORE operations, wherein the previous T_STORE operations are part of the same transaction as the T_STORE operation and the entries corresponding to the previous T_STORE operations are stored in the merge window; in response to a match between the first address and a second address, associated with a second T_STORE operation, of the plurality of addresses, merging a first entry corresponding to the first T_STORE operation with a second entry corresponding to the second T_STORE operation; and consolidating results associated with the first T_STORE operation with results associated with the second T_STORE operation.
    Type: Grant
    Filed: September 16, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Khary J. ALexander, Christian Jacobi, Gerrit Koch, Martin Recktenwald, Timothy J. Slegel, Hans-Werner Tast
  • Patent number: 8972627
    Abstract: An apparatus, system, and method are disclosed for managing operations for data storage media. An adjustment module interrupts or otherwise adjusts execution of an executing operation on the data storage media. A schedule module executes a pending operation on the data storage media in response to adjusting execution of the executing operation. The pending operation comprises a higher execution priority than the executing operation. The schedule module finishes execution of the executing operation in response to completing execution of the pending operation.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: March 3, 2015
    Assignee: Fusion-io, Inc.
    Inventors: John Strasser, David Flynn, Robert Wood
  • Patent number: 8966139
    Abstract: A memory access request is received from a first lower-level device among a plurality of lower-level devices and, when an address of the memory access request is an address in a given range, the memory access request is converted into a setting request from the upper-level device to a second lower-level device among the lower-level devices, the second lower-level device corresponding to the address of the memory access request.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: February 24, 2015
    Assignee: NEC Corporation
    Inventor: Shigeru Suganuma
  • Patent number: 8959382
    Abstract: A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the peripheral to request a clock signal. The method also includes selectively control communication of the clock signal to the peripheral in response to the request.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: February 17, 2015
    Assignee: Silicon Laboratories Inc.
    Inventor: Gabriel Vogel
  • Patent number: 8959261
    Abstract: A data transfer control device 1061 includes a read pointer update unit 5004 updating a value of a global read pointer RPg with a value of a local read pointer (first local read pointer) RPl1 held by a local read pointer hold unit 5007 when completion of data transfer is recognized and a position, in an order of reading descriptors, of a descriptor D3010a indicated by the local read pointer RPl1 is earlier than positions of descriptors D3010b and D3010c respectively indicated by local read pointers (second local read pointers) RPl2 and RPl3 held by the other data transfer control devices 1062 and 1063.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: February 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yuusaku Ohta, Masaaki Harada, Satoru Kuriki, Satomi Amano, Hideki Taniguchi
  • Patent number: 8959304
    Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 17, 2015
    Assignee: ARM Limited
    Inventors: Dominic Hugo Symes, Ola Hugosson, Donald Felton, Sean Tristram Ellis
  • Patent number: 8959262
    Abstract: A method for accelerating signal transmission in a USB network protocol architecture having a USB server, a processing device and a peripheral device connected to the USB server. The method includes: intercepting request signals sent from the processing device according to the USB network protocol; sending, by the USB server, virtual request signals to the peripheral device so as to cause the peripheral device to generate control signals corresponding to the virtual request signals; receiving, by the USB server, the control signals from the peripheral device, and transmitting, by the USB server, the control signals to the processing device; and matching, by the processing device, the control signals and the intercepted request signals so as to perform operations corresponding to the control signals. Therefore, the present invention eliminates the need to wait for the arrival of request signals before making responses, thereby accelerating the speed of signal transmission.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: February 17, 2015
    Assignee: KCodes Corporation
    Inventors: Tang-En Chiu, Yung-Ju Liang, Ze-Kai Hsiau
  • Patent number: 8949489
    Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Google Inc.
    Inventor: Arif Merchant
  • Publication number: 20150026369
    Abstract: System and methods are provided for managing universal-serial-bus (USB) data transfers. An example system includes a non-transitory computer-readable storage medium including a first scheduling queue for sorting endpoints and a host controller. The host controller is configured to: store a plurality of endpoints for data transfers to the storage medium, an endpoint corresponding to a portion of a USB device; sort the plurality of endpoints in a first order; generate a first transmission data unit including multiple original data packets, the original data packets being allocated to the plurality of endpoints based at least in part on the first order; and transfer the first transmission data unit.
    Type: Application
    Filed: July 16, 2014
    Publication date: January 22, 2015
    Inventors: Xingzhi Wen, Yu Hong, Hefei Zhu, Jeanne Q. Cai, Yan Zhang, Shaori Guo
  • Patent number: 8938589
    Abstract: A disclosed example apparatus includes an interface (702, 726) to receive a request to access a memory (602a) of a memory module (600) and a data store status monitor (730) to determine a status of the memory. The example apparatus also includes a message output subsystem (732) to, when the memory is busy, respond to the request with a negative acknowledgement indicating that the request to access the memory is not grantable.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: January 20, 2015
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Naveen Muralimanohar, Norman Paul Jouppi
  • Patent number: 8930583
    Abstract: A method for controlling data transfer in a serial-ATA system includes using serial-ATA Native Command Queuing (NCQ) to issue a queue of NCQ commands to at least two serial-ATA devices. The commands include a first plurality of commands for a first one of the devices and a second plurality of commands for a second one of the devices. Each of the commands includes a respective port address of one of the at least two devices and a first command identifier identifying a command for the one of the at least two devices. The method further includes receiving a first acknowledgement, which has a port address of a first target device and a second command identifier identifying a first outstanding command for the first target device. Each of the queues of commands is sent to the at least two serial-ATA devices prior to receiving the first acknowledgement.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: January 6, 2015
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Yaniv Shapira, Hrvoje Billic
  • Patent number: 8930593
    Abstract: A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage nodes has a determined maximum latency.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: January 6, 2015
    Assignee: Spansion LLC
    Inventors: Seiji Miura, Roger Dwain Isaac
  • Patent number: 8918557
    Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 23, 2014
    Assignee: LSI Corporation
    Inventor: Brett J. Henning
  • Patent number: 8909764
    Abstract: There is provided a method of scheduling requests from a plurality of services to at least one data storage resource. The method comprises receiving, on a computer system, service requests from said plurality of services. The service requests comprise metadata specifying a service ID and a data size of payload data associated with said service request, and at least some of said service IDs have service throughput metadata specifying a required service throughput associated therewith. The method further includes arranging, in a computer system, said requests into FIFO throttled queues based on said service ID and then setting a deadline for processing of a request in a throttled queue. The deadline is selected in dependence upon the size of the request and the required service throughput associated therewith. Then, the deadline of each throttled queue is monitored and, if a request in a throttled queue has reached or exceeded the deadline the request is processed in a data storage resource.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: December 9, 2014
    Assignee: Xyratex Technology Limited
    Inventor: Ganesan Umanesan
  • Patent number: 8904063
    Abstract: An improved technique for handling events in a multipathing driver employs an event queue and a queue manager that run in the kernel of a computing system. The queue manager receives events raised by the multipathing driver, as well as events raised by software constructs, such as application programs. Records of events are added to the event queue in the order the queue manager receives them. Event records may be consumed chronologically by external software. Preferably, the event queue is sufficiently large to store all events arising out of most predicted fault scenarios. Also, the queue manager is sophisticated and can perform certain diagnostic and analysis tasks without the aid of external software.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: December 2, 2014
    Assignee: EMC Corporation
    Inventors: Harold M. Sandstrom, Tao Tao, Hitesh Trivedi, Robert J. Pellowski
  • Patent number: 8904023
    Abstract: A system and method are disclosed for processing commands to network target devices through a SCSI router in a Fiber Channel network having a plurality of Fiber Channel hosts. The system may be configured to receive a command, and determine that the command requires a transfer of data larger than a threshold size. The system may also be configured to receive a plurality of data blocks associated with the command, store the plurality of data blocks in at least one buffer, and determine if there is an initial amount of data in the at least one buffer. The system may be further configured to forward at least one of the plurality data blocks, and request an additional data block associated with the command.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: December 2, 2014
    Assignee: KIP CR P1 LP
    Inventors: Keith M. Arroyo, Stephen K. Wilson
  • Patent number: 8904062
    Abstract: A method and apparatus of operating a Universal Serial Bus device to determine if a host sending Network Control Model Transfer Blocks (NTBs) is compliant with end of transfer rules for NTBs and to then determine appropriate operations at the device to complete transactions with a non-compliant host.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 2, 2014
    Assignee: MCCI Corporation
    Inventors: Terrill M. Moore, Mats Webjorn
  • Patent number: 8904061
    Abstract: A method is used in managing storage operations in a data storage environment. An I/O request is received a server having a server cache where the server cache contains cached data previously supplied from a storage system in communication with the server. At the storage system, determine if the I/O request can be at least partially satisfied from the cached data.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: December 2, 2014
    Assignee: EMC Corporation
    Inventors: Walter A. O'Brien, III, Thomas E. Linnell, Roy E. Clark, John S. Harwood
  • Patent number: 8898351
    Abstract: In one aspect, a method of compressing data includes splitting an I/O into smaller I/Os based on an I/O throughput. The size of the smaller I/Os are equal or less than a set block size. The method also includes asynchronously compressing the smaller I/Os. In another aspect, an article includes a non-transitory machine-readable medium that stores executable instructions. The instructions cause a machine to split an I/O into smaller I/Os based on an I/O throughput and asynchronously compress the smaller I/Os. The size of the smaller I/Os being equal or less than a set block size. In a further aspect, a system includes circuitry configured to split an I/O into smaller I/Os based on an I/O throughput and asynchronously compress the smaller I/Os. The size of the smaller I/Os being equal or less than a set block size.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 25, 2014
    Assignee: EMC Corporation
    Inventors: Aleksander Gennadevich Povaliaev, Helen S. Raizen
  • Patent number: 8893215
    Abstract: An approach is provided for distributed policy management and enforcement. A policy manager determines one or more domains of an information system. The one or more domains are associated at least in part with respective subsets of one or more resources of the information system. The policy manager also determines one or more respective access policies local to the one or more domains. The one or more respective access policies configured to enable a determination at least in part of access to the respective subsets, the one or more resources, or a combination thereof. At least one of the one or more respective access policies is configured to operate independently of other ones of the one or more respective schemas.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: November 18, 2014
    Assignee: Nokia Corporation
    Inventor: Theodore Robert Burghart
  • Patent number: 8879985
    Abstract: Embodiments of the invention include electronic communications devices having a memory in near field communication device, a memory arbitrator and a host processor. The near field communication (NFC) devices are configured to receive data and drive power from the communication signal. The memory arbitrator is connected to the NFC device and the memory. The memory arbitrator is also configured to access the memory in response to an access request from the NFC device. Additionally, the memory is configurable to be accessed by both the host processor and the NFC device according to embodiments of the present invention.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: November 4, 2014
    Assignee: Broadcom Corporation
    Inventor: Craig Fukuo Ochikubo
  • Patent number: 8880760
    Abstract: In one aspect a memory module storing a plurality of packets is provided. A self organizing heap contains elements associated with each of the packets. The self organizing heap reorders the packets based on packet passing rules. In another aspect, a plurality of elements associated with packets is provided. Each element includes a state machine. The state machine operates in accordance with packet passing rules. The state machine reorders the packets by selective swapping of adjacent elements.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: November 4, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Derek Alan Sherlock, Matthew B Lovell
  • Patent number: 8875140
    Abstract: A method for managing jobs scheduled for execution on a target system in which some jobs may spawn additional jobs scheduled for execution on the target system including intercepting jobs scheduled for execution in the target system, determining whether there is resource sufficiency in the target system for executing jobs, responsive to an affirmative determination of resource sufficiency, releasing previously intercepted jobs for execution in the target system, computing a limit of a number of jobs which can be concurrently scheduled by an external system to the target system, and transmitting the computed limit to the external system.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Giulio Santoli, Fabio Barillari, Fabio Benedetti, Pietro Iannucci
  • Patent number: 8874807
    Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: October 28, 2014
    Assignee: Oracle International Corporation
    Inventors: Sue K. Lee, Vivekananda C. Kolla, Akshay D. Shah, Sumanta Chatterjee, Margaret Susairaj, Juan R. Loaiza, Alexander Tsukerman, Sridhar Subramaniam
  • Patent number: 8868801
    Abstract: A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: October 21, 2014
    Assignee: Altera European Trading Company Limited
    Inventor: Hartvig Ekner
  • Patent number: 8843672
    Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Kazuichi Oe, Kazutaka Ogihara, Yasuo Noguchi, Tatsuo Kumano, Masahisa Tamura, Yoshihiro Tsuchiya, Takashi Watanabe, Toshihiro Ozawa
  • Patent number: 8838782
    Abstract: In a network protocol processing system in which variables of each of TCP transmission processing and TCP reception processing depend on each other, asynchronous parallel processing is realized between a transmission processing block and a reception processing block for updated protocol processing. Specifically, the system includes a high priority queue for transferring control data to be processed with high priority, a low priority queue for control data other than the above control data, and priority control means for distributing the control data to two kinds of queues. When a request for session establishment and the session disconnection of a new TCP session is issued from an application during transmission of TCP data, data related with the session establishment and the session disconnection is notified preferentially through the high priority queue, and other control data is transferred through the low priority queue.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: September 16, 2014
    Assignee: NEC Corporation
    Inventors: Masato Yasuda, Kiyohisa Ichino
  • Patent number: 8819308
    Abstract: A method, computer program product, and computing system for combining a plurality of discrete IO write requests to form a combined IO write request, wherein the plurality of IO write requests define data to be written to a storage network. The combined IO write request is provided to a pseudo multi-write device included within the storage network.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 26, 2014
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Kenneth J. Taylor, Robert P. Ng, Yaron Dar
  • Patent number: 8819303
    Abstract: In one embodiment, a method includes determining a request for a transfer of content where the request is associated with a user device. It is determined if a deferred transfer should be performed. The deferred transfer defers the transfer of the content with a completion by a completion time. The request is stored in a queue where the request is associated with the completion time. The method processes the request from the queue to transfer the content at a start time. The content is transferred by the completion time. The method then adjusts, for a user associated with the user device, a charging parameter for the transfer due to the transfer being deferred.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: August 26, 2014
    Assignee: General Instrument Corporation
    Inventors: Ajith Venugopal, Anita Ramachandran
  • Patent number: 8811893
    Abstract: Embodiments of the invention include electronic communications devices having a memory in near field communication device, a memory arbitrator and a host processor. The near field communication (NFC) devices are configured to receive data and drive power from the communication signal. The memory arbitrator is connected to the NFC device and the memory. The memory arbitrator is also configured to access the memory in response to an access request from the NFC device. Additionally, the memory is configurable to be accessed by both the host processor and the NFC device according to embodiments of the present invention.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: August 19, 2014
    Assignee: Broadcom Corporation
    Inventor: Craig Fukuo Ochikubo