Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.

Abstract: A computer program product is provided for performing input/output (I/O) processing at a host computer system. The computer program product is configured to perform: generating an address control structure for each of a plurality of consecutive data transfer requests specified by an I/O operation, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW) that includes an Offset field indicating a relative order of a data transfer request; generating and storing in local channel memory at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests and including an Expected Offset field indicating a relative order of an expected data transfer request; receiving a transfer request from the network interface and comparing the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order.

Abstract: A storage processor of a data storage system includes a data relocation task scheduler that provides system limit control on the execution of data relocation requests. The data relocation task scheduler also provides fairness and concurrency limit enforcement by scheduling relocation requests from different provisioning domains, such as storage pools, in a fair manner. For example, the data relocation task scheduler includes stackable sets of pending task queues that store incoming data relocation requests. The data relocation task scheduler applies an iteration scheme to remove data relocation requests from the pending task queues thereby providing scheduling fairness among the queues and among the different provisioning domains within the data storage system.

Abstract: A unique system and method for ordering commands may reduce disc access latency while giving preference to pending commands. The method and system involves giving preference to pending commands in a set of priority queues. The method and system involve identifying a pending command and processing other non-pending commands in route to the pending command if performance will not be penalized in doing so. The method and system include a list of command node references referring to a list of sorted command nodes that are to be scheduled for processing.

Abstract: A machine implemented method and system for communication between a computing system and an adapter is provided. An application from among a plurality of applications sends a message to the adapter with a value V. The adapter queues the message at the first storage location and writes the value V at a second storage location after the message is successfully queued at the first storage location. To determine if the message was successfully queued, the computing system reads the written value at the second storage location and compares it to the value V that was sent with the message.

Abstract: An example method involves: providing a user-interface having a plurality of input regions, where one of the input regions is a home region, where each of the input regions is associated with a primary character from a set of primary characters, and where at least one of the input regions is associated with a subset of secondary characters from a set of secondary characters; receiving data indicating an input-movement from the home region to a second input region from the plurality of input regions that is associated with a subset of secondary characters; receiving data indicating an input-movement from the second input region to the home region; selecting, in response to the input-movement from the second input region to the home region, a character from the subset of secondary characters associated with the second input region; and causing the selected character to be displayed on a graphical display.

Abstract: The correspondence of the respective ports and the respective microprocessors is dynamically changed based on the load of the respective microprocessors. When an open port MP including a plurality of ports connected to a host computer receives an I/O request from the host computer via a port, it specifies an MPPK to become the transfer destination of the I/O request, and transfers the I/O request to the specified MPPK. Each MP belonging to the MPPK that received the I/O request selects either an exclusive mode where a single MP exclusively performs the processing of the I/O request, or a share mode where two or more MPs share the processing of the I/O request. Each MP selects the exclusive mode or the share mode corresponding to when load information concerning the ports shows a low load or high load condition, respectively, and executes the I/O processing accordingly.

Abstract: To facilitate retransmission of a data file that has been deleted from a server, a data processing device includes a first storage section in which a management table is stored. The management table includes a list of communication histories with respect to communications with each of the servers. Each communication history indicates a data file transmitted to the server. The device further includes a second storage section storing data files transmitted to the servers. A control section is provided for judging, when a communication section is in communication with a server, whether or not a data file which has already been transmitted to the server needs to be retransmitted and retransmit the data file to the server upon retrieving the data file from the second storage section when judgment is made so that retransmission of the data file is needed.

Abstract: The present disclosure describes, among other things, a method. The method may include receiving, by a computing device, a first request for a workflow from an external system. The method may include determining, by the computing device, a priority level associated with the workflow. The method may include determining, by the computing device, a queue in a priority stack, wherein the queue is associated with the priority level. The method may include adding, by the computing device, the first request for the workflow to the queue.

Abstract: The present invention relates to managing I/O requests in a storage system. By dynamically changing the scheduling parameters to achieve optimal turn around time for I/O requests pending for processing at a component in the storage system. The scheduling parameters are changed based on a feedback mechanism. The turn around time of the I/O request are calculated as the ratio of I/O request processing rate and the average number of I/O requests in the component.

Abstract: A system and method are provided that involve a host computing machine and an SR IOV storage adapter in which the host machine hosts a virtual machine having a guest operating system (guest) coupled for direct passthrough IOV data path and also hosts a virtualization intermediary; a guest operating system (guest) and a virtualization intermediary exchange information concerning IO completions through a shared memory space; the guest writes information to a shared memory space that is indicative of whether an IO completion queue has reached a fill level since the most recently dispatched interrupt at which it is unsafe to coalesce an interrupt; the virtualization intermediary writes information to the shared memory space that is indicative of the interrupt most recently delivered to the guest; the virtualization intermediary reads the information written by the guest to the shared memory space that is indicative of whether an IO completion queue has reached a fill level since the most recently dispatched inter

Abstract: The present invention provides an improved method and system of improving the efficiency, and ensuring the integrity, of a data transfer in a serverless backup, or third party copy, system having one or more physical storage devices. The present invention provides improvements to the processing of serverless copy, or EXTENDED COPY, commands, and transfers of data associated with such commands. These improvements increase the speed at which such commands are executed and completed, and increase the capabilities of copy managers in serverless backup systems. The improvements also make better use of the storage devices involved in the data backup process. Certain aspects of the invention allow for execution of data segments of any size, and providing a compiler for generating input/output actions.

Abstract: A system and method are disclosed for processing commands to network target devices through a SCSI router in a Fiber Channel network having a plurality of Fiber Channel hosts. The system and method are implemented in the SCSI router and include receiving a command from one of the plurality of Fiber Channel hosts and, if the command is for a transfer of data larger than a threshold size, streaming the data to the target device. If a preset size memory block is free, a data block is requested from the Fiber Channel host that issued the command. Otherwise, the method of this invention waits to request the data block until the preset size memory block is free. The SCSI router receives the data block and stores the data block in a FIFO queue. The method of this invention repeats until an initial number of data blocks are stored in the FIFO queue. The command and the first data block received are forwarded to the network target device.

Abstract: When a virtual tape of the main storage system is updated, journal data is created. The journal data is transmitted to the disaster recovery storage system asynchronously with the timing at which the write data is received. The journal data includes a marker to notify of the start of updating and a marker to notify of the completion of updating. The disaster recovery storage system prohibits the use of the copy destination data during the period from start of updating until completion of updating, and permits referencing the copy destination data during other periods.

Abstract: One embodiment of the present invention sets forth a technique for processing cache misses resulting from a request received from one of the multiple clients of an L1 cache. The L1 cache services multiple clients with diverse latency and bandwidth requirements, including at least one client whose requests cannot be stalled. The L1 cache includes storage to buffer pending requests for caches misses. When an entry is available to store a pending request, a request causing a cache miss is accepted. When the data for a read request becomes available, the cache instructs the client to resubmit the read request to receive the data. When an entry is not available to store a pending request, a request causing a cache miss is deferred and the cache provides the client with status information that is used to determine when the request should be resubmitted.

Abstract: A computer readable storage medium comprising software instructions, which when executed by a processor, perform a method, the method including obtaining a first non-optional Input/Output (I/O) request from an I/O queue, determining that a second non-optional I/O request and an optional I/O request are adjacent to the first non-optional I/O request, generating a new data payload using a first data payload from the first non-optional I/O request, a second data payload for the second non-optional I/O request, and a third data payload corresponding to the optional I/O request, wherein the third data payload is interposed between the first data payload and the second data payload, generating a new non-optional I/O request comprising the new data payload, and issuing the new non-optional I/O request to a storage pool, wherein the new data payload is written to a contiguous storage location in the storage pool.

Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.

Abstract: Input and output (I/O) operations performed by a data storage device are managed dynamically to balance aspects such as throughput and latency. Sequential read and write requests are sent to a data storage device whereby the corresponding operations are performed without time delay due to extra disk revolutions. In order to minimize latency, particularly for read operations, random read and write requests are held in a queue upstream of an I/O controller of the data storage device until the buffer of the data storage device is empty. The queued requests can be reordered when a higher priority request is received, improving the overall latency for specific requests. An I/O scheduler of a data server is still able to use any appropriate algorithm to order I/O requests, such as by prioritizing reads over writes as long as the writes do not back up in the I/O queue beyond a certain threshold.

Abstract: methods and systems for monitoring data activity may include various operations, including, but not limited to: modifying a value of at least one counter in response to one or more input/output requests directed to at least one data storage region during a first time interval; storing a first cumulative value of the counter modified in response to one or more input/output requests directed to at least one data storage region during the first time interval following the expiration of the first time interval; modifying a value of at least one counter in response to one or more requests directed to the at least one data storage region during a second time interval; storing a second cumulative value of the counter modified in response to one or more requests directed to the at least one data storage region during the second time interval following the expiration of the second time interval; and computing at least one activity index for the at least one data storage region from at least the first cumulative value

Abstract: In a method of processing requests for hardware in a multi-core system including a first processor core and a second processor core according to example embodiments, the first processor core receives a plurality of hardware input/output requests from a plurality of applications, manages the plurality of hardware input/output requests using a hardware input/output list, and responds to the plurality of hardware input/output requests in a non-blocking manner. The second processor core sequentially processes the plurality of hardware input/output requests included in the hardware input/output list.

Abstract: This invention enables resources included in a storage system to be effectively used. In a storage system 1 including a host computer 3, a first storage apparatus 10 that receives a data I/O request from the host computer 3, the second storage apparatus 10, and including a function of external attachment processing for managing the entity of a first logical volume of the first storage apparatus 10 in a second logical volume of the second storage apparatus 10, when a problem occurs in performance of the first storage apparatus 10, the external attachment processing is released, while external attachment release processing is performed in which path for accessing from the host computer 3 the second logical volume is switched to allow direct access from the host computer 3 to the second logical volume. When the problem in performance of the first storage apparatus 10 is solved, path switching is performed again to resume the external attachment processing.

Abstract: A network device may include a line interface to receive and transmit data units, a memory including instructions associated with a user space and a kernel space that are executable by a processor, the user space including a first-in-first-out (FIFO) region for storing the data units and corresponding metadata, where the kernel space writes the data unit and the corresponding metadata to the FIFO region, the metadata including a next pointer that identifies a memory address for storing the next data unit in the FIFO region, a user space process determines whether to transmit or drop the data unit, the user space process being a single process, and the user space transmits the data unit from the FIFO region without involving the kernel space when the user space process issues a command.

Abstract: In one aspect, a method of compressing data includes splitting an I/O into smaller I/Os based on a throughput of I/Os in a queue, a smaller I/O is equal or smaller than a block size. The method also includes storing the smaller I/Os in the queue. The method further includes asynchronously compressing the smaller I/Os.

Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.

Abstract: A computer-implemented method for managing access to a peripheral device is described. A request is received from an operating system to interface with a peripheral device. The operating system requesting to interface with the peripheral device is analyzed. A determination is made as to whether the operating system is a host operating system based on the analysis of the operating system. The operating system is prevented from interfacing with the peripheral device if the operating system is a host operating system.

Abstract: Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virtual servers, and an IO controller that controls an IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.

Abstract: The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set.

Abstract: An optical disc drive is provided, mainly comprising a buffer, a processor and a driving module for accessing an optical disc. The optical disc drive receives a plurality of write commands. Each write command comprises a data block and a destination address. The buffer buffers data blocks to be recorded to the optical disc with corresponding write commands in either a random mode or a sequential mode. The processor schedules a recording operation based on the write commands, and selectively switches the buffer to the random mode or to the sequential mode based on arrangements of data blocks buffered in the buffer. The driving module is controlled by the processor to perform the recording operation, whereby the data blocks are recorded to the optical disc when a start recording condition is met. Specifically, the start recording condition varies with the random or sequential modes.

Abstract: Methods and apparatuses for delaying execution of input/output (I/O) requests for solid state drives are contemplated. Some embodiments comprise receiving I/O requests for a solid state drive and calculating amounts of time based on characteristics of the requests, such as differences of the logical block addresses (LBAs) of the requests. The embodiments may then delay responses by the solid state drive for the requests. Calculating the amounts of time and delaying the responses by the amounts of time may allow the solid state drives to emulate the responses of various types of hard disk drives. Some embodiments comprise an apparatus for delaying execution of the I/O requests for solid state drives. The apparatuses may have numerous modules, such as a request receiver to receive the I/O requests, a calculation module to calculate the amounts of delay times, and a delay module to delay the responses of the I/O requests.

Abstract: A universal serial bus (USB) communication system, the communication system including: (a) at least one asynchronous transmission queue manager configured to queue, in at least one asynchronous transmission queue, information for asynchronous transmission through at least one asynchronous pipe; (b) at least one guaranteed transmission queue manager configured to insert into at least one queue information for transmission through a dedicated pipe utilized by the communication system; wherein the at least one queue is selected from the at least one asynchronous transmission queue, at least one periodic transmission queue and at least one additional queue; and (c) a transmitter configured to transmit information through the at least one asynchronous pipe and the dedicated pipe, wherein the transmitting through the dedicated pipe is prioritized over the transmitting at the at least one asynchronous pipe, wherein the transmitting at the dedicated pipe is irrespective of time in which information for transmission a

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: A memory access request is received from a first lower-level device among a plurality of lower-level devices and, when an address of the memory access request is an address in a given range, the memory access request is converted into a setting request from the upper-level device to a second lower-level device among the lower-level devices, the second lower-level device corresponding to the address of the memory access request.

Abstract: A system and method for coordinating control setting with respect to an automated input/output (I/O) processor. A state machine having a transition algorithm can be configured in association with a storage controller in order to permit multiple entities to safely transmit an I/O request to an I/O device. Specific combinations of control bits associated with a fast path engine can be determined by identifying different modes with respect to the behavior of the fast path engine. Each mode can be assigned as a state with respect to the state machine. An I/O path exception and error condition that can cause transitions between the states can be determined and the transitions can be assigned from one state to another state. A generic logic template can then be configured to govern the transitions with respect to the state machine. The logic can be executed when an event occurs in order to trigger multiple state transition and/or modifications with respect to the hardware control bits of the fast path engine.

Abstract: Mechanisms provide hosts such as servers and mobile devices with access to virtualized I/O resources including virtual Host Bus Adapters (vHBAs) and virtual Network Interface Cards (vNICs) over a wireless I/O interconnect. Host applications access virtualized I/O resources using virtual device drivers that communicate with virtualized I/O resources on an I/O director using a reliable communication protocol running over a wireless network. I/O data is throttled if necessary based on wireless network considerations.

Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on a one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.

Abstract: Re-sequencing commands and data between a master and slave device utilizing parallel processing is disclosed. When utilizing parallel processing while reading and writing data, there is a chance that the data will be read or written in an improper order, given the time delays associated with different slave devices and the processing time associated with various commands. Therefore, to retain the speed and improved performance of parallel processing while maintaining data coherency, the instructions and data are re-sequenced and processed in the proper order, and the returned data are re-sequenced and returned to the processor in the proper order.

Abstract: A method for binding input/output (I/O) objects to nodes includes an subsystem receiving a request to use an I/O device from a process, determining a first resource to service the request, generating a first I/O object corresponding to the first resource, wherein the first I/O object is unbound, and sending the first I/O object to a Non-Uniform Memory Access (NUMA) I/O Framework. The method further includes the NUMA I/O Framework selecting a first NUMA node of a plurality of NUMA nodes, to which to bind the first I/O object and binding the first I/O object to the first NUMA node. The method further includes servicing the request by processing, on the first NUMA node, the first resource corresponding to the first I/O object.

Abstract: Disclosed is a technique for flow control. It is detected that a work request is being transferred to an in-memory structure. A maximum limit is compared with a number of work requests stored in the in-memory structure. If the number of work requests stored in the in-memory structure equals the maximum limit, a notification is sent that indicates that additional work requests are not to be sent.

Abstract: In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands.

Abstract: A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.

Abstract: The correspondence of the respective ports and the respective microprocessors is dynamically changed based on the load of the respective microprocessors. When an open port MP including a plurality of ports connected to a host computer receives an I/O request from the host computer via a port, it specifies an MPPK to become the transfer destination of the I/O request, and transfers the I/O request to the specified MPPK. Each MP belonging to the MPPK that received the I/O request selects either an exclusive mode where a single MP exclusively performs the processing of the I/O request, or a share mode where two or more MPs share the processing of the I/O request. Each MP selects the exclusive mode or the share mode corresponding to when load information concerning the ports shows a low load or high load condition, respectively, and executes the I/O processing accordingly.

Abstract: An apparatus, system, and method are disclosed for enqueue prioritization. The apparatus for enqueue prioritization is provided with a plurality of modules configured to functionally execute the necessary steps of anticipating a need to access a computing resource, generating a dummy request, the dummy request configured to hold a place for an actual request in a queue of requests to access the computing resource, and generating an actual request to access the computing resource, wherein the actual request is configured to replace the dummy request in the queue. These modules in the described embodiments include a forecast module, a dummy generator, and a request generator.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.

Abstract: A computer readable storage medium comprising software instructions, which when executed by a processor, perform a method, the method including obtaining a first non-optional Input/Output (I/O) request from an I/O queue, determining that a second non-optional I/O request and an optional I/O request are adjacent to the first non-optional I/O request, generating a new data payload using a first data payload from the first non-optional I/O request, a second data payload for the second non-optional I/O request, and a third data payload corresponding to the optional I/O request, wherein the third data payload is interposed between the first data payload and the second data payload, generating a new non-optional I/O request comprising the new data payload, and issuing the new non-optional I/O request to a storage pool, wherein the new data payload is written to a contiguous storage location in the storage pool.

Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.

Abstract: Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The I/O device driver determines whether the pending queue is sorted and responds to a determination that the pending queue is sorted, determining if queued I/O requests exceed the maximum ordered queue length. Responding to a determination that the pending queue exceeds the maximum ordered queue length, the I/O device driver adds the I/O request based on a high pointer, and points the high pointer to the I/O request.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: A method, apparatus and program product are provided for moving data from a source memory zone to a target memory zone of a computer. A source host operating system invokes a synchronous multiple move command for SBAL output buffers with a common target zone. The machine firmware identifies and validates the target argument of the first SBAL, validates the target zone state, moves the data associated with the first SBAL to the target zone; and then iteratively moves the data associated with the remaining SBALs to the target zone.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.