Abstract: There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access from outside. The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register.

Abstract: An article of manufacture, an apparatus, and a method for providing extended measurement word data from a control unit to a channel subsystem of an I/O processing system are disclosed. The article of manufacture includes at least one computer usable medium having computer readable program code logic. The computer readable program code logic performs a method including receiving a command message from the channel subsystem at the control unit, and initiating a timing calculation sequence of a plurality of time values in response to receiving the command message at the control unit. The computer readable program code logic also populates extended measurement word data at the control unit including the plurality of time values, and outputs the extended measurement word data from the control unit to the channel subsystem.

Abstract: A USB port transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one USB transmission from among multiple scheduled USB transmissions based on their types. A selector selects one of the arbiters to select the one USB transmission from among the multiple scheduled USB transmissions. A programmable storage element controls the selector to select the one arbiter. In one embodiment, at least a first arbiter prioritizes header/data packets higher than link commands, and at least a second arbiter prioritizes link commands higher than header/data packets. In one embodiment, at least one arbiter prioritizes flow control and power management link commands higher than header/data packets. In one embodiment, at least a first of the arbiters prioritizes USB LGO_Ux link commands higher than USB LAU/LXU link commands, and at least a second arbiter prioritizes USB LAU/LXU link commands higher than USB LGO_Ux link commands.

Abstract: In described embodiments, a method of generating an identifier for a disk includes the steps of requesting an ASCII identification string for the disk and generating a padded string by processing the ASCII identification string into a predetermined number of bytes. The padded string is divided into portions and an encoded value is generated for each portion. The two or more encoded values for the portions are combined into a candidate value compatible with a World-Wide Name (“WWN”). The candidate value is compared to a list of previously generated candidate values and if the candidate value differs from the values in the list, the candidate value is included in the list of generated values and the candidate value is provided as the system-wide name for the disk.

Abstract: A system for implementing wireless control between apparatuses. In at least one scenario, an apparatus may, after an event (e.g., receiving wireless communication), create a wireless message based on the event, and may then send the wireless message to a peripheral apparatus. The peripheral apparatus may utilize some or all of the message data to formulate and display a user interface. Inputs (e.g., soft-coded or hardware based buttons) in the peripheral device may be actuated in accordance with the user interface, which may result in a response message being sent to the apparatus. The response message may, in turn, trigger functionality in the apparatus.

Abstract: A memory controller is unaware of device types (DTs) of a plurality (N) of series-connected memory devices in an interconnection configuration. Possible DTs include, e.g., random access memories and Flash memories. First, the memory controller sends a specific DT (“don't care”) and an initial number of binary code to the first device of the interconnection configuration and the binary code is propagated through the devices. Each device performs a “+1” calculation regardless of the DT. The last device provides the memory controller with Nד+1” from which the memory controller can obtain the number N of devices in the interconnection configuration. Thereafter, the memory controller sends a search number (SN) of binary code and a search DT for DT matching that propagate through the devices. Each device performs DT match determination of “previous match”, “present match” and “don't care match”. Based on the match determination, the SN and search DT are or not modified.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: An open network system transacts communication over on open network. The system includes an input device associated with a non-standard I/O device for obtaining communication transaction data and a client program for generating a communication transaction message in an extended open network protocol with the communication transaction data.

Abstract: A CEC on the fly modification function, operated by a manipulating switch including at least three HDMI-CEC ports, enables the manipulating switch to receive a CEC block comprising a CEC address according to the initiator's HDMI-CEC network; modify on the fly the CEC address in the received CEC block to match the follower's HDMI-CEC network view; and supply the modified CEC block to one or more devices.

Abstract: A method, system and computer program product are disclosed for routing data packet in a computing system comprising a multidimensional torus compute node network including a multitude of compute nodes, and an I/O node network including a plurality of I/O nodes. In one embodiment, the method comprises assigning to each of the data packets a destination address identifying one of the compute nodes; providing each of the data packets with a toio value; routing the data packets through the compute node network to the destination addresses of the data packets; and when each of the data packets reaches the destination address assigned to said each data packet, routing said each data packet to one of the I/O nodes if the toio value of said each data packet is a specified value. In one embodiment, each of the data packets is also provided with an ioreturn value used to route the data packets through the compute node network.

Abstract: It is desired to reduce the danger of leakage of data stored in a logical storage device. A storage system has a detection unit and a security processing unit. The detection unit detects a system change, during which it is not possible to perform I/O for a first logical storage device, among a plurality of logical storage devices in the storage system. And the security processing unit takes this type of system change as the opportunity for performing security processing, i.e. formatting or shredding, upon the first logical storage device.

Abstract: A computer system includes a shared I/O device including functions providing access to device local memory space, and a plurality of roots coupled to the shared I/O device via a switch fabric. A first root assigns a first address in a first root memory space to a first function. A second root assigns a second address in a second root memory space to a second function. The switch fabric maps the first root memory space to a first portion of device local memory space and the second root memory space to a second portion of device local memory space. Subsequently, the switch receives a data transaction request from the first root targeted to the first address, translates the first address to a corresponding location in the first portion of the device local memory space based on the mapping, and routes the data transaction request to the I/O device.

Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.

Abstract: A method and system for performing serial data communication between a main device and an external module connected to the main device. The data communication system and method include a main device, and an external module connected to the main device and communicating data with the main device. The external module transmits its identification information to the main device before the external module and the main device communicate the data between each other, and the main device receives the identification information from the external module, confirms its connection to the external module, and transmits an identification information confirmation signal to the external module.

Abstract: Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write request directed to a memory address and generates a plurality of graphics device addresses based on the memory address of the write request when the memory address is within a particular range of broadcast addresses. An offset may be applied to a reference address in each address range associated with one of the graphics devices when generating the plurality of graphics device addresses. The write request is forwarded to each graphics device of the plurality of graphics devices associated with one of the generated graphics device addresses.

Abstract: An embodiment of the present invention includes a communication system configured to conform to SATA or SAS standards and causing communication between one or more hosts and a SATA device. The communication system includes a communication device adapted to generate debug information incorporated through one or more links using an analyzer to identify problems associated with the communication system.

Abstract: The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value.

Abstract: A personal computer system and an operation method thereof for multiple outputs are provided. In the present method, input data generated by each of a plurality of input devices of the personal computer system are received. According to an identification information of each of the input devices, each of the input data is respectively transmitted to one of a plurality of application programs. After that, each of the application programs separately generates an output result according to the received input data and displays the output result on a corresponding application program interface, wherein all of the application program interfaces displaying the corresponding output results are in one and the same display screen of the personal computer system.

Abstract: The system according to the present invention for data transfer between microcomputer devices contains a standard protocol controller, a generally known ethernet controller, for example, as a coupling device instead of the known multipart RAM. Instead of a parallel data connection, the microcomputer devices are coupled to one another via a standardized, serial data connection, for example, ethernet. Using functions of ethernet switches already known, a number of microcomputer devices in the system may be increased.

Abstract: The present invention is a method and a system for dynamic mapping of a fiber channel loop ID in an ALPA loop. Based on reserved address information for the fiber channel system and a number of select ID bits for a slot ID, a dynamic drive mapping table is created. A unique address may be assigned to each drive and each controller in the ALPA loop. The created drive mapping table may be stored on logic decoding circuitry of an adaptor card coupled to each disk drive in the ALPA loop. When fiber channel loop ID signals are sent from a backplane, the fiber channel loop ID signals are translated into seven bits within an ALPA address range based on the dynamic drive mapping table. The converted signals may be sent to the disk drive coupled the adaptor card at boot up time.

Abstract: A data storage device includes one or more electrical contacts and one or more data paths through the electrical contacts. The one or more electrical contacts enable bits to be transferred into and out of the data storage device via the one or more data paths. The data storage device also includes a memory that stores an indication of a number of the one or more data paths. The data storage device is configured to provide the indication via at least one of the one or more data paths while the data storage device is operatively coupled to a host device to indicate to the host device the number of the one or more data paths.

Abstract: Registering memory space within a data processing system is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. At least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.

Abstract: A modular computer system formed by connecting a processing module having a processor mounted thereon and a plurality of I/O modules in a stacked form via connectors, where differing ones of the plurality of I/O modules being differing types of I/O modules from one another, which operate with mutually differing types of bus-layout configurations. In accordance with the association of I/O modules with identification information, for each differing type of I/O module stacked via the connectors, said processing module selects from differing preset bus-layout configurations and device drivers from a memory, to dynamically reconfigure the reconfigurable generic bus for accessing the differing type of I/O module.

Abstract: An object is to improve reliability and availability of a storage system. A single service processor (SVP 20) manages a plurality of storage apparatuses 10. The storage apparatus 10 includes a channel substrate 11, a drive substrate 13, a cache memory 14, and a processor substrate 12 as well as a sub-service processor (SSVP 18) that has an environment monitor unit 181 acquiring operation state information and a service processor monitoring unit (SVP monitoring unit 182) monitoring a SVP 20 and that is coupled to the processor substrate 12. The SVP 20 includes a communication control unit 203 coupled via a communication network 52 to the respective processor substrates 12 of the storage apparatuses 10 and a power control unit 205 coupled via a communication line to the SSVP 18 and powering off or on the SVP 20 according to a control signal sent from the SVP monitoring unit 182 via the communication line 55.

Abstract: Watch (1) including time display means (8; 10) covered by a crystal (4). This watch includes an interface device for controlling a computer cursor. It forms a contactless watch-mouse. For this purpose, a plurality of touch sensitive sensors are arranged so that their sensitive pads (16) are supported at least partially by the crystal (4). The sensitive pads are arranged in particular in the shape of a matrix extending over most of the crystal (4). The click function is performed using a push-button (14) associated with electric contactor or by a pressure sensor or by a touch sensitive sensor provided for this purpose.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: A storage system configured to associate a virtual port 810 to a plurality of physical ports 800. In response to commands from computers, the storage system 100 manages relation between physical ports and virtual ports and relation between virtual port and volumes by performing processes such as creating a virtual port, assigning LUs to a virtual port, moving a virtual port between physical ports and deleting a virtual port. The storage system also maintains/calculates statistics information for ports and displays the information for each virtual port.

Abstract: An electronic device and data control method are provided. The electronic device includes a connector which is connected to an external storage medium storing media data therein; an identification unit which identifies a storage identifier (ID) of the external storage medium connected to the connector; and a controller which performs a media function corresponding to the media data stored in the external storage medium whose storage ID is identified by the identification unit.

Abstract: A device control apparatus in a video image display system including a plurality of connected devices. The apparatus includes an obtaining unit which obtains a logical address of a first device connected to the device control apparatus as a control object, a specifying unit which specifies the device type of the first device if the obtained logical address of the first device is not a logical address according to the device type, a selection unit which selects a second device which is connected to the device control apparatus and is of the same device type as the first device, and a control unit which controls a logical address assigned to the selected second device according to the device type thereof so that the first device obtains a logical address.

Abstract: A power management system may comprise two or more POL regulators configured to transmit and receive data over a shared bus according to either a proprietary or a common bus protocol. Each POL regulator may be identified by a unique address that is part of an address group, and may be configured via pin strapping to be able to perform a variety of power management functions. Any one of the POL regulators within the address group may become a bus master and transmit information to the shared bus by addressing itself. The other POL regulators in the address group may monitor the shared bus for events, and may respond to the transmitted information according to their address, their configuration, and the transmitted information. The response may include the POL regulators performing one or more power management functions, including adjusting their respective output voltages.

Abstract: A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are redistributed among the extended set so as to cause some logical addresses to be transferred from the devices in the initial set to the additional device. There is substantially no transfer of the logical addresses among the initial set. If a surplus device is removed from the initial set, forming a depleted set, the logical addresses oldie surplus device are redistributed among the depleted set. There is substantially no transfer of the logical addresses among the depleted set. In both cases the balanced access is maintained.

Abstract: Particular embodiments include a system and method to enable a user-controlled proxy system or coordinating computer to automatically or semi-automatically communicate with multiple devices, determine the currently operating software contents and versions for each device, and to automatically or semi-automatically upgrade each device with updated software without requiring user intervention. The software may include communication, operating system or application-specific program codes that improve a given device's designed function.

Abstract: A computer program product, apparatus, and method are provided for determining a state of an input/output (I/O) operation in an I/O processing system. A request from a channel subsystem is received at a control unit for performing the I/O operation. After a predetermined amount of time passes without the I/O operation completing, an interrogation request is received from the channel subsystem at the control unit for determining the state of the I/O operation. A response is sent from the control unit to the channel subsystem indicating the state of the I/O operation in response to the interrogation request. The response also includes information regarding a state of an I/O device executing the I/O operation and information indicating a state of the control unit controlling the I/O device executing the I/O operation.

Abstract: A first storage system is connected to a second storage system, and an external device within the first storage system is provided to a host as a device of the second storage system. The second storage system includes a cache control section having cache adaptors, each controlling a disk and a cache, a protocol conversion section including protocol adaptors that switch requests from the host to appropriate ones of the cache adaptors, a management adaptor, and an internal network that mutually connects the cache adaptors, the protocol adaptors and the management adaptor. The first storage system being connected to any of the protocol adaptors is connected to the second storage system. The second storage system executes a processing for the external device by the cache control section, or connects to the first storage system through the protocol conversion section without the cache control section executing processing for the external device.

Abstract: A network apparatus is provided that is capable of requiring a reservation for an access right to a peripheral device that is not yet connected to the network apparatus from one of the terminals on a network. A server (network apparatus) may receive a reservation command and a sender identifier (ID) from one of the terminals on the network that requests to reserve an access right for a peripheral device that is not yet connected to the server. In a case where a new connection of a peripheral device is detected, the server allows the terminal identified by the sender ID that accompanied the reservation command to access the peripheral device. While the reservation is established, access to the detected peripheral device from senders other than the identified terminal is rejected.

Abstract: According to one embodiment, an electronic apparatus comprises a first communication module, a terminal, a second communication module and an address management module. The first communication module is configured to communicate with at least one device in accordance with a first communication scheme. The second communication module is configured to communicate with at least one device in accordance with a second communication scheme via the terminal. Lastly, the address management module is configured to assign a first physical address value to said at least one device via the second communication module based on an identification (ID) value of the apparatus, wherein the first physical address value is information associated with the second communication scheme and the ID value is information associated with the first communication scheme and is assigned based on an assignment scheme defined by the first communication scheme.

Abstract: Systems, methods and computer program products for providing indirect data addressing at an I/O subsystem of an I/O processing system. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a control word for an I/O operation. The control word includes an indirect data address for data associated with the I/O operation. The indirect data address includes a starting location of a list of storage addresses that collectively specify the data, the list spans two or more non-contiguous storage locations. Data is gathered responsive to the list. The gathered data is transmitted to a control unit in the I/O processing system.

Abstract: A system capable of efficiently transferring a command set for controlling an image forming apparatus to the image forming apparatus from a host apparatus. A command separate/storage unit separates an image forming command set into a context command set and an object command set, and allocates both command sets in a main memory device. A command read instruction transmission unit transmits a command read instruction having a transfer size and a storage address of each of the allocated context command set and object command set, to the memory access controller. The memory access controller compares the storage address of the context command set included in the received command read instruction with a previous storage address, and reads the context command set from the main memory device only when both storage addresses differ from each other.

Abstract: The present invention provides an apparatus and method for a robust and configurable mobile computer architecture with navigation computational capabilities. The present invention further provides a bus network which allows for an efficient and durable Input/Output (I/O) management system. The I/O management system has configurable connections to allow for modular addition, expansion, or replacement of navigation, crash detection, and communication line replacement units (LRUs). Additional I/O device connections allow several modes of input into the computational system. The present invention is a single, self-contained unit and provides an accessible user interface to the computer system.

Abstract: An input/output memory management unit (IOMMU) configured to control requests by an I/O device to a system memory includes control logic that may perform a two-level guest translation to translate an address associated with an I/O device-generated request using translation data stored in the system memory. The translation data includes a device table having a number of entries. The control logic may select the device table entry for a given request by the using a device identifier that corresponds to the I/O device that generates the request. The translation data may also include a first set of I/O page tables including a set of guest page tables and a set of nested page tables.

Abstract: A system for managing a circular buffer memory includes a number of data writers, a number of data readers, a circular buffer memory; and logic configured to form a number of counters, form a number of temporary variables from the counters, and allow the data writers and the data readers to simultaneously access locations in the circular buffer memory determined by the temporary variables.

Abstract: This invention increases the design efficiency of an upper layer such as a job control means. To accomplish this, an image processing apparatus having a plurality of types of external interfaces (a USB and LAN) different in protocol has an external interface adaptor 203 which dynamically allocates external interfaces as objects of processing to lower layer IDs within a predetermined range, and a job controller 202 which controls execution of various types of jobs by using the lower layer IDs, and a value which the lower layer ID can take is constant regardless of the type of external interface.

Abstract: A method of controlling a peripheral device includes generating, in a host processor, a control message for transmission to the peripheral device, and calculating a signature for the control message. The control message and the signature are written to an address in a system memory of the host processor, and the peripheral device is notified of the address, so as to cause the device to read the control message and the signature from the system memory.

Abstract: The invention relates to an input/output channel control block that comprises a number of successive input/output modules. The first is a control master module and the subsequent ones are expansion slave modules. Each expansion slave module comprises a processing logic unit as well as respective first signal port and a respective equal number of second signal ports and an equal number of third signal ports which are arranged at identical positions of each expansion slave module. The first signal port is connected to the processing logic unit, to which at least one fourth signal port for connecting an input/output bus terminal subscriber belongs, and a respective second signal port is connected to a third signal port. The control master module likewise possesses a number of third signal ports and a control logic unit for data exchange with a data bus and for targeted driving of the signal ports.

Abstract: Structure, Structure, system, apparatus, method, and computer program for managing and configuring a computer storage system by mapping the topology and connectivity of all servers, storage devices, and storage device controllers within the storage subsystem, based on unique identifiers especially World Wide Number (WWN) identifiers. The method includes querying a server to identify host bus adapters coupled to the server, querying each host bus adapter to identify attached device controllers, issuing a read connection information command to the device controller and returning the connection results including identifying devices coupled to the device controller, and storing the returned connection results in a data structure.

Abstract: A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.

Abstract: Provided are a method, system, and article of manufacture, wherein a persistent storage is maintained in a device receiving unit that is capable of receiving one or more devices. The device receiving unit receives a device that includes device specific information that identifies the device. The device is interfaced with the device receiving unit. The persistent storage is updated with the device specific information that identifies the device, in response to the interfacing of the device with the device receiving unit.

Abstract: A modular distributed I/O system that allows one or more modules of an island to be omitted without requiring reconfiguration of the system and a method for auto-addressing the system. The island includes a network interface module that is operably connected to a user interface. The user interface allows a user to indicate for each of the nodes of the island whether the node has an I/O module physically present or not physically present. This allows a constant process image in a system where the process image is dependent upon node ID's of modules, and modules are assigned addresses (i.e., ID's) automatically without using unique markers or signatures.

Abstract: At least one first numbered phy of a first SAS expander is grouped with at least one second numbered phy of a second SAS expander physically separate from the first SAS expander into at least one common SAS wide port. An identical SAS address is assigned to the first SAS expander and the second SAS expander for operating the first SAS expander and the second SAS expander to behave and respond as a single, cohesive SAS expander. The first SAS expander is directly connected to the second SAS expander for inter-expander communications.