Abstract: A wireless Universal Serial Bus (USB) host that optimizes the data transfer between the Wireless Host Controller Driver (WHCD) and the Wireless Host Controller (WHC). The data transfer between the WHCD and the WHC is optimized by reducing the overhead of data fragmentation. Higher performance without sacrificing memory and computation power is achieved with the optimization of the data transfer.

Abstract: A method implemented by a non-volatile memory (NVM) controller comprising obtaining a NVM express (NVMe) command comprising a namespace identifier (NSID) from a host memory via a peripheral component interconnect express (PCIe) function, determining a mapping between the PCIe function and a namespace identified by the NSID based on a data structure stored in a PCIe memory address space, and accessing the namespace based on the mapping between the PCIe function and the namespace.

Abstract: Disclosure is related to a universal driving method and a system for a variety of peripherals. For solving the problem in a hardware manufacturer required to provide many versions of drivers and proprietary programs for different host systems and operating systems, the universal driving method allows the host system drives its peripherals via a scripting language. In accordance with the embodiment of the invention, the host system may recognize and connect to a peripheral device via an address while the peripheral device is linked to the host system. After that, a channel is established between the peripheral device and the host system. The scripting language is then used to generate an operating interface for the peripheral device. Users may therefore access the peripheral device through the interface.

Abstract: An information synchronization method includes acquiring declaration information of a first local area network device that is in a first local area network. The declaration information includes a private address of the first local area network device in the first local area network. The private address of the first local area network device is mapped into a corresponding external address according to a preset mapping relation between private addresses and external addresses. A notification message carrying the external address of the first local area network device is sent to a second local area network, so as to enable the second local area network to store the external address of the first local area network device and notify a state of the first local area network device to a second local area network device in the second local area network.

Abstract: A method of identifying devices on a bus and an apparatus are provided. A method of identifying devices on a bus comprises pooling a plurality of devices connected to a bus, each of the plurality of devices not having uniquely assigned to it a respective unique device identifier (ID) of the bus, selecting, after the pooling, one of the plurality of devices using at least one selection criteria, the at least one selection criteria identifying the one of the plurality of devices uniquely among all of the plurality of devices, and reassigning a unique device ID of the bus to the selected one of the plurality of devices uniquely. An apparatus is configured to carry out the method of identifying devices on a bus.

Abstract: There is provided a data processing method of a client terminal that communicates with a server, including: receiving a data request message for requesting data of a USB device connected to the client terminal, from the server, the data request message including information about a size of data that is to be read from the USB device; acquiring data corresponding to the size of data included in the data request message, from the USB device; deciding a size of data that is able to be additionally transmitted from the USB device, according to operation states of other USB devices connected to the client terminal; and transmitting a data transmission completion message to the server, wherein the data transmission completion message includes information about the size of data that is able to be additionally transmitted, and the data acquired from the USB device.

Abstract: A system and method for clients, a control module, and storage modules to participate in a unifed address space in order to and read and write data efficiently using direct-memory access. The method for reading data includes determining a first location in a first memory to write a first copy of the data, a second location in a second memory to write a second copy of the data, where the first memory is located in a first storage module including a first persistent storage and the second memory is located in a second storage module including a second persistent storage. The method further includes programming a direct memory access engine to read the data from the client memory and issue a first write request to a multicast address, where the first location, the second location, and a third location are associated with the multicast address.

Abstract: Systems and methods for configuring contacts of a first connector includes detecting mating of a second connector with the first connector and in response to the detection, sending a command over one of the contacts and waiting for a response to the command. If a valid response to the command is received, the system determines the orientation of the second connector. The response also includes configuration information for contacts in the second connector. The system then configures some of the other contacts of the first connector based on the determined orientation and configuration information of the contacts of the second connector.

Abstract: A method for operating a bus system, in particular a CAN bus is disclosed. Several stations can be connected to the bus system. A transmitted message has an identifier, wherein a certain identifier (for example, IDENT) always may be used only by a single station. Each of the stations compares the identifier of a transmitted message with the identifiers the station itself uses (for example, IDENT2). An error message is produced in the event of a match.

Abstract: An automation device comprising a first functional unit, a second functional unit, a first network connection for connection to a first data network and a bus master unit for connecting a peripheral component. The first functional unit includes a first interface unit that is assigned a first network address, and the second functional unit includes a second interface unit that is assigned a second network address. A partitioning device can be used to logically partition an address space of the peripheral component, and a first address space can be directly assigned, as a partitioned part of the address space, to a superordinate computation unit that can be connected through the first network connection.

Abstract: A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit.

Abstract: According to one embodiment, a non-transitory medium, a controller, a memory, an extension function section, and an extension register. The controller controls the non-transitory medium. The memory which is serving as a work area is connected to the controller. The extension function section is controlled by the controller. The extension register which is provided on the memory is provided with a certain block length capable of defining an extension function of the extension function section. The controller processes a first command to write header data of a command to operate the extension function section to the extension function section through the extension register, and a second command to read header data of a response from the extension function section through the extension register.

Abstract: System, apparatus, and methods for dynamically managing logical path resources are provided. The logical path resources are managed by adding, removing, and establishing logic paths based on specified priority schemes associated with the logical path resources. Information associated with the logical path resources is updated in a logical path resource table.

Abstract: This invention is a system and a method for operating a storage server that provides read or write access to a data in a data network using a new architecture. The method of processing I/Os in response to a request by a client of the storage server executes one or more services communicated by a policy engine. The I/Os received from the application are tagged and catalogued to create co-related I/O patterns. The policy engine is then updated with the results of processing the I/Os after executing services on those I/Os.

Abstract: An image processing apparatus includes: an acquiring unit that acquires a display request including a first external apparatus identification information and screen identification information; a storage unit storing external apparatus screen information; an update unit updating the first external apparatus screen information whenever the display request is acquired; a determining unit determining a polling interval for a first external apparatus on the basis of the stored external apparatus screen information; and a transmitting unit transmitting, to the first external apparatus, screen data which includes information of the determined polling interval, wherein, when a second external apparatus identification information item corresponding to the same screen identification information as that in the display request is stored in the storage unit, the determining unit determines the polling interval for the first external apparatus to be less than that for a second external apparatus indicated by the second ext

Abstract: An image processing apparatus includes: a receiving unit that receives a screen update request including identification information of a screen and a job start request including identification information of a job; a database that defines a relationship between the identification information of the screen, the identification information of the job, and a polling interval corresponding to a degree of association between the screen and the job; a determining unit that determines the polling interval corresponding to the degree of association between the screen and the job on the basis of the identification information of the screen and the identification information of the job received by the receiving unit and the database; and a transmitting unit that incorporates information of the determined polling interval into screen data and transmits the incorporated screen data to an external apparatus that outputs the screen update request.

Abstract: A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the SMP virtual connecting unit is provided within the firmware.

Abstract: A device includes an interface configured to receive an indication of a second device on a network, and a processor configured to determine if the indication is one of an expected set of indications and generate a permanent node address for assignment to the second device if the indication is one of an expected set of indications. The permanent node address places the second device into an active mode as a permanent node addressed device. The processor is further configured to receive at least one device parameter from the permanent node addressed device, determine if the at least one device parameter matches an expected device parameter for the permanent node addressed device, and generate a second permanent node address for assignment to the device if the at least one device parameter matches the expected device parameter for the permanent node addressed device.

Abstract: A storage device includes a control unit that carries out a communication process with a host device that is connected via a bus; a storage unit into which data from the host device is written; and a storage control unit that controls access to the storage unit. The control unit returns an acknowledgment to the host device in the case where the control u has received acknowledgment return request information broadcasted from the host device to a plurality of storage devices connected to the bus after the end of a period in which data is written into the plurality of storage devices by the host device, and the data has been successfully written into the storage unit of the storage device to which the control unit belongs.

Abstract: An electronic device includes an HDMI output terminal connectable to one of a first HDMI input terminal and a second HDMI input terminal of an external device, the first and second HDMI input terminals having a first physical address and a second physical address assigned thereto, respectively, a detection means for detecting a connection of the HDMI output terminal to one of the first and second HDMI input terminals, a read means for reading the first physical address from the external device when the connection of the HDMI output terminal to the first HDMI input terminal is detected and reading the second physical address from the external device when the connection of the HDMI output terminal to the second HDMI input terminal is detected, and a transmission means for transmitting one of the read first and second physical addresses to the external device via the HDMI output terminal.

Abstract: Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer.

Abstract: This document discusses, among other things, an identification (ID) detection module configured to identify a first ID code in a first detect period within a first attach period and to identify a second ID code in a second detect period within the first attach period.

Abstract: In a method for allocating SAS addresses to SAS expander devices in an SAS expander system, the SAS expander system includes a master SAS expander device, a slave SAS expander device and an EEPROM. The method defines an address parameter for specifying a master SAS address for the master SAS expander device and specifying a slave SAS address for the slave SAS expander device, and obtains an original SAS address from the EEPROM when the original SAS address is identical to either the master SAS address or the slave SAS address. The method adds the address parameter to the original SAS address to generate a first SAS address and allocates the first SAS address to the master SAS expander device. The method adds the address parameter to the first SAS address to generate a second SAS address, and allocates the second SAS address to the slave SAS expander device.

Abstract: One embodiment is a storage device that has multiple physical ports receiving input/outputs (I/Os) from a host computer. Each of the ports presents plural virtual ports using N_Port ID Virtualization (NPIV) to prioritize the I/Os.

Abstract: An electronic Input/Output Interface and device abstraction system used in gaming machines includes: a game central processing unit (game “CPU”); an intelligent input/output controller board (“IOCB”); an Industry Standard Architecture PC bus (“ISA” bus); and a framed message transport protocol. The IOCB facilitates communications between the game CPU and virtual device services, which are peripheral devices associated with the gaming system. The game CPU communicates to gaming peripherals by sending virtual device messages across the ISA bus to the IOCB. The IOCB routes virtual device messages to appropriate virtual device services. Virtual device services are responsible for handling specific hardware, and include virtual device drivers on the game CPU that communicate with virtual devices on the IOCB. Use of the IOCB and the high speed interface enables the game CPU to use more of its available functions for controlling gaming functions rather than one operation of its associated peripheral devices.

Abstract: A method includes addressing, through a command generated by an application executing on a computing platform, one or more device(s) in storage communication with the computing platform based on an appropriate communication link. The method also includes accessing, based on the addressing, a physical register of the one or more device(s) through an appropriate interface therein. Further, the method includes obtaining statistical information associated with a performance of the one or more device(s) at the computing platform through the access of the physical register.

Abstract: Methods and apparatus for enabling FCS and zoning operations in an enhanced SAS expander. Features and aspects hereof provide for enhanced logic within a SAS expander to detect receipt of an SAF in a zoning capable SAS expander and to modify the SAF to correct the zone group identifier and associated CRC to enable switching among a plurality of established connection (as provided by FCS enhancement) while maintaining accurate zoning information.

Abstract: A baseboard management controller is disclosed. The baseboard management controller adapted to monitor a host comprises a baseboard management control module, a memory controller and a video graphic array (VGA) module. The VGA module comprises a video controller, a decoder, a select circuit and a mapping circuit. The decoder receives a transaction signal from a first local bus and decodes a first address signal contained in the transaction signal. The select circuit selectively transfers data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal. The mapping circuit being connected with the decoder maps the first address signal and a second address signal to a third address signal, updates the first address signal and transfers an updated transaction signal.

Abstract: A semiconductor device correctly switches endian modes regardless of the current endian mode of an interface. The semiconductor device includes a switching circuit and a first register. The switching circuit switches an interface to be used in big endian or little endian mode. The first register holds control data of the switching circuit. The switching circuit sets the interface in little endian mode when first predetermined control information is supplied to the first register, and sets the interface in big endian mode when second predetermined control information is supplied to the first register. The control information can be correctly inputted without being influenced by the endian setting status.

Abstract: A system for generating a computing system specific value comprising, a computing system not comprising any specialized hardware to generate a device specific value, a software product tangibly embodied in a machine-readable medium, comprising instructions operable to cause computing system to perform operations comprising: generating a digital value which is substantially dependent on manufacturing variation among like devices of computing system.

Abstract: A system and method of connecting a computer to a peripheral of another computer. An example system includes a processor connected to a network and to the one and the other computers through the network. The processor executes web service software which establishes a discovery service for receiving a peripheral connection request from application software of the one computer and peripheral management software which receives information from the other computer through the web service software about the peripherals of the other computer.

Abstract: Virtual Functions (VFs) 602-1 to 602-N of an I/O device are separately allocated to a plurality of computers 1-1 to 1-N. In an address swap table 506, a root domain that is an address space of the computer 1 and mapping information of an I/O domain that is an address space unique to the I/O device 6 are registered. Mapping is set with the VFs 602-1 to 602-N as units. When accessing the VFs 602-1 to 602-N of the I/O device 6 to which each of the computers 1-1 to 1-N is allocated, an I/O packet transfer unit 701 checks the address swap table 506 to swap source/destination addresses recorded in packet headers.

Abstract: A device comprises circuitry and a transceiver. In operation, the device is configured to cause the transceiver to: receive a first message from another device to support at least one aspect of attachment of the device and the another device, send, to the another device, a second message after the first message and prior to attachment, receive, from the another device, a third message that is sent after the second message and prior to attachment, send, to the another device, a fourth message after the third message and prior to attachment, receive, from the another device, a fifth message that is sent after the fourth message and prior to attachment, and send, directly to the another device, data utilizing at least one channel for data transfer utilizing a second one of the addresses for identification in association with the device on the shared wireless communication network.

Abstract: Embodiments of the present invention relate to a method and an apparatus for obtaining equipment identification information, where the method includes: detecting, by using a first GPIO port, a first discharging duration for a capacitor to discharge through a resistor to be tested; detecting, by using a second GPIO port, a second discharging duration for the capacitor to discharge through a fixed value resistor; and obtaining a resistance of the resistor to be tested according to the first discharging duration, the second discharging duration, and a resistance of the fixed value resistor. The embodiments of the present invention are capable of increasing identification efficiency of the GPIO port.

Abstract: A method for operating a portable electronic device includes receiving an identifier associated with an accessory connected to the portable electronic device. The portable electronic device then determines a set of actions to be performed for that accessory based on the received identifier. The portable electronic device then performs the determined actions.

Abstract: A system and method for dynamically migrating stash transactions include first and second processing cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), and an operating system (OS) scheduler. The first core executes a first thread associated with a frame manager. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers to indicate scheduling-out and scheduling-in of the first thread from the first core and to the second core. The STMMU uses the pre-empt notifiers to enable dynamic stash transaction migration.

Abstract: An electrical device includes a plurality of apparatus connected with a daisy chain connection through a communication line so that the apparatus communicate with each other through the communication line; and a control unit connected to one of the apparatus at an end stage thereof so that the control unit is configured to communicate with the one of the apparatus. The apparatus includes an address setting unit for setting a specific number to an address of the apparatus according to an address setting command when the apparatus receives address setting data including an address addition instruction as the address setting command for adding the specific number to the address of the apparatus. The apparatus further includes an address setting data transmission control unit for outputting the address setting data to a later stage apparatus when the address setting unit sets the specific value to the address of the apparatus.

Abstract: A robotic tape library which queues two or more move instructions is described. Generally, the robotic system receives a first move instruction which commands a first robot to move a first tape cartridge from a shelf to a first tape drive to be loaded therein. Though the first move has not actually taken place, the library replies to the host computer that the first tape drive has been loaded with the first tape cartridge, at least to an acceptable level of engagement, at which point, the first move instruction is queued. After receiving a second move instruction from the host to move a second tape cartridge from the shelf to a second tape drive, the library reorganizes and physically carries out the move instructions with potentially different hardware in a preferred order.

Abstract: Systems and methods for providing a differentiation of two identical slave devices on a same I2C bus without any hardware (e.g. additional ID pins) or software overhead are disclosed. Each identical slave device is connected to the SDA/SCL lanes by interchanging its SDA/SCL ports. It is up to the slave device to detect its signal connectivity to the SDA/SCL lanes of the I2C bus. The slave devices detect the signal connectivity by interpreting the I2C transfer in normal and interchanged connectivity.

Abstract: One exemplary method of assigning addresses in two or more address spaces with address fields of different lengths comprises defining address types, assigning a value to first bits at the high ends of the address fields to identify a first said address type, assigning second bits at the low ends of the address fields to identify addresses of the first said address type, and inserting different numbers of additional bits between the first bits and the second bits in the two or more address spaces.

Abstract: A system, method, and computer-readable medium are disclosed for entitling the implementation of a feature associated with a device after it is manufactured. A feature entitlement management system receives a device's unique identifier, which is then processed to determine which features associated with the device are available for implementation. Once determined, the available features are provided to the user of the device, who in turn selects a feature for implementation. A feature entitlement is then generated by performing late binding entitlement operations to associate the selected feature's corresponding entitlement data with the device's unique identifier. The resulting feature entitlement is then is processed to implement the selected feature.

Abstract: A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.

Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

Abstract: An integrated circuit includes a first configuration terminal, a second configuration terminal, a bus terminal, and an auto addressing circuit coupled to the first and second configuration terminals. The auto addressing circuit is responsive to a data pattern received at the first configuration terminal to assign a node address to an operational circuit, and subsequently to couple the first configuration terminal to the second configuration terminal. The integrated circuit is subsequently responsive to the node address when the node address is received.

Abstract: An input/output (I/O) device includes a host interface for connection to a host device having a memory, and a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Processing circuitry is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory. At least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges.

Abstract: A method for implementing an addressing scheme may include mapping a digital peripheral function to one or more contiguous configurable blocks in an array of configurable blocks; and assigning a memory address from a plurality of memory addresses to at least one register of each of the one or more contiguous configurable blocks based on an access mode width of the digital peripheral function and a width of each of the one or more contiguous configurable blocks.

Abstract: A method of generating length parameters, comprising the steps of reading a data stream from a host, detecting a particular field of the data stream, and calculating a variable based on a length parameter of a first list to be transferred. The data stream may comprise a plurality of definitions. The method may also comprise the step of selecting one of the list definitions. One of the list definitions may be used to generate a length parameter used in a second list in response to (i) the particular field of the data stream and (ii) the length parameter of the first list.

Abstract: A virtualization processing method and apparatuses, and a computer system are provided. Where a computing node includes: a hardware layer, a Host running on the hardware layer, and at least one virtual machine (VM) running on the Host, the hardware layer includes an I/O device, several corresponding virtual function (VF) devices are virtualized from the I/O device, the Host has several VF software instances, the several VF software instances and the several VF devices are in one-to-one correspondence; the Host further has a back-end instance (BE) of an I/O virtual device having the same type with the I/O device, the VM has a front-end instance (FE) of the I/O virtual device; the BE in the Host is bound with an idle VF software instance. The solutions of the embodiments of the present invention are beneficial to optimization of the performance and compatibility of a virtualization system.

Abstract: A data processing apparatus and method have a processor for executing instructions, and a prefetch unit for prefetching instructions from memory prior to sending those instructions to the processor for execution. A branch target cache structure has a plurality of entries, where the cache structure comprises an initial branch target cache having a first number of entries and a promoted entry branch target cache having a second number of entries. During lookup operation, both the initial entry branch target cache and the promoted entry branch target cache are accessed in parallel. For a branch instruction executed by the processor that does not currently have a corresponding entry in the branch target cache structure, allocation circuitry performs an initial allocation operation to allocate one of the entries in the initial entry branch target cache for storing the branch instruction information for that branch instruction.

Abstract: The present application is directed towards systems and methods for systems and methods for handling real-time streaming protocol sessions by an intermediary multi-core system. When a multi-core intermediary receives a setup request for a real-time streaming protocol session, the intermediary processes and forwards the request to a server providing the streaming media. The server sets up an RTSP session and transmits a session identification to the multi-core intermediary. A core of the intermediary receives the transmitted session identification and determines an owner core of the session, based on a hash of the session identification. The core transmits the session information to the determined owner core, which selects two consecutive ports on which to establish listening services. The owner core then notifies all other cores to establish listening services on the same consecutive ports, such that any core that receives an RTSP control message from a client can handle it properly.