Abstract: A system for discovering devices on a common bus without direct communication. Each device on the bus has a unique identification. One of the devices or a computer may be a master or a host. The host may broadcast a request asking every device with an identification value in a particular range to respond. If no device or one device exists on the bus in this particular range, then there is no or one response, respectively. If multiple devices exist within the range, then multiple responses may be received by the host. In a case of multiple responses, the host may re-transmit its request to one or more half ranges. If multiple responses are again received, then the host may again re-transmit its request where the half range or ranges are again split in half. This approach of half-range reduction may be repeated until no more collisions occur.

Abstract: Emulating HDMI-CEC devices, sub networks, or messages, including selecting the properties of an HDMI-CEC device to be emulated from at least two devices representing different functionalities, and initiating spoofed CEC messages. One of the methods includes selecting an initiator CEC logical address to emulate, and initiating a CEC message comprising the selected CEC logical address that is not unregistered logical address and does not represent a functionality of the device that actually initiated the CEC message.

Abstract: A computer implemented method includes receiving a request to access a configuration space that is associated with a virtual function. The request may include a configuration space address and a root complex identifier. The computer implemented method may include identifying a root complex based on the root complex identifier. The computer implemented method may also include selecting a slot that is associated with the root complex. The slot may be capable of coupling a hardware input/output adapter to the root complex. The computer implemented method may further include determining whether the configuration space address is associated with the selected slot. The computer implemented method may include accessing the configuration space using an access mechanism in response to determining that the configuration space address is associated with the selected slot.

Abstract: An electronic component (10a, 10b), with assignment of an address to the component, comprises a first terminal (A10a) for the application of a first signal (SCL) and a second signal (SDA) different from the first signal, and a second terminal (A10b), different from the first terminal, for the application of the first signal (SCL) and the second signal (SDA). Depending on the external connection of the first and second terminals (A10a, A10b), the component is assigned an address by means of which the component is addressable.

Abstract: A method of pipelining hardware accelerators of a computing system includes associating hardware addresses to at least one processing unit (PU) or at least one logical partition (LPAR) of the computing system, receiving a work request for an associated hardware accelerator address, and queuing the work request for a hardware accelerator using the associated hardware accelerator address.

Abstract: A programmable network component for use in a plurality of network devices with a shared architecture, where the programmable network component includes an interface with an external processing unit to provide management interface control between the external processing unit and a network device. The programmable network component also includes a plurality of internal busses each of which is coupled to the programmable network component and to at least one network component. The programmable network component further includes a plurality of external buses each of which is coupled to the programmable network component and to at least one physical interface. The programmable network component is configured to support a plurality of protocols for communication with a plurality of physical interface components and comprises a plurality of programmable registers for determining the status of the plurality of physical interfaces.

Abstract: A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of PEs each having an associated PE number, where each of the plurality of PEs including one or more requesters each having a respective requester ID. An I/O host bridge, responsive to receiving an I/O message including a requester ID and an address, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index and validates the address by reference to the accessed entry in the second data structure. The I/O host bridge, responsive to successful validation, provides a service indicated by the I/O message.

Abstract: Field bus system, comprising (i) at least one field bus module with a connection unit for the connection to a network, wherein a control unit can be connected to the network and the at least one field bus module can be addressed in the network, and with a plurality of ports for the connection of field devices, in particular sensors and/or actuators, and (ii) at least one address connector which has a non-volatile memory for an address, wherein the at least one field bus module has an address port for the at least one address connector and the address of the at least one address connector in the network is communicated to the field bus module via its connection.

Abstract: In general, techniques are described for performing work conserving packet scheduling in network devices. For example, a network device comprising queues that store packets and a control unit may implement these techniques. The control unit stores data defining hierarchically-ordered nodes, which include leaf nodes from which one or more of the queues depend. The control unit executes first and second dequeue operations concurrently to traverse the hierarchically-ordered nodes and schedule processing of packets stored to the queues. During execution, the first dequeue operation masks at least one of the selected ones of the leaf nodes from which one of the queues depends based on scheduling data stored by the control unit. The scheduling data indicates valid child node counts in some instances. The masking occurs to exclude the node from consideration by the second dequeue operation concurrently executing with the first dequeue operation, which may preserve work in certain instances.

Abstract: A memory controller is unaware of device types (DTs) of a plurality (N) of series-connected memory devices in an interconnection configuration. Possible DTs include, e.g., random access memories and Flash memories. First, the memory controller sends a specific DT (“don't care”) and an initial number of binary code to the first device of the interconnection configuration and the binary code is propagated through the devices. Each device performs a “+1” calculation regardless of the DT. The last device provides the memory controller with Nד+1” from which the memory controller can obtain the number N of devices in the interconnection configuration. Thereafter, the memory controller sends a search number (SN) of binary code and a search DT for DT matching that propagate through the devices. Each device performs DT match determination of “previous match”, “present match” and “don't care match”. Based on the match determination, the SN and search DT are or not modified.

Abstract: A method for reducing address space in a shared virtualized I/O device includes allocating hardware resources including variable resources and permanent resources, to one or more functions. The method also includes allocating address space for an I/O mapping of the resources in a system memory, and assigning a respective portion of that address space for each function. The method further includes assigning space within each respective portion for variable resources available for allocation to the function to which the respective portion is assigned, and further assigning space within each respective portion for a set of permanent resources that have been allocated to the function to which the respective portion is assigned. The method further includes providing a translation table having a plurality of entries, and storing within each entry of the translation table, a different internal address of a permanent resource that has been allocated to a particular function.

Abstract: A method and system of providing physical port security in a digital data network is disclosed. The system keeps bit maps of allowed physical output ports for each physical network connection. The map of allowed ports can be different for different source addresses connected to the device. When digital data, such as an IP packet, is received, the appropriate physical port security bit map is retrieved and a logical AND is done on the physical port bit map generated by the destination information. The resulting bit map is used to determine which physical ports the data is routed to, blocking any requested destinations that are not appropriate destinations based on the port security bit map.

Abstract: A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.

Abstract: A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.

Abstract: An electronic device includes a set of programming terminals for receiving corresponding programming signals, and assignment circuitry for assigning an address to the electronic device according to the programming signals. The assignment circuitry includes circuitry for providing a set of comparison signals, with at least part of the comparison signals that is variable during a non-zero comparison interval, and comparison circuitry for determining the address according to a comparison between the programming signals and the comparison signals during the comparison interval.

Abstract: The driving of an audio device that supports two or more audio modes is accomplished by associating a first physical device object of an audio device with a first device identifier, the first physical device object representing a first audio mode enumerated by a bus enumerator; associating a second physical device object of an audio device with a second device identifier, the second physical device object representing a second audio mode enumerated by the bus enumerator; and if the first device identifier matches the second device identifier, enabling a coupled kernel streaming audio interface compatible with both the first physical device object and the second physical device object.

Abstract: Architecture that allows programmatic association of devices to sessions and redirects input to the desired session. When the solution is active, input from the devices is not realized by the standard operating system input stack, thereby allowing even reserved key sequences such as Ctrl-Alt-Del to be intercepted and redirected to a desired session. Moreover, in addition to redirecting input to a specific session, the architecture facilitates the filtering of input from unwanted/unmapped devices, the interception and filtering or redirection of reserved key sequences such as Ctrl-Alt-Del, and the maintenance of input state for each session.

Abstract: An address management method and a device thereof are provided. The address management method includes checking by a device whether logical addresses are currently being used by external devices; and setting by the device a non-use logical address as a logical address of the device regardless of the type of the device, if the device determines that the non-use logical address exists. Therefore, a device may use all logical addresses regardless of its device type, and may also have a logical address even though all logical addresses corresponding to its device type are currently being used.

Abstract: A spoofing module that mimics remote computer resources to optimize system responsiveness and avoid expiration of intentional and unintentional timeouts in extended computer systems. The invention is capable of appearing to the host system and selectively responding to the host system as if it were the actual hardware. The invention includes a throttling mechanism to prevent data over-run.

Abstract: An object is to improve reliability and availability of a storage system. A single service processor (SVP 20) manages a plurality of storage apparatuses 10. The storage apparatus 10 includes a channel substrate 11, a drive substrate 13, a cache memory 14, and a processor substrate 12 as well as a sub-service processor (SSVP 18) that has an environment monitor unit 181 acquiring operation state information and a service processor monitoring unit (SVP monitoring unit 182) monitoring a SVP 20 and that is coupled to the processor substrate 12. The SVP 20 includes a communication control unit 203 coupled via a communication network 52 to the respective processor substrates 12 of the storage apparatuses 10 and a power control unit 205 coupled via a communication line to the SSVP 18 and powering off or on the SVP 20 according to a control signal sent from the SVP monitoring unit 182 via the communication line 55.

Abstract: Disclosed is a method and a SAS controller device that abstract access from one or more virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller (i.e., unique for the SAS controller such that other replicates/clones on other virtual ports have a different SAS address).

Abstract: A command is issued to a first data storage system for addressing a set of data and at least one of a first referral response including a referral to at least a second data storage system or at least a first subset of the set of data and the first referral response including the referral to the at least the second data storage system. The at least one of a first referral response is accessed. A command is issued to the second data storage system for addressing the set of data and a second referral response including a referral to at least one of the first data storage system and a third data storage system, the second data storage system including at least a second subset of the set of data. The second subset of the set of data and the second referral response including the referral to the at least one of the first data storage system or the third data storage system is accessed.

Abstract: An address management method and a device thereof are provided. The address management method includes determining by a device whether all logical addresses corresponding to a type of the device are currently being used by external devices; setting by the device a non-use logical address as a logical address of the device, if it is determined that one of the logical addresses is currently not in use; and setting by the device a predetermined logical address as a logical address of the device, if it is determined that all the logical addresses are currently being used. Therefore, logical addresses may be allocated to a device even if all logical addresses corresponding the type of the device are currently being used.

Abstract: In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.

Abstract: Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.

Abstract: A method, storage medium, and system for a managed audio bell/intercom including a controller and audio devices connected by an industry standardized network, wherein the controller contains logic to distribute action via the network to the audio devices.

Abstract: Electronic equipment such as hosts, hubs, and devices may be connected to form a network. The electronic equipment may include audio connectors such as four-contact plugs and jacks. Cables may be used to interconnect the audio connectors and thereby form communications paths between pieces of equipment in the network. The equipment may include uplink and downlink data interfaces having associated uplink interface addresses and downlink interface addresses. Devices and hybrid equipment may contain endpoints that are associated with components such as speakers and microphones. Equipment may also include input-output devices such as buttons that are used in gathering user input such as button press data. When a network is formed, a host can broadcast downstream data including its downlink interface address. Downstream equipment can assign uplink interface addresses, downlink interface addresses, and endpoint addresses using received downlink interface address information.

Abstract: A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.

Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a first processor configured to exchange data with a first data length format, a second processor configured to exchange data with a second data length format and a shared memory configured to store data, the shared memory being shared by the first and second processors, the shared memory further configured to receive a read command from at least one of the first and second processors and to output data in response to the read command based on which of the first and second data length formats is used by the processor issuing the read command.

Abstract: Subject matter disclosed herein relates to techniques involving transitioning serial data into a serial parallel interface.

Abstract: The described embodiments provide a system for accessing values for configuration space registers (CSRs). This system includes a CSR data storage mechanism with an address input and a CSR data output. The CSR data storage mechanism includes a memory containing a number of memory locations for storing the true or actual values for CSRs for functions for corresponding devices. In these embodiments, the memory locations are divided into at least one shared region and at least one unique region. In these embodiments, in response to receiving an address for a memory location on the address input, the CSR data storage mechanism accesses the value for the CSR in the memory location in a corresponding shared region or unique region.

Abstract: A programmable processing device comprises a plurality of universal digital blocks (UDBs) in a UDB linear array. Each register in each UDB is associated with a plurality of memory addresses, where each memory address is from each of the different memory address spaces associated with different access mode widths of different digital peripheral functions. A digital peripheral function of an access mode width is mapped to one or more contiguous UDBs starting with a first UDB in the UDB linear array. Based on the access mode width, one of the associated memory addresses is chosen for the first UDB.

Abstract: A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are redistributed among the extended set so as to cause some logical addresses to be transferred from the devices in the initial set to the additional device. There is substantially no transfer of the logical addresses among the initial set. If a surplus device is removed from the initial set, forming a depleted set, the logical addresses of the surplus device are redistributed among the depleted set. There is substantially no transfer of the logical addresses among the depleted set. In both cases the balanced access is maintained.

Abstract: A state of an input/output (I/O) operation in an I/O processing system is determined. A request for performing the I/O operation is received from an I/O operating system at a channel subsystem and forwarded to a control unit controlling an I/O device for executing the I/O operation. After a predetermined amount of time passes without receiving indication from the control unit that the I/O operation is completed, an interrogation request is received at the channel subsystem from the I/O operating system for determining the state of the I/O operation. An interrogation command is sent from the channel subsystem to the control unit. A response is received from the control unit, the response indicates a state of the I/O device executing the I/O operation, a state of the control unit controlling the I/O device executing the I/O operation, and the state of the I/O operation being executed.

Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.

Abstract: The present invention relates to a data processing system based on a multithreaded operating system. The data processing system comprises at least one processor (PROC) for processing data based on multiple threads, at least one controller unit (CU) for controlling the communication between said at least one processor (PROC) and an external peripheral device (PD) connected to said at least one controller unit (CU). Said at least one controller unit (CU) comprises at least one buffer memory (BM) for buffering data from said peripheral device (PD) connected to said at least one controller unit (CU), and at least one memory managing unit (MMU) for managing the access to said at least one buffer memory (BM) by mapping said at least one buffer memory (BM) into N banks (C0-C3) each with a dedicated prefetch register (Addr.0-Addr.3). At least one of said multiple threads (T0-T3) is mapped to one of said N banks (C0-C3) and its dedicated prefetch register (Addr.0-Addr.3).

Abstract: A semiconductor device correctly switches endian modes regardless of the current endian mode of an interface. The semiconductor device includes a switching circuit and a first register. The switching circuit switches an interface to be used in big endian or little endian mode. The first register holds control data of the switching circuit. The switching circuit sets the interface in little endian mode when first predetermined control information is supplied to the first register, and sets the interface in big endian mode when second predetermined control information is supplied to the first register. The control information can be correctly inputted without being influenced by the endian setting status.

Abstract: An interface to transfer data between a host processor and an external coprocessor is provided. The interface may operate in several write modes, in which in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. The interface can perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. The interface can include buffers to store read and write operations and clock gates to selectively gate off clock signals provided to the buffers to synchronize transfer of data into and out of the buffers. A selectable priority scheme can be modified to select between priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.

Abstract: A fluid infusion system as described herein includes a number of local “body network” devices, such as an infusion pump, a handheld monitor or controller, a physiological sensor, and a bedside or hospital monitor. The body network devices can be configured to support communication of status data, physiological information, alerts, control signals, and other information between one another. In addition, the body network devices can be configured to support networked communication of status data, physiological information, alerts, control signals, and other information between the body network devices and “external” devices, systems, or communication networks. The networked medical devices are configured to support a variety of wireless data communication protocols for efficient communication of data within the medical device network.

Abstract: Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used as part of a DMA operation generated by an I/O device that is programmed by a VM. It also includes transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written. It further includes updating a P2M translation table associated with the hypervisor, and an IOMMU translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page.

Abstract: A method of identifying devices on a bus and an apparatus are provided. A method of identifying devices on a bus comprises pooling a plurality of devices connected to a bus, each of the plurality of devices not having uniquely assigned to it a respective unique device identifier (ID) of the bus, selecting, after the pooling, one of the plurality of devices using at least one selection criteria, the at least one selection criteria identifying the one of the plurality of devices uniquely among all of the plurality of devices, and reassigning a unique device ID of the bus to the selected one of the plurality of devices uniquely. An apparatus is configured to carry out the method of identifying devices on a bus.

Abstract: An ID setting method and system capable of easily setting IDs of a plurality of display units. The ID setting system includes a plurality of display units connected through an input port and an output port to each other, and a control unit that controls assignment of an ID to each of the plurality of display units. Each of the display units compares a present ID to an initial ID, and disables a connection between the output port and an another display unit when the present ID and the initial ID match. Accordingly, a user can easily assign IDs to each of the plurality of display units.

Abstract: Method of processing data of at lease one data stream, data processing module for processing at a of at least one data stream, data processing system comprising such module, computer program product, data storage system and method of use thereof. For a time-based transfer of data to or from a device, data streams may be given a system ID and it is proposed to dynamically distribute available stream IDs. The proposed concept provides for indicating a type of data stream, providing and/or handling a set of stream IDs comprising a number of stream IDs and issuing a stream ID from the set of stream IDs to the data stream depending on the type of data stream. In a preferred embodiment, it is proposed to reserve one stream ID for an audio-video request, characterized by having no error handling time available. A further stream ID may be reserved for best effort requests.

Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.

Abstract: The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value.

Abstract: In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.

Abstract: An object of the present invention is to provide a module connecting system that can comply flexibly with the number of expansion modules and has an inexpensive and simple configuration. In the configuration of the module connecting system of the present invention, a basic module transmits a repetitive pulse signal to an expansion module, the repetitive pulse signal whose frequency is divided by a frequency dividing circuit included in the expansion module is output as frequency dividing information to the basic module, and the number of expansion modules is determined based on the frequency dividing information.

Abstract: A memory controller is unaware of device types of a plurality of memory devices in a serial interconnection configuration. Possible device types include, e.g., random access memories (DRAM, SRAM, MRAM) and NAND-, NOR- and AND-type Flash memories. Each device has device type information on its device type. Each device is capable of performing a “+1” to an input search number. First, the memory controller sends a specific device type (“don't care”) and an initial search number. Each device performs the “+1” calculation. The last device provides the memory controller with an Nד+1” search number from which the memory controller can recognize the total number of devices in the serial interconnection configuration. Thereafter, the memory controller sends a pre-determined device number for device type matching.

Abstract: There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access from outside. The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register.

Abstract: An article of manufacture, an apparatus, and a method for providing extended measurement word data from a control unit to a channel subsystem of an I/O processing system are disclosed. The article of manufacture includes at least one computer usable medium having computer readable program code logic. The computer readable program code logic performs a method including receiving a command message from the channel subsystem at the control unit, and initiating a timing calculation sequence of a plurality of time values in response to receiving the command message at the control unit. The computer readable program code logic also populates extended measurement word data at the control unit including the plurality of time values, and outputs the extended measurement word data from the control unit to the channel subsystem.