Abstract: A memory controller, and/or operation thereof, to generate a single interrupt for a plurality of data blocks which are the subject of a data transfer request. In an embodiment, a set of flags is allocated for the data transfer request, each flag corresponding to a respective one of the plurality of data blocks. In another embodiment, a single hardware interrupt is generated for all data which is the subject of the data transfer request, the generating based on an evaluation of the allocated set of flags.

Abstract: Embodiments of the invention are directed to systems and methods for reducing the number of interrupts on a controller for a non-volatile storage device to improve data transfer performance of the storage system. The embodiments described herein selectively enable an interrupt generated by host transfer hardware for a host command. The interrupt can be enabled or disabled by considering the command type, availability of interface resources to accept additional host transfers, and the command size. Embodiments described herein are useful for host interfaces implementing a tagging scheme for host transfers with a limited range of identification tags.

Abstract: Methods and systems for a personal video recorder (PVR) software buffer management to support the software passage are disclosed. A first plurality of receive buffer descriptors may be allocated for recording at least one received packet in at least a portion of a shared memory. The received packet may be recorded in the shared memory utilizing at least one of the allocated first plurality of receive buffer descriptors. A plurality of playback buffer descriptors may be allocated for playback of the recorded received packet from the shared memory. A first portion of the received packet may be simultaneously played back from the shared memory while recording a second portion of the received packet in the shared memory. If at least one of the recorded received packet is consumed, the playback buffer descriptors corresponding to a number of the consumed received packet may be de-allocated.

Abstract: A method for operating a host device includes comparing a predetermined response of a peripheral device to a response token received from the peripheral device. The predetermined response and the response token are generated based on a first command transmitted from the host device to the peripheral device. The method further includes controlling a transfer of first data from a first memory to a peripheral control module based on the comparison between the predetermined response and the response token without interrupting a host control module, and selectively passing interrupts to the host control module when the predetermined response does not match the response token.

Abstract: A method to perform a version pre-check of a storage controller command, wherein the method extracts a plurality of objects from a storage controller command, and determines, without querying the storage controller, if each object comprising a method or a method parameter is enabled on that storage controller. If each object comprising a method or a method parameter is enabled on the storage controller, the method indicates success for a version pre-check of the storage controller command.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a programmable logic controller (PLC). The system can comprise a serial communications port connected to the PLC. In certain exemplary embodiments, the system can comprise a controller adapted to enable a customer application program to access and control the serial communications port.

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.

Abstract: A device including an attachable multi-functional peripheral device and a method of managing functions according to a connection between the device and the multi-functional peripheral device includes the steps of: checking a connected/disconnected state of the multi-functional peripheral device and an open/closed state of the folding device when a preset interrupt is generated; and controlling a functional operation related the preset interrupt according to the connected or disconnected state of the multi-functional peripheral device and the open or closed state of the folding device.

Abstract: A utility meter comprises a measurement circuit configured to measure commodity consumption and provide consumption data. A memory in the meter is configured to store meter data including the consumption data. The memory includes a plurality of memory segments, each of the plurality of memory segments protected by a different password. The meter further comprises a receiver configured to receive a memory request and an associated password from a source external to the utility meter. A controller in the meter is configured to grant or deny the memory request depending upon the associated password received from the source external to the utility meter.

Abstract: A program disposed on a computer readable medium, having a main program with a first routine for issuing commands in an asynchronous manner and a second routine for determining whether the commands have been completed in an asynchronous manner. An auxiliary program adapts the main program to behave in a synchronous manner, by receiving control from the first routine, waiting a specified period of time with a wait routine, passing control to the second routine to determine whether any of the commands have been completed during the specified period of time, receiving control back from the second routine, and determining whether all of the commands have been completed. When all of the commands have not been completed, then the auxiliary program passes control back to the wait routine. When all of the commands have been completed, then the auxiliary program ends.

Abstract: Provided is an apparatus for processing a key input using an interrupt. When a key is pressed, a key input signal and a key interrupt signal may be generated and transmitted to a control unit which may process the pressed input key. When the control unit receives the key interrupt signal, the control unit may identify an input key corresponding to the key input signal and process the identified input key.

Abstract: A method for binding input/output (I/O) objects to nodes includes an subsystem receiving a request to use an I/O device from a process, determining a first resource to service the request, generating a first I/O object corresponding to the first resource, wherein the first I/O object is unbound, and sending the first I/O object to a Non-Uniform Memory Access (NUMA) I/O Framework. The method further includes the NUMA I/O Framework selecting a first NUMA node of a plurality of NUMA nodes, to which to bind the first I/O object and binding the first I/O object to the first NUMA node. The method further includes servicing the request by processing, on the first NUMA node, the first resource corresponding to the first I/O object.

Abstract: A method and apparatus for a programmable interrupt routing system is described.

Abstract: In general, this disclosure describes techniques that allow communication between devices/modules of a computer system regarding inter-device/module command execution. In accordance with the techniques described herein, an operating device of a computing system may receive from a client one or more command indications of commands to be executed on the operating device. The operating device may further receive at least one command completion indicator that indicates a command for which one or more clients are awaiting completion of execution. The operating device may generate an interrupt that indicates completion of execution of the command for which the at least one command completion indicator was received. The interrupt may be a generic interrupt or a client-specific interrupt. In this manner, inefficiencies caused by client monitoring of operating device command execution may be reduced.

Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.

Abstract: A method and a system for data transmission between a first electronic device and a second electronic device, wherein the second electronic device is in a sleep mode. Transmission of data between the first electronic device and the second electronic device occurs while a microprocessor in the second device is in sleep mode and the wireless transceiver is in a wake mode. The first electronic device transmits data signals and the second electronic device detects the transmitted signal. A base band processor in the second electronic device optionally determines if the signal is from a known source. If the first electronic device is a known electronic device, an interrupt signal is generated to wake up the microprocessor in the second electronic device. The wakened microprocessor opens a communication port and disables the wake-up interrupt. In yet another embodiment of the present invention, the data receive line is directly coupled to a line that triggers an interrupt when a signal is detected.

Abstract: A method for arbitrating between a host device and a cellular base band mode for use of a shared SD storage, including requesting, by a cellular base band modem from a host device, access to an SD storage, including writing an access request message, notifying the host device of the access request message, reading, by the host device, the access request message, granting, by the host device, the access request, including writing an access grant message, notifying the cellular base band modem of the access grant message, reading, by the cellular base band mode, the access grant message, holding an SD host bus in a busy state, thereby forcing the host device to hold and not access the bus, accessing, by the cellular base band modem, the SD storage, and upon completion of the accessing, removing the busy state from the SD host bus.

Abstract: A method to detect an event between a data source and a data sink using a trigger core is described herein. The method comprises monitoring control lines and an associated data stream for a programmable pattern, wherein the pattern is one or more of a condition, state or event. The method further comprises generating an indication by updating a status register, sending an interrupt or asserting a control line upon a pattern match.

Abstract: Method and system for latency-independent peripheral device identification. The computer system receives an interrupt from a peripheral device via a communications port. In response, an interrupt notification message is posted to alert a notification handler, and compliant peripheral class is determined. The voltage on a device may sense pin of the communications port for this determination. If the interrupt is indicative of the compliant peripheral class and the communications port is inactive, the port is opened, and an inquiry is sent and a response is received. If a response is received within a predetermined time period, an identification notification message is posted based on the response including information for classifying the peripheral device, so that a software handler registered with the operating system can handle the identification notification message when the software handler receives it. Thus, no time-critical interrupt response requirement is imposed for its successful operation.

Abstract: Disclosed is a disk array apparatus which includes disk apparatuses and which reads and writes data of the disk apparatus based on an I/O instruction issued by a host computer, includes: a CPU which carries out a first firmware; a memory which stores the first firmware in a first storage area of physical address space; and a TLB which belongs to the CPU and makes the first storage area of the physical address space of the memory associated with a first logical area of logical address space, wherein in case that the CPU receives a second firmware and an instruction to exchange firmware, the CPU stores the second firmware in a second storage area of the physical address space of the memory, and updates the TLB to make the second storage area associated with the first logical area. A method and program for exchanging firmware are also disclosed.

Abstract: Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor.

Abstract: Systems and methods for aggregating transmit completion interrupts for multiple packets are provided. A network device can include a buffer with multiple memory locations capable of temporarily storing a packet being transmitted across the network via the network device and nodes connected to the network device. The network device can include a high watermark for determining when to process transmit completion interrupts. If the number of packets stored in the memory exceeds the high watermark, an aggregated transmit completion interrupt for all of the packets can be processed. Otherwise, the network device waits until sufficient packets are received to reach the high watermark.

Abstract: A host device includes an electrical activity monitoring (EAM) module that is configured to monitor the electrical activity of a slave storage device interfaced with the host device. Responsive to the value of, or change in, the electric current fed to the slave storage device being at or near a certain level, or within a predetermined range, the EAM module notifies the host device that the slave storage device has pending service request(s) or information for the host device.

Abstract: Firmware is interactively updatable in a setup facility prior to loading an operating system on a computer. A computer repeatedly provides progress information during the course of a firmware update. This progress information may be in the form of a repeatedly updated completion percentage displayed on a screen during the update.

Abstract: Methods and apparatus to transfer data between one or more clock domains are described. In one embodiment, a plurality of signals corresponding to write pointers of a buffer and a read pointer of the buffer are generated. The signals corresponding to the write pointers of the buffer are to be generated based on different data patterns for transmission over different channels. Other embodiments are also claimed and described.

Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.

Abstract: A device, method and software for handling multiple interrupts in a peripheral device are disclosed. The disclosed method includes, upon a hardware event in the peripheral device recording the hardware event and determining an acceptable period before which an interrupt should be generated to service the event. A timer at the peripheral device is adjusted as needed to maintain a value within the acceptable period. Upon expiry of the timer a single interrupt is generated to a processor interconnected to the peripheral device. In response to the single interrupt, software code is executed on the processor to service un-serviced hardware events for which an indicator has been recorded.

Abstract: Computerized methods, computer systems, and computer-readable media for governing how virtual processors are scheduled to particular logical processors are provided. A scheduler is employed to balance a CPU-intensive workload imposed by virtual machines, each having a plurality of virtual processors supported by a root partition, across various logical processors that are running threads and input/output (I/O) operations in parallel. Upon measuring a frequency of the I/O operations performed by a logical processor that is mapped to the root partition, a hardware-interrupt rate is calculated as a function of the frequency. The hardware-interrupt rate is compared against a predetermined threshold rate to determine a level of an I/O-intensive workload being presently carried out by the logical processor. When the hardware-interrupt rate surpasses the predetermined threshold rate, the scheduler refrains from allocating time slices on the logical processor to the virtual machines.

Abstract: Coprocessor systems for using a main microprocessor DMA channel to write to a port to control a coprocessor system are provided. In certain examples, coprocessor systems are described using a main CPU counter to trigger a DMA channel to perform a single byte transfer to a port used to control coprocessor command timing.

Abstract: A portable communication device (10) may send a service device locating request (42) including a position associated with the portable communication device to a service device locating device (12). The service device locating device (12) may determine at least one service device located close to the indicated position and respond to the request by sending a response (46) including at least one network identifier of a service device (16) capable of handling the desired service. The portable communication device may then directly contact (48) the service device (16).

Abstract: A method and apparatus for transferring data from a first electronic device to a second electronic device, both first and second electronic devices having Universal Serial Bus (USB) client interfaces, the method comprising the steps: connecting the two electronic devices with a USB cable; toggling the voltage on a VBUS line of the USB cable between logic high voltage and no voltage at the first electronic device; detecting toggles of the VBUS line at the second electronic device; and interpreting the toggles detected in the detecting step as data.

Abstract: To provide a multi-core LSI capable of improving the stability of operation. A multi-core LSI comprises a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bus and the second shared bus, for arbitrating an access to the module (s) by the CPUs, and a system controller that monitors whether or not a response signal to an access request signal of the CPUs is output from module to be accessed, wherein the system controller outputs a pseudo response signal to the first shared bus via the shared bus controller to terminate the access by the CPU while accessing if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses.

Abstract: The invention relates to a method for computer signal processing data and command transfer over an interface and more particularly to a communication between peripheral firmware and a host processor or Basic Input/Output System (BIOS) on a Peripheral Component Interconnect (PCI) bus. In one embodiment, a device and method for reducing the load on the PCI Bus is described. In yet another embodiment, a device and method is described for constructing a variable length command block comprising message frames and aligning all message frames for a particular command block that are contiguous in memory.

Abstract: A method includes halting at least one processing core of a computer system in response to a system management interrupt. The method further includes handling the system management interrupt with at least one other processing core of the computer system in response to determining that the at least one processing core is halted. An associated system and machine readable medium are also disclosed.

Abstract: Herein described are at least a system and a method of reducing or decreasing the rate of interrupts transmitted by a device to a microprocessor. In a representative embodiment, the device comprises a universal asynchronous receiver/transmitter. In a representative embodiment, the rate of interrupts is reduced by receiving and using a first signal as an input to a first counter. The first counter outputs a first count, and compares the first count to a value provided by a memory. Subsequently, a second signal is generated to initiate an interrupt when the first count equals the value. In a representative embodiment, a system for delaying transmission of an interrupt from a universal asynchronous receiver/transmitter (UART) to a microprocessor comprises a counter capable of generating a count, a memory capable of storing a value, and a comparator used for comparing the count to the value.

Abstract: In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract: An interrupt controller for a disk controller includes an interrupt scanner module that receives a plurality of interrupt requests (IRQs) from a plurality of corresponding interrupt sources, performs a scan of respective vector values of the plurality of IRQs, and selectively outputs a priority based on the scan. An interrupt generation module receives the priority and generates at least one of a fast interrupt and a regular interrupt based on the priority.

Abstract: In one embodiment, a method includes receiving an incoming posted transaction in a processor complex from a peripheral device, determining if the transaction is an interrupt transaction, and if so routing it to a first queue, and otherwise routing it to a second queue. Other embodiments are described and claimed.

Abstract: In a processing system with a main partition and a sequestered partition, the main partition sends an interrupt to the sequestered partition before calling an operating system (OS) boot loader for the main partition. The sequestered partition may then enter an interrupt handler. After the sequestered partition enters the interrupt handler, an address line of the processing system may be disabled, and the OS boot loader for the non-sequestered partition may be called. The sequestered partition may then determine whether the address line has been re-enabled. The sequestered partition may remain in the interrupt handler until after the address line has been re-enabled. Other embodiments are described and claimed.

Abstract: A method for interfacing single transfer and burst transfer components, comprising: processing transfer completion of a byte in burst transfer as an interrupt; maintaining the current state of signal lines to prevent occurrence of next interrupt; copying the transferred byte from buffer to memory; and allowing next interrupt; and enabling sending of next byte in burst transfer. This invention interfaces incompatible signaling of the components, and solves the handshake, communication and buffering problems involved.

Abstract: An I2C bus control circuit includes a continuous transmission control section in addition to a transmission control section, a sequence control section, a data line control section, and a clock line control section. The continuous transmission control section has a number-of-continuous transmission bytes register and first to (n?1)th continuous transmission data registers, and supplies an interrupt signal to the controller when continuous transmission is completed or an error is detected. The number of times the controller conducts interrupt processing is thus reduced and the processing time is reduced.

Abstract: A communication program causes a computer to perform communication processing of received packets in response to reception of interrupt processing, the interruption processing being a packet reception notification after the lapse of a predetermined holding time. The communication program causes the computer to perform a packet counting process of counting the number of received packets received per unit time, and a parameter value changing process of changing, based on a counting result of the packet counting process, a timer parameter value for determining the time packets are held before processing.

Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

Abstract: A system that includes a docking station comprising a graphics processor and a transceiver. The system also includes a computer comprising a display. The computer is in communication with the docking station. The graphics processor receives input signals from the computer and, as a result, provides output signals to the computer. The computer uses the output signals to display images on the display.

Abstract: A system and method for logging events processed by an operating system is provided. The events logged can include interrupt and non-interrupt events, and can include user-defined events. Information concerning the interrupt events is initially written, during event handling time, into a first buffer while information concerning non-interrupt events is initially written, during event handling time, into a second buffer. Information from the two buffers is then written to a third buffer not during event handling time. Separating the interrupt event buffer from the non-interrupt event buffer rather than having one buffer, and writing relatively small amounts of data during event handling time to memory, rather than transporting data to slower non-memory mapped devices allows the event logger to be less intrusive and facilitates greater accuracy in event logging.

Abstract: A platform to support verification of the contents of an input-output device. The platform includes a platform hardware, which may verify the contents of the I/O device. The platform hardware may comprise components such as manageability engine and verification engine that are used to verify the contents of the I/O device even before the contents of the I/O device are exposed to an operating system supported by a host. The platform components may delete the infected portions of the contents of I/O device if the verification process indicates that the contents of the I/O device include the infected portions.

Abstract: An apparatus, method, and computer-readable program code for dynamically controlling slip is disclosed. The method monitors the time of an actual interrupt, wakes up, interacts with the physical environment, and then notes the completion time and reduces a wait period. The wait period ends in a scheduled interrupt time. By reducing the wait period based on the difference between the actual interrupt time (instead of the scheduled interrupt time) and the completion time, slip is prevented from accumulating and is reduced.

Abstract: The present invention provides an interrupt generation circuit that can reduce the time between the moment a monitored object actually enters a desired state and the moment an interrupt is generated. An external event detection unit 101 detects the effective edge of an external event signal. A count period generation circuit 103 generates external event division signals which are counted by the main timer 104 and each of which has a period that is 1/N of the time interval between the effective edges of the immediately preceding external event signal. A compare register 105 stores a value corresponding to the time at which an interrupt is to be generated. When the count value of the main timer 104 becomes equal to or larger than the value stored in the compare register 105, the interrupt determination circuit 106 generated an interrupt.

Abstract: A method for command transmission between systems is introduced. The command transmission between the systems, such as a north bridge chip, a south bridge chip and a central processing unit (CPU), employs the signals transmission specified by a PCI Express bus originally for the communication between system chips or peripheral devices. The signals transmission includes an interrupt or a system management instruction specified by the PCI Express bus, which further defines the specific addresses of a memory packet and a system message packet. In the preferred embodiment, the method thereof comprises the steps of transmitting an INTA command first, then a second system chip upstreams an INTR/system-management command to a first system chip. After that, the first system chip downstreams an EOI/system-management command to the second system chip.