Abstract: A system and method that allows out of order fetching of host non-volatile memory commands can improve and maximize the memory device performance. The memory device can examine the non-volatile memory command headers available in the non-volatile memory command queue to select one or more, non-volatile memory commands to be fetched, in an optimum order and executed according to currently available resources in the memory device. The memory device can optimize performance of the non-volatile memory commands by re-ordering the host commands fetched from the host memory.

Abstract: An information processing apparatus includes: a retention unit that retains a list of paper information and detailed information associated with the paper information; a first acquisition unit that acquires a list of paper information from a storage unit of a printer; an update unit that updates the list of the paper information retained in the retention unit by using the acquired list of paper information; a second acquisition unit that acquires, based on a difference between the list, of the paper information retained in the retention unit and the acquired list of paper information, part of detailed information associated with paper information stored in the storage unit, from the storage unit; and a generation unit that generates, based on the detailed information acquired by the second acquisition unit, data to be transmitted to the printer. The update unit updates, based on the acquired detailed information, the retained detailed information.

Abstract: Many storage devices (or drives) include a mechanism, such as a processor, to execute internal maintenance process(es) that maintain data integrity and long-term drive health. One example of such an internal maintenance process is a background media scan (BMS). However, on busy systems, the BMS may not have an opportunity to execute, which can damage long term drive performance. In one embodiment, a method includes sending a command from a host device to a storage device. The storage device can responsively run an internal maintenance process of the storage device. In one embodiment, the internal maintenance process can be an internal maintenance process such as a background media scan.

Abstract: A testing device of high-frequency memory comprises a transfer interface, a tester and a socket group. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal, wherein the first testing signal and the second testing signal are outputted by the tester, and through the transfer interface, the double frequency testing signal is shared and transmitted to the socket group for testing at least two memory packages disposed on the socket group.

Abstract: A memory system includes: a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: Embodiments of the present invention provide methods, systems, and computer program products for transferring data in a MapReduce framework. In one embodiment, MapReduce jobs are performed such that data spills are stored by mapper systems in memory and are transferred to reducer systems via one-sided RDMA transfers, which can reduce CPU overhead of mapper systems and the latency of data transfer to reducer systems.

Abstract: A system is provided that generates a dynamic haptic effect that includes one or more key frames, where each key frame includes a first interpolant value and a first haptic effect. The system further receives an interpolant value, where the interpolant value is between at least two interpolant values of at least two key frames. The system further determines the dynamic haptic effect from the interpolant value. The system further distributes the dynamic haptic effect among a plurality of actuators.

Abstract: An apparatus and a method that includes a program execution monitoring dedicated circuit connected to a CPU of a control apparatus of an on-vehicle electronic equipment that includes an execution time monitoring timer circuit, an execution sequence monitoring comparison circuit, a setting register, and an other attached circuit, perform monitoring of an execution sequence of a task executed by a control program of the on-vehicle electronic equipment and/or an execution time of the task executed by the control program, stop monitoring the execution time of the task when a priority interruption occurs, and enable the control of the on-vehicle electronic equipment such as an electric power steering apparatus to be continued by performing an alternative processing in the case of detecting an abnormality in the execution sequence and/or the execution time.

Abstract: A method for controlling an I2C slave device with the aid of a control device, including: evaluating states on a data line and on a clock line of the I2C bus; and assigning the states on the data line and on the clock line to states in a state diagram, control signals for the I2C slave device being generated with the aid of the control device from the states in the state diagram.

Abstract: A method, comprises receiving a test case on a processor, receiving an input from a user to call the test case in a first calling environment, identifying the first calling environment, setting a first indicator in a memory indicating the first calling environment, running a directive in the test case, wherein the directive calls a subroutine associated with the directive, and running the subroutine called by the directive wherein the subroutine includes receiving the first indicator indicating the first calling environment, performing a first task associated with the directive wherein the first task is performed in the first calling environment responsive to receiving the first indicator indicating the first calling environment, and outputting a result of the first task to a user on a display.

Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.

Abstract: A method, computer program product, and computing system for receiving a point-in-time copy command for a virtual volume exposed within a storage virtualization layer of a storage system. The point-in-time copy command is provided to one or more data arrays underlying the storage virtualization layer. The virtual volume is associated with physical storage within the one or more data arrays, thus defining associated physical storage. A level of high-availability is identified for the associated physical storage. A copy of the associated physical storage is generated that has the same level of high-availability, thus defining a high-availability copy.

Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

Abstract: Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.

Abstract: A semiconductor device includes a memory device, a host, and an interface. The memory device includes various types of memory units configured to be mounted to one slot. The host stores memory characteristic information of the various types of memory units contained in the memory device, processes a signal for the memory units on the basis of the memory characteristic information, and transmits and receives the processed signal to and from the memory units. The interface allows the host to interface with the various types of memory units contained in the memory device.

Abstract: Embodiments herein provide for tag allocation in a PCIe application layer. In one embodiment, an apparatus operable to interface with a plurality of virtual functions and a plurality of physical functions to process data via the PCIe protocol. The apparatus includes a packet builder communicatively coupled to each of the virtual functions and the physical functions and operable to build packets for non-posted commands from the virtual and physical functions. The apparatus also includes a tag allocator operable to allocate tags from a first set of tags to the packets of non-posted commands from any of the virtual and physical functions employing extended tags when the tags of the first set are available, and to reserve a second different set of tags for remaining virtual and physical functions not employing extended tags until the first set of tags are all allocated.

Abstract: An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device.

Abstract: A firmware updating method in just a bunch of disks includes the following blocks. A motherboard is coupled to a first primary storage extension chip or to a second primary storage extension chip. The first primary storage extension chip and the second primary storage extension chip are coupled to each other. At least one secondary storage extension chip is coupled to the first primary storage extension chip. At least one secondary storage extension chip is coupled to the second primary storage extension chip. A signal sent to the first primary storage extension chip or to the second primary storage extension chip by the motherboard causes firmware of each storage extension chip to be updated.

Abstract: Methods and SATA devices having more than one operating state suitable for providing efficient command and data transfers over a SATA bus. A SATA device is provided for communicating with a host. The host sends commands to the SATA device and the SATA device sends data to the host in response to the commands being received by the SATA device. The SATA device has a queue of commands received from the host. The SATA device is configured to operate in a first operating state wherein the commands are received by the SATA device and the data are not sent to the host, and a second operating state wherein the commands are received by the SATA device and the data are sent to the host wherein data being sent to the host has priority over receiving commands by the SATA device.

Abstract: A method, non-transitory computer readable medium, and device that manages API requests includes receiving an API request to obtain a list of storage volumes from one or more storage devices, wherein the received API request is non-compatible with the API server computing device or the one or more storage devices. The received API request is scanned to identify a service type associated with the received request. Next, one or more service instances associated with the identified service type are identified. The list of storage volumes from the one or more storage devices using information from at least one service instance of the identified one or more service instances without converting the received API request is provided.

Abstract: An apparatus and a method that includes a program execution monitoring dedicated circuit connected to a CPU of a control apparatus of an on-vehicle electronic equipment that includes an execution time monitoring timer circuit (111), an execution sequence monitoring comparison circuit (113), a setting register (115), an attached circuit (117), perform monitoring of an execution sequence of a task executed by a control program of the on-vehicle electronic equipment and/or an execution time of the task executed by the control program, and enabled to continue the control of the on-vehicle electronic equipment such as an electric power steering apparatus by performing an alternative processing in the case of detecting an abnormality in the execution sequence and/or the execution time.

Abstract: The present invention relates to an apparatus and a method for transferring a data signal between a smartcard interface and an interface of a processor within an embedded system. According to an exemplary embodiment of the present invention, an interface conversion device communicating between a processor and a smartcard IC chip includes: an input/output signal conversion logic configured to transfer a signal between a first interface of the processor and a second interface of the smartcard IC chip; a clock generator configured to generate a clock signal driving the smartcard IC chip depending on a first control signal received from the processor and provide the generated clock signal to the smartcard IC chip; and a reset controller configured to generate a reset signal depending on a second control signal received from the processor and provide the generated reset signal to the smartcard IC chip.

Abstract: A technique quantifies logical storage space trapped in an extent store due to overlapping write requests associated with volume metadata managed by the volume layer. The volume metadata is illustratively organized as a multi-level dense tree metadata structure, wherein each level of the dense tree metadata structure (dense tree) includes volume metadata entries for storing the volume metadata. When a level of the dense tree is full, the volume metadata entries of the level are merged with a next lower level of the dense tree in accordance with a merge operation. Illustratively, the technique may be invoked during the merge operation to examine the volume metadata entries at each level of the dense tree involved in the merge and determine the LBA range overlap of the entries.

Abstract: A method of migrating DMA mappings from a source I/O adapter of a source computing system to a destination I/O adapter of a destination computing system, including: collecting, by a source hypervisor of the source computing system, DMA mapping information, wherein the source hypervisor supports operation of a logical partition executing on the source computing system and the logical partition is configured for DMA operations with the source I/O adapter utilizing the DMA mapping information; configuring, by a destination hypervisor of the destination computing system, the destination I/O adapter with DMA mappings based on the DMA mapping information collected by the source hypervisor; placing, by the destination hypervisor, the destination I/O adapter in an error state; migrating the logical partition from the source computing system to the destination computing system; and restarting the logical partition on the destination computing system, including recovering, by the logical partition, from the error state

Abstract: Migrating DMA mappings from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, DMA mapping information, where the hypervisor supports operation of a logical partition executing on the computing system and the logical partition is configured for DMA operations with the source I/O adapter utilizing the DMA mapping information; configuring, by the hypervisor, the destination I/O adapter with DMA mappings based on the DMA mapping information collected by the hypervisor; placing, by the hypervisor, the source and destination I/O adapter in an error state; deconfiguring the source I/O adapter from the logical partition; and enabling the logical partition and destination I/O adapter to recover from the error state.

Abstract: A computer-implemented method for protecting computing systems from peripheral devices may include (1) identifying a peripheral device configured to perform a charging function and at least one non-charging function, (2) configuring an endpoint protection application with an endpoint protection rule that allows the charging function of the peripheral device and does not allow the non-charging function of the peripheral device, (3) detecting that the peripheral device is connected to a computing system that is provisioned with the endpoint protection application, and (4) applying the endpoint protection rule on the computing system to allow the charging function of the peripheral device so that the peripheral device is able to charge via the computing system and block the non-charging function of the peripheral device from being performed on the computing system. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A storage system comprises a storage array comprising a plurality of solid state storage devices (SSDs), a first processor comprising a first root complex of the storage system, a plurality of controller devices, and a first switch to interconnect the plurality of SSDs, the first processor and the plurality of controller devices. A first controller device of the plurality of controller devices is to connect the storage system to one or more remote servers. The first controller device is further to receive a first request from a first server of the one or more remote servers and determine whether the first request is a data request or a control request. The first controller device is further to send a first message to a first SSD of the plurality of SSDs via the first switch, bypassing the first processor, responsive to a determination that the first request is a data request.

Abstract: In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation. Channels of multiple buffers and associated processors provide implement read and write instructions received at the interface. Multiple access modes are provided to read and write to system memory and to store sequences of commands in the provided buffers and to execute those stored sequences using an associated processor. By writing a sequence of commands and/or data blocks to the channel buffers, the associated processors can execute programs of varying complexity that may have been written or modified in real time or preconfigured.

Abstract: Aspects include transmitting a synchronous I/O command to a persistent storage control unit (SCU in response to a synchronous I/O request from an operating system (OS). A unit of work in the OS corresponding to the synchronous I/O request remains active at least until the synchronous I/O request is completed. Based on an operation code of the synchronous I/O command specifying a read operation and in response to detecting that the persistent SCU has stored one or more read data records in a memory located on the processor, the firmware indicates to the OS that the synchronous I/O request is completed. Based on the operation code specifying a write operation and in response to detecting an indication from the persistent SCU that write data has been written or indicating that an error has occurred, indicating to the OS that the synchronous I/O request is completed.

Abstract: In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.

Abstract: Aspects include communicating synchronous input/output (I/O) commands between an operating system and recipient by issuing a first synchronous I/O command with an initiation bit set, identifying that a mailbox command has been initiated to return control to an operating system before waiting for operations of the first synchronous I/O command to complete, and issuing a second synchronous I/O command with a completion bit set in response to the control returning to the operating system.

Abstract: Aspects include transmitting a synchronous I/O command to a persistent storage control unit (SCU in response to a synchronous I/O request from an operating system (OS). A unit of work in the OS corresponding to the synchronous I/O request remains active at least until the synchronous I/O request is completed. Based on an operation code of the synchronous I/O command specifying a read operation and in response to detecting that the persistent SCU has stored one or more read data records in a memory located on the processor, the firmware indicates to the OS that the synchronous I/O request is completed. Based on the operation code specifying a write operation and in response to detecting an indication from the persistent SCU that write data has been written or indicating that an error has occurred, indicating to the OS that the synchronous I/O request is completed.

Abstract: A computing device includes, a memory component, a memory module including memory resistors, and a virtualization module. The virtualization module intercepts communication between an application and a memory component and directs the communication to the memory module including memory resistors. The virtualization module directs communication from the memory module to the application.

Abstract: Aspects include communicating synchronous input/output (I/O) commands between an operating system and recipient by issuing a first synchronous I/O command with an initiation bit set, identifying that a mailbox command has been initiated to return control to an operating system before waiting for operations of the first synchronous I/O command to complete, and issuing a second synchronous I/O command with a completion bit set in response to the control returning to the operating system.

Abstract: A proactive networking system and method is disclosed. The network anticipates the user demands in advance and utilizes this predictive ability to reduce the peak to average ratio of the wireless traffic and yield significant savings in the required resources to guarantee certain Quality of Service (QoS) metrics. The system and method focuses on the existing cellular architecture and involves the design and analysis of learning algorithms, predictive resource allocation strategies, and incentive techniques to maximize the efficiency of proactive cellular networks. The system and method further involve proactive peer-to-peer (P2P) overlaying, which leverages the spatial and social structure of the network. Machine learning techniques are applied to find the optimal tradeoff between predictions that result in content being retrieved that the user ultimately never requests, and requests that are not anticipated in a timely manner.

Abstract: A communication apparatus performs wireless connection processing for performing wireless communication with another communication apparatus, specifies a service that is to be executed along with the other communication apparatus, in the wireless connection processing, using wireless communication that is based on the wireless connection processing, and performs port control such that a port necessary for execution of the specified service is opened, and a port not necessary for execution of the service is locked.

Abstract: In response to receiving a “Return Available PPI Credits” command from a credit-aware (CA) device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the CA device, and zeroes out its stored CTBR value. The CA device adds the credits returned to a “Credits Available” value it maintains. The CA device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another aspect, the CA device issues one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.

Abstract: One embodiment of the present invention sets forth a technique for distributing graphics commands and atomic commands to a color processing unit (CROP) in an efficient manner. The interleaving mechanism determines, at each clock cycle, which graphics command(s) or atomic command(s) is transmitted to the CROP based on different factors. First, the interleaving mechanism ensures that atomic commands or graphics commands associated with a multi-transaction command stream are processed together. Second, the interleaving mechanism selects consecutive graphics commands for transmission to the CROP that optimize the use of different memory caches. Third, the interleaving mechanism prioritizes atomic commands over graphics commands. At each clock cycle, the graphics command(s) or the atomic command(s) selected by the interleaving mechanism are transmitted to the CROP for processing.

Abstract: Techniques are described for securely provisioning a client device. A client device may output first client information over a secure interface to a trusted device to be transmitted to an authentication server. Second client information related to the first client information may be transmitted to the authentication server. The authentication server may link the second client information and the first client information. The client device may receive an encrypted authentication credential from the authentication server. The authentication credential may be encrypted based at least in part on the first client information or the second client information. The client device may decrypt the encrypted authentication credential using the first client information, the second client information, or a shared secret key.

Abstract: There is provided a reconfigurable semiconductor device including a plurality of circuit blocks each including a reconfigurable logic unit, and an analog circuit configured to convert an analog signal from the outside into a digital signal to output the digital signal to the reconfigurable logic unit, and convert a digital signal outputted from the reconfigurable logic unit into an analog signal to output the analog signal to the outside. The circuit block has a rectangular shape, is connected to the two adjacent circuit blocks from one side with a plurality of analog lines, and is connected to the other two adjacent circuit blocks from the other side on a side opposite to the one side with a plurality of analog lines.

Abstract: A device and method for communicating between cores are provided. The device comprises: a postbox component, configured to store a message sent from a message sending core to a message receiving core and notify the message receiving core to read the message; and a bus adapter component, connected between the postbox component and the message receiving core and the message sending core which communicate with each other and configured to provide read/write interfaces of the postbox component and the message receiving core and the message sending core. By means of the disclosure, the problems that the device and method for communicating between cores with high complexity, poor timeliness and poor expandability during multi-core application in the related art are solved, thereby achieving the effects of reducing the communication between cores complexity significantly, reducing communication time delay and having excellent expandability and scalability.

Abstract: Example embodiments of the present invention provide for parallel replication of an IO received by a storage array. Such parallelism provide numerous benefits, including enqueuing the command phase of the write command at the storage array and the replication appliance in parallel, providing data still in memory (i.e., slot) and not destaged to disk, and providing data processing in parallel (e.g., validate checksum, validate data is good, validate internal data structures).

Abstract: An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device.

Abstract: Aspects of the present disclosure describe automatically changing an output mode of an output device from a first output mode to a latency reduction mode. An initiation signal and the output data may be received from a client device platform or a signal distributor. Upon receiving the initiation signal, the output device may change the output mode from the first output mode to the latency reduction mode. Thereafter, the output device may receive an end latency reduction mode signal. The output device may then revert back to the first output mode. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A system and method for creating a rights expression for association with an item for use in a system for controlling use of the item in accordance with the rights expression, including specifying rights expression information indicating a manner of use of an item, the rights expression information including at least one element, the element having a variable and corresponding value for the variable; and performing an encoding process, including determining an identifier associated with a template corresponding to the rights expression information, extracting from the rights expression information the value for the variable corresponding to the element, and encoding a license adapted to be enforced on a device based on the variable and the identifier, the license including an identification of the template and the value for the variable.

Abstract: Hybrid storage apparatus and logical block address assigning methods for the hybrid storage apparatus are provided. A hybrid storage apparatus includes a plurality of storage apparatuses having different writing methods, and a controller to combine the storage apparatuses as a single storage apparatus, to assign one or more logic block addresses to the single storage apparatus, and to access the storage apparatuses using the logic block addresses. The address assigning method of a hybrid storage apparatus includes searching and detecting one or more storage apparatuses included in a hybrid storage apparatus when an initially set condition is generated, combining the storage apparatuses as a single storage apparatus, assigning one or more logic block addresses to the single storage apparatus, and accessing the storage apparatuses using the logic block addresses.

Abstract: Enhanced handling of device configuration data in wireless communication devices is provided herein. In one example, a method is presented that includes receiving data transferred by a device management node for incorporation into a node of a configuration data tree that stores device configuration data for the wireless communication device. The method also includes identifying the data as unable to be incorporated into the configuration data tree, and transferring a rejection notice for delivery to the device management node. The method also includes receiving a node addition instruction and responsively creating a new data tree that is populated with at least one blank node and is linked to a root node shared with the configuration data tree. The method also includes receiving again the data transferred by the device management node and responsively incorporating the data into the blank node of the new data tree.

Abstract: Techniques are described herein that are capable of suggesting intent frame(s) for user request(s). For instance, the intent frame(s) may be suggested to elicit a request from a user. An intent frame is a natural language phrase (e.g., a sentence) that includes at least one carrier phrase and at least one slot. A slot in an intent frame is a placeholder that is identified as being replaceable by one or more words that identify an entity and/or an action to indicate an intent of the user. A carrier phrase in an intent frame includes one or more words that suggest a type of entity and/or action that is to be identified by the one or more words that may replace the corresponding slot. In accordance with these techniques, the intent frame(s) are suggested in response to determining that natural language functionality of a processing system is activated.

Abstract: A method of storing log entries of events from a plurality of network elements in a communication network, comprising the steps of: a) receiving log entries at a control processor of events from a plurality of different elements positioned, the log entries grouped into threads based on a common purpose; b) converting each log entry into a compact log record in a logging module, and c) storing the compact log records in a first memory buffer in random access memory (RAM) forming a first log file.

Abstract: System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.