Abstract: A card device according to an aspect of the present disclosure includes: a first interface that connects the card device with a host device. The card device notifies, through the first interface, the host device of whether or not the card device includes a second interface different from the first interface.

Abstract: A computer-implemented method for processing blockchain-based transactions, the computer-implemented method including: receiving a target transaction initiated by a member node device in a blockchain, wherein the target transaction comprises a unique identifier of the target transaction; querying a transaction idempotent table on the block chain to determine whether the transaction idempotent table has stored a transaction idempotent record corresponding to the unique identifier of the target transaction; and in response to determining that the transaction idempotent table has not stored the transaction idempotent record corresponding to the unique identifier of the target transaction, recording the target transaction in a candidate block on the blockchain.

Abstract: The present technology includes a controller including an allocation manager configured to determine whether a host identification (ID) output from a host is an allocable ID, an address manager configured to perform an allocation operation using the host ID to select logical blocks corresponding to the host ID when the host ID is received from the allocation manager, and output an address of the logical blocks as an allocation address, and a map table component configured to store a map table in which logical block addresses and physical block addresses are respectively mapped, select a logical block address corresponding to the allocation address, and output the physical block address mapped to the selected logical block address, a memory system including the controller, and a method of operating the memory system.

Abstract: A storage device includes a nonvolatile memory device; and a controller configured to, sequentially receive first read commands and a first write command, the first write command being associated with first write data, slice the first write command to generate a plurality of sub-commands, slice the first write data to generate a plurality of sub-data elements, and alternately transmit, to the nonvolatile memory device, at least one read command of the first read commands, and one sub-command of the plurality of sub-commands and one sub-data element of the plurality of sub-data elements.

Abstract: A first computing device is part of a distributed electronic storage system (DESS) that also comprises one or more second computing devices. The first computing device comprises client process circuitry and DESS interface circuitry. The DESS interface circuitry is operable to: receive, from client process circuitry of the first computing device, a first client file system request that requires accessing a storage resource on one or more of the second computing devices; determine resources required for servicing of the first client file system request; generate a plurality of DESS file system requests for the first file system request; and transmit the plurality of DESS file system requests onto the one or more network links. How many such DESS file system requests are generated is determined based on the resources required for servicing the first client file system request.

Abstract: A high speed tabletop and industrial printer is disclosed with integrated high speed RFID encoding and verification at the same time. The industrial printer simultaneously prints on and electronically encodes/verifies RFID labels, tags, and/or stickers attached to a continuous web. The industrial printer comprises a lighted sensor array for indexing the printing to the RFID tags; and a cutter powered from the industrial printer for cutting the web that the RFID tags are disposed on. The industrial printer comprises two RFID reader/writers that are individually controlled. Specifically, one of the RFID reader/writers comprises the ability to electronically encode the RFID tags while the web is moving; and the second RFID reader/writer uses an additional RFID module and antenna on the printer for verifying the data encoded to the RFID tags. The printer provides for successive writes to various memory blocks and optimizes the communication sequence between the interrogator and tag.

Abstract: The present disclosure discloses a file access method of a virtualization instance, including performing union on some image subfiles in a host operating system (host OS) and mounting a united directory to a union directory, and when an application in a library operating system instance needs to access a file in the union directory, causing a central processing unit to generate an exit event such that a hypervisor captures and processes the exit event, and during processing, converts an access request that is from the instance into an access request based on a system call of the host OS, and performs access.

Abstract: A method and apparatus for determining a port rate determines a channel transmission rate of an SAS port including N physical channels. The method includes: determining M different negotiated rates of the N physical channels; separately determining M total port bandwidths corresponding to the M different negotiated rates; and determining a negotiated rate corresponding to a largest total port bandwidth in the M total port bandwidths as a channel transmission rate of the port. A lowest negotiated rate is no longer used as the channel transmission rate of the port, but the negotiated rate corresponding to the largest total port bandwidth is determined as the channel transmission rate of the port.

Abstract: [Object] To provide a communication apparatus, a communication method, and a program, each of which is capable of flexibly controlling operation of the communication apparatus in accordance with a change in communication environment while reducing power consumption. [Solution] A communication apparatus includes: a control module configured to control operation of the communication apparatus; and a communication module configured to determine whether or not information obtained by reception from another communication apparatus has been changed and control state transition of the control module in a case where it is determined that the information obtained by the reception has been changed.

Abstract: Techniques for processing I/O operations may include: receiving, an I/O operation including a tag value denoting a process of a database application that issued the I/O operation; determining, in accordance with the tag value, whether the I/O operation is directed to a data file storing content of a database or a log file of recorded operations of the database; and responsive to determining the I/O operation is directed to a data file storing content of the database, performing processing including: determining a current configuration setting of the database that indicates whether the database is configured for use with the database application as an in-memory database; and determining, in accordance with current configuration setting of the database, a first service level objective for the I/O operation, wherein the first service level objective for the I/O operation is a default service level objective or a revised service level objective.

Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

Abstract: A method for enforcing data integrity in an RDMA data storage system includes flushing data write requests to a data storage device before sending an acknowledgment that the data write requests have been executed. An RDMA data storage system includes a node configured to flush data write requests to a data storage device before sending an acknowledgment that a data write request has been executed.

Abstract: A signal processing apparatus includes a memory; a processor comprising arithmetic logic units (ALUs); and a hardware accelerator configured to perform an arithmetic logic operation by using shared ALUs that are not used by the processor among the ALUs.

Abstract: In an information processing apparatus, a processor firstly acquires all device port names registered in a memory, and instructs the operating system to register new device information indicating a new device. The processor secondly acquires, in response to determining that the operating system completes registering the new device information, all device port names including the new device port name associated with the new device information from the memory. The processor identifies the new device port name which is included in the secondly acquired device port names but excluded from the firstly acquired device port names by comparing the firstly acquired device port names with the secondly acquired device port names, and registers in the operating system the new device port name and the software to be correlated with each other so that the software can communicate with the new device through the new device port.

Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

Abstract: Implementations disclosed herein include a system and method of storing one or more data and program data in a memory, temporarily storing the one or more data and the program data in a cache, managing the one or more data from the memory and the cache in a read data register and a read cache register, and managing the program data from the memory and the cache in a program data register and a program cache register, wherein each of the read data register and the read cache register are separate from the program data register and the program cache register. Read operations are performed only with the read data register and the read cache register. Program operations are performed only with the program data register and the program cache register.

Abstract: A system is described that mitigates the unintentional triggering of action keys on keyboards. The system detects and interprets first and second keyboard input events. If the first keyboard input event is interpreted as a character input and the second keyboard input event is interpreted as an action input, the system performs a pattern analysis based at least on an elapsed time between the first and second keyboard input events. If the second keyboard input is determined to be unintentional, the system may mitigate the unintentional triggering of the second keyboard input event by ignoring it or by interpreting the second keyboard input event as something other than the action input. If the second keyboard input is determined to be intentional, then the second keyboard input is accepted as the action input.

Abstract: The disclosure facilitates rerouting data traffic of applications. A failover request is received by a failover application including an application identifier of a main application, the failover application indicating at least one sub-application and a target data source. The failover application selects a configuration data set of the main application based on the application identifier, wherein the selected configuration data set defines an address mask of the target data source associated with the at least one sub-application. The failover application generates failover instructions for activating data traffic routing of the at least one sub-application to the target data source based on the address mask of the target data source. The failover application provides the generated failover instructions to a data traffic manager associated with the main application, whereby data traffic of the at least one sub-application is routed to the target data source by the data traffic manager.

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract: A system that implements a scaleable data storage service may maintain tables in a data store on behalf of storage service clients. The service may maintain data in partitions stored on respective computing nodes in the system. The service may support multiple throughput models, including a committed throughput model and a best effort throughput model. A service request to create a table may specify that requests directed to the table should be serviced under a committed throughput model and may specify the committed throughput level in terms of logical service request units. The service may reserve low-latency storage and other resources sufficient to meet the specified committed throughput level. A client/user may request a modification to the committed throughput level in anticipation of workload changes, such as an increase or decrease in traffic or data volume. In response, the system may increase or decrease the resources reserved for the table.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: The present invention relates to a method for verifying a partitioning configuration, between consuming elements (13), of resources (14) of an electronic module (12), each resource (14) having a capacity and being divisible into segments, the method comprising: verifying the compliance with a set of partitioning rules, according to which: the sum of the unitary capacities of the resource segments allocated for each resource (14) is less than the capacity of said resource (14), only the resource segments previously defined can be allocated to distinct consuming elements (13), the use of resource segments by a consuming element (13) is limited to the resource segments allocated to said consuming element (13), the partitioning configuration being considered valid when the set of partitioning rules is respected, exploiting the module (12) with the partitioning configuration.

Abstract: A memory controller includes an interface circuit and a control circuit. The interface circuit is configured to communicate with a host device. When the control circuit finishes executing N commands from the host device, the memory controller notifies the host device to release corresponding memory in the host device corresponding to the N commands, and N is a positive integer. The control circuit compares a data transmission speed of the interface circuit with a predetermined value to generate a comparison result, and the control circuit adjusts a value of N based on the comparison result.

Abstract: Apparatuses and methods are described that provide for a mechanism for allocating physical device memory for one or more virtual functions. In particular, a memory allocating framework is provided to utilize device memory more efficiently by mapping at least one target location of the physical memory in a Base Address Register (BAR) associated with the virtual function from a plurality of available target locations based on an allocation request. The memory allocating framework is further configured to compare an indication associated with the requesting virtual function to an identifier of the requested target location. Moreover, the memory allocating framework is further configured to allow the simultaneous use of more than one virtual function at a time while providing isolation between multiple virtual functions.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request for data. A number of storage devices of a plurality of storage devices in a Mapped RAID group that will be used to process the I/O request may be determined. It may be determined that each storage device of the number of storage devices in the Mapped RAID group that will be used to process the I/O request lacks a respective threshold number of credits to process the I/O request. It may be determined whether a cache associated with the Mapped RAID group allows a user I/O queue. If the cache allows the user I/O queue, a user I/O may be placed in the user I/O queue. If the cache does not allow the user I/O queue, the I/O request may be failed.

Abstract: Various examples described herein provide for a management controller that includes a virtual universal serial bus (USB) host controller that can emulate an actual USB host controller to a central processor. A particular endpoint from a number of endpoints is associated with a virtual USB device that is coupled to the virtual USB host controller. The particular endpoint is to refer to a location in a management memory.

Abstract: A computer-implemented method, computer program product and computing system for: allowing a third-party to select a training routine for a specific attack of a computing platform, thus defining a selected training routine; analyzing the requirements of the selected training routine to determine a quantity of entities required to effectuate the selected training routine, thus defining one or more required entities; generating one or more virtual machines to emulate the one or more required entities; and generating a simulation of the specific attack by executing the selected training routine.

Abstract: Wireless restricted peripheral sessions are described herein. In a wireless restricted peripheral session, a mobile device has wireless access to peripheral devices and associated resources of a computing device but is restricted from accessing other resources of the computing device (such as files or applications unrelated to the peripheral devices). The mobile device can then receive input provided through a keyboard or mouse associated with the computing device, for example, and can provide information for display on a monitor associated with the computing device. A wireless restricted peripheral session can be established through a variety of approaches that can include the use of hardware, firmware, software, and/or virtual machine sessions. Wireless restricted peripheral sessions allow a visitor with a mobile device to work using peripheral devices of an organization's computer in a secure manner.

Abstract: Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command.

Abstract: Methods and systems for resource usage metric grading are disclosed. In one embodiment, an exemplary method comprises receiving a request to assign a first role to at least one virtual server; configuring the virtual server to associate the first role with a first resource of the virtual server; modifying a database to include an identifier associated with the virtual server and an identifier of the first role assigned to the virtual server; receiving, from the virtual server, indications of resource usage for a plurality of roles; calculating an efficiency metric associated with the first role, the efficiency based on resource usage associated with the first role and resource usage associated with the plurality of roles; modifying a user interface element for presentation on a web page to include the calculated efficiency metric for the first role; receiving a request from a user; and delivering the web page.

Abstract: Systems and methods for wireless enabled security in relation to a storage drive are described. In one embodiment, the systems and methods may include receiving, at a storage drive, a request from a host of the storage drive. In some cases, the request may be received via a wired connection between the storage drive and the host. In some embodiments, the systems and methods may include determining whether the request is flagged by the host as a secure connection request, processing the request upon determining the request is not flagged as a secure connection request, and establishing a wireless connection with the host upon determining the request is flagged by the host as a secure connection request.

Abstract: Hardware mechanisms are provided for performing hardware based access control of instructions to data. These hardware mechanisms associate an instruction access policy label with an instruction to be processed by a processor and associate an operand access policy label with data to be processed by the processor. The instruction access policy label is passed along with the instruction through one or more hardware functional units of the processor. The operand access policy label is passed along with the data through the one or more hardware functional units of the processor. One or more hardware implemented policy engines associated with the one or more hardware functional units of the processor are utilized to control access by the instruction to the data based on the instruction access policy label and the operand access policy label.

Abstract: Systems, methods, and computer readable media to encode and execute an indirect command buffer are described. A processor creates an indirect command buffer that is configured to be encoded into by a graphics processor at a later point in time. The processor encodes, within a command buffer, a produce command that references the indirect command buffer, where the produce command triggers execution on the graphics processor of a first operation that encodes a set of commands within the data structure. The processor also encodes, within the command buffer, a consume command that triggers execution on the graphics processor of a second operation that executes the set of commands encoded within the data structure. After encoding the command buffer, a processor commits the command buffer for execution on the graphics processor.

Abstract: A method is disclosed for changing data within a solid state drive without using a host interface, comprising issuing a write buffer command with a code to the solid state drive, receiving the code at the solid state drive, storing the code at the solid state drive, transmitting a command to run the code at the solid state drive, running the code with a processor in a virtual machine arranged within the solid state drive, wherein the running of the code alters data within the solid state drive and altering at least one memory arrangement in the solid state drive such that the memory arrangement records the altered data.

Abstract: A storage device including a nonvolatile memory device including memory blocks and a controller connected with the nonvolatile memory device through data input and output lines and a data strobe line may be provided. The nonvolatile memory device and the controller may be configured to perform training on the data input and output lines by adjusting a delay of a data strobe signal sent through the data strobe line and adjust delays of the data input and output lines based on the training result.

Abstract: A memory system may include: a memory device including a plurality of memory dies suitable for storing data; and a controller operatively coupled to the memory dies of the memory device via a plurality of channels, the controller may be suitable for checking the plurality of the channels, selecting independently best transmission channels and best reception channels among the plurality of the channels according to states of the channels, requesting performing of command operations corresponding to the commands through the best transmission channels to the memory dies, and receiving performance results of the command operations through the best reception channels from the memory dies.

Abstract: An example hardware accelerator in a computing system includes a bus interface coupled to a peripheral bus of the computing system; a lock circuit coupled to the bus interface; and a plurality of kernel circuits coupled to the lock circuit and the bus interface; wherein the plurality of kernel circuits provide lock requests to the lock circuit, the lock requests for data stored in system memory of the computing system; wherein the lock circuit is configured to process the lock requests from the plurality of kernel circuits and to issue atomic transactions over the peripheral bus through the bus interface based on the lock requests.

Abstract: A cooking management system is described that identifies a customer and orders a product for the customer based at least on current temporal data. The cooking management system identifies customers associated with previous product requests that occurred during a predetermined range of time based at least on a comparison of current temporal data with temporal data associated with the previous product requests. The cooking management system causes presentation of identifiers of the identified customers on a display. Responsive to determining that the identifier for a particular customer has been selected, the cooking management system automatically causes a cooking device to prepare a product for the particular customer based at least on customer data associated with the particular customer.

Abstract: An inter-process signaling system and method support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

Abstract: Examples described herein relate to a system consistent with the disclosure. For instance, the system may comprise a memory resource, a processing resource, and a database to collect command code information for a command line interface of a client device included in a plurality of client devices, analyze the command code information, modify a command code based on the command code information, and send the modified command code to of the plurality of client devices to cause a modified output responsive to execution of the command code on the plurality of client device.

Abstract: In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, determines a backlog of the respective channel controller in accordance with pending commands in one or more command queues, receives power credits allocated by the storage controller, based at least in part on the backlog of the respective channel controller, and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received power credits. For example, limiting execution includes deferring execution of a respective command in accordance with a determination that executing the respective command would require power credits in excess of power credits available in the respective channel controller.

Abstract: A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least three of the above components are integrated with each other.

Abstract: A system and method provide for the selective authorization and admission of a client into a data sharing session with a host. A host may select one or more clients into the sharing session based on the proximity of the clients. When a client is selected, an identifier is provided from the client device to the host device, for example, utilizing an optical identifier such as a bar code or an audible identifier such as an encoded sound. The identifier is then utilized to establish a link between the client and the host. In this fashion any number of client devices may be selectively admitted into the sharing session in a quick and easy process enabling security for the host and anonymity for the client.

Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.

Abstract: An interface superpipe is implemented in a filesystem. A filesystem in a kernel, receives a command to open a file, the command issued in the execution of a process in an application. The file is determined to be on an interface disk. It is determined that a context does not exist for the process and, in response, an adapter queue is allocated for the process in a kernel memory and mapped into a process address space associated with the process. The context information of the process is saved in the kernel memory. The filesystem may be part of a system further comprising a processor, a storage, an interface adapter in communication with the storage and sharing a memory space with the processor, and an application in communication with the filesystem.

Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

Abstract: Systems and methods for using distributed Universal Serial Bus (USB) host drivers are disclosed. In one aspect, USB packet processing that was historically done on an application processor is moved to a distributed USB driver running in parallel on a low-power processor such as a digital signal processor (DSP). While a DSP is particularly contemplated, other processors may also be used. Further, a communication path is provided from the low-power processor to USB hardware that bypasses the application processor. Bypassing the application processor in this fashion allows the application processor to remain in a sleep mode for longer periods of time instead of processing digital data received from the low-power processor or the USB hardware. Further, by bypassing the application processor, latency is reduced, which improves the listener experience.

Abstract: An Input/Output (I/O) adapter device is provided. The I/O adapter device comprises: a device interface configured to communicate with a first device and a second device communicatively coupled to the I/O adapter device; a host interface configured to support communication with a frontend driver of a host device via a software interface of the host device; a first emulated backend driver configured to communicate with the frontend driver through the host interface using the software interface and to communicate with the first device to provide the frontend driver with access to the first device; and a second emulated backend driver configured to communicate with the frontend driver through the host interface using the software interface and to communicate with the second device to provide the frontend driver with access to the second device.

Abstract: This computer system includes: at least one computer having a memory and a plurality of CPU cores; and a storage sub device having a plurality of logical storage units configured using storage devices. In the computer, a plurality of queues are configured in the memory, and at least one of the plurality of CPU cores is assigned to each of the plurality of queues. The queue is enqueued with an I/O command dispatched from a CPU core, to which the queue is assigned, to a logical storage unit. The computer system has access control information including information concerning whether to accept or refuse access from each queue to each logical storage unit.

Abstract: Methods, techniques, computer program products, apparatus, devices, etc., used in connection with DSL Management Interfaces, significantly improve the management capabilities of a DSL network and/or improve testing relating to DSL equipment and services by permitting better control and operation of a DSL system, including implementation of timestamping for more accurate measurement, monitoring and control of a system. Timestamping further allows customized data collection techniques, where a DSL line can be measured or monitored at intervals whose frequency depends on the line's stability. Moreover, data parameter read and control parameter write operations are presented in conjunction with the use of timestamping. Also, control and operation of a DSL system is enhanced by implementing bit-loading that minimizes, eliminates or otherwise mitigates the amount by which the SNR margin per tone exceeds a maximum SNR margin quantity, where such bit-loading can be selected through an appropriate interface.