Abstract: A method of processing a network request and response includes: merging a plurality of requests to obtain a merged request; transmitting the merged request to a server side; detecting a current status identification of the merged request; when the status indicated by the current status identification shows that data is transferring, receiving resource data corresponding to each request in the merged request and returned by the server side, and detecting the received resource data and obtaining a boundary identification contained in the received resource data; extracting and processing the resource data corresponding to each request in the merged request one by one according to the obtained boundary identification; and when the status indicated by the current status identification shows that the data transferring is completed, stopping receiving the resource data.

Abstract: A system and method for configuring a filter object for a controller area network is disclosed. The method includes determining, by a processor, a plurality of message identifiers of messages that are to be captured by a filter object. The method also includes performing factorization of a function that represents the plurality of message identifiers to generate a simplified function. The method also includes configuring at least one filter object based on the generated simplified function.

Abstract: Systems and methods presented herein provide a controller that is operable to monitor a plurality of background commands to a storage device over a pre-determined period of time and to determine how often each of the background commands is issued during the pre-determined period of time. The controller is further operable to establish a time interval for each of the background commands, and to issue each of the background commands at their respective time intervals.

Abstract: Various embodiments of a microprocessor include a scoreboard implementation that directs the microprocessor to the location of data values. For example, the scoreboard may include individual bits that instruct the microprocessor to retrieve the data from a re-order buffer, retire queue, result bus, or register file. As a first step, the microprocessor receives an instruction indicating a process that requires data from one or more source registers. Instead of automatically retrieving the data from the register file, which is a costly process, the microprocessor may read the scoreboard to determine whether the needed data can be more cost-effectively retrieved from the re-order buffer, retire queue, or result busses. Therefore, the microprocessor can avoid costly data retrieval procedures. Additionally, the scoreboard implementation enables the microprocessor to handle limited out-of-order instructions, which improves overall performance of the microprocessor.

Abstract: The disclosed embodiments provide a system that operates a computer system. During operation, the system detects a first change in a setting associated with a first computing environment executing on the computer system, wherein the first change is associated with at least one of an input/output (I/O) device setting, a regional setting, a network setting, a power setting, and a display setting. Next, the system propagates the first change to one or more other computing environments executing on the computer system.

Abstract: A cache controller determines replacement priority for cache lines at a cache based on data stored at non-cache buffers. In response to determining that a cache line at the cache is to be replaced, the cache controller identifies a set of candidate cache lines for replacement. The cache controller probes the non-cache buffers to identify any entries that are assigned to the same memory address as a candidate cache line and adjusts the replacement priorities for the candidate cache lines based on the probe responses. The cache controller deprioritizes for replacement cache lines associated with entries of the non-cache buffers.

Abstract: A microcontroller includes a program memory, data memory, central processing unit, at least one register module, a memory management unit, and a transport network. Instructions are executed in one clock cycle via an instruction word. The instruction word indicates the source module from which data is to be retrieved and the destination module to which data is to be stored. The address/data capability of an instruction word may be extended via a prefix module. If an operation is performed on the data, the source module or the destination module may perform the operation during the same clock cycle in which the data is transferred.

Abstract: A device includes multiple communication interfaces configured to send and receive data over multiple communication paths. The device also includes multiple input/output (I/O) channels configured to communicate with multiple field devices. The device further includes at least one processing device configured to process at least some of the data and control at least one of the field devices based on the processed data. The device may also include an intrinsic safety barrier electrically separating the communication interfaces and the I/O channels. The communication interfaces may include at least one first interface configured to communicate over one or more first communication paths with at least one component of an industrial control system and at least one second interface configured to communicate over one or more second communication paths with at least one other device that is configured to communicate with additional field devices.

Abstract: A controller of a storage device analyzes data comprising a plurality of previous host idle durations to identify a trend in the previous host idle duration. The controller projects a next host idle duration based on the trend. The controller determines a transition from a storage device active state to a next storage device sleep state or a transition from a storage device sleep state to a next storage device active state based on the projected host idle duration.

Abstract: An apparatus, method, and program product are disclosed for loading a program during boot of a device. A monitor module collects usage data for each of one or more programs executing on a device. The usage data for each program comprising an amount of time that the program was used and a schedule of when the program was used. A priority module assigns a boot priority to each of the one or more programs based on the amount of time that each program was used. A boot module selects one or more programs to load during a boot period for the device based on each program's usage schedule. The one or more selected programs are loaded according to each selected program's boot priority.

Abstract: A system and method for capturing automation data from an automated system uses a multi-array populated by an automation controller with automation data including timing data defined by a controller clock. The multi-array includes at least one member corresponding to a sensor sensing a state of the member and a plurality of member-defined data elements, which may correspond to a start time and end time of the member state. Automation data is captured from the controller multi-array by a computing device in communication with the controller including a first data table corresponding with the controller multi-array for efficient collection of the automation data from the controller memory, and a second data table for associating each data element with its defining member and storing the associated data in a historical database which may be used for analysis of cycle time data of a member, device or operation of the automated system.

Abstract: Systems are provided for logging transactions in heterogeneous networks that include a combination of one or more instrumented components and one or more non-instrumented components. The instrumented components are configured to generate impersonated log records for the non-instrumented components involved in the transaction processing hand-offs with the instrumented components. The impersonated log records are persisted with other log records that are generated by the instrumented components in a transaction log that is maintained by a central logging system to reflect a complete flow of the transaction processing performed on the object, including the flow through the non-instrumented component(s).

Abstract: Example methods are provided to perform persistent reservation emulation in a shared virtual storage environment that includes a first host supporting a first node and a second host supporting a second node. One example method may comprise detecting a command issued by a first node to command issued by a first node to update information relating to a reservation or registration associated with a virtual disk, and updating persistent reservation information associated with the virtual disk to indicate that the command has been issued by the first node. The method may also comprise determining that the second node either has acknowledged the updated persistent reservation information, or has not acknowledged the updated persistent reservation information within a time interval. The method may further comprise updating the persistent reservation information based on the command.

Abstract: A storage server comprises a plurality of solid state drives (SSDs), a plurality of input/output (I/O) controllers, a switch, and a management controller. A first SSD of the plurality of SSDs comprises a plurality of queue pairs. The management controller is to allocate a first subset of the plurality of queue pairs in the first SSD to a first I/O controller, wherein the first I/O controller is to use the first subset of the plurality of queue pairs to read from and write to the first SSD. The management controller is further to allocate a second subset of the plurality of queue pairs in the first SSD to a second I/O controller, wherein the second I/O controller is to use the second subset of the plurality of queue pairs to read from and write to the first SSD.

Abstract: A universal serial bus (USB) testing method includes selecting a selected test mode from test modes, creating a USB communication link between a USB device and a testing fixture board, generating, by the testing fixture board, a test-triggering instruction corresponding to the selected test mode according to the selected test mode, sending the test-triggering instruction to the USB device with the USB communication link, generating, by the USB device, a testing packet corresponding to the selected test mode according to the test-triggering instruction, and outputting the testing packet repeatedly from at least one external port of the USB device.

Abstract: Provided are a memory device and a memory system including the same. The memory device may include a first memory rank including at least one first memory chip, a memory controller configured to provide a command to the first memory rank, at least one data buffer configured to buffer data input to the at least one first memory chip or being output from the at least one first memory chip, and a second memory rank connected to the first memory rank and comprising at least one second memory chip. The first memory rank may provide training data and a data strobe signal to the second memory rank based on a data training command from the memory controller without the training data and the data strobe signal passing through the data buffer. The second memory rank may determine a delay of the data strobe signal based on the training data being detected by the second memory rank.

Abstract: A downlink communication data DND from a main control circuit section to a combination control circuit section is divided into first and second downlink data, high-speed communication using a downlink clock signal and a transmission start instruction signal is performed, a high-speed load which has been directly driven from the main control circuit section is indirectly driven at high speed from the combination control circuit section by the first downlink data, a low-speed analog input signal ANL which has been indirectly inputted to the combination control circuit section is inputted to a specific input channel of a multi-channel converter through an indirect multiplexer, and channel selection is made by the downlink communication data.

Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.

Abstract: A command from a host is received via a port of a storage system. The port is assigned a current port revision identifier. The current port revision identifier of the port is associated with the command. Responsive to a status change associated with the port, an updated port revision identifier is assigned to the port to replace the current port revision identifier of the port and execution of the command is aborted responsive to determining that the current port revision identifier associated with the command is different than the updated port revision identifier of the port.

Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.

Abstract: When mounting hardware which is coupled to another portion by a plurality of paths with different applications, despite the hardware being a single device, and a failure occurs in any of the paths, there is a risk that the failure may propagate to other components unless the other paths are also blocked. In order to solve the problem described above, in a storage apparatus to which a device coupled by a plurality of coupling paths with different applications can be mounted, the present invention determines a block range at the time of an occurrence of a failure to be a device and a plurality of coupling paths coupled to the device, manages the block range, and upon an occurrence of a failure, executes failure handling which involves blocking an appropriate block range determined in advance by referring to the information.

Abstract: Techniques herein are for accessing non-materialized blocks of a sparse file. A method involves a storage system receiving a storage command to access a sparse file. A combined content of a set of materialized blocks and a header that identifies one or more non-materialized blocks is assembled. The combined content does not comprise a content of the one or more non-materialized blocks. Responsive to the assembling, the combined content is transferred between the storage system and a computer system.

Abstract: Quality of service is provided to prioritized VMs and applications, based on the varied quality of different shared computing resources. Each VM or application has an associated priority. A quality rating is dynamically assigned to each shared computing resource. Requests for shared computing resources made by specific VMs or applications are received. For each specific received request, the current priority of the requesting VM or application is identified. In response to each received request, a specific shared computing resource is assigned to the specific requesting VM or application. This assignment is made based on the current priority of the requesting VM or application and the current quality rating of the shared computing resource, thereby providing quality of service to the requesting VM or application corresponding to its current priority.

Abstract: Systems and methods are disclosed for probabilistic aging command sorting, including adjusting an execution order for a command based on a probability of the command reaching a time out threshold. Various example embodiments are directed to selecting a command for execution from a queue of commands awaiting execution, in which the commands have non-uniform attributes influencing their selection and a time limit within which to execute them. In some embodiments, an apparatus may comprise a circuit configured to calculate a first estimated access time to execute a selected command from a command queue, modify the first estimated access time based on a probability of the selected command reaching a time-out age threshold to determine a time out-adjusted access time, and execute the selected command in an order based on the time out-adjusted access time.

Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.

Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.

Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

Abstract: The present invention provides a method and apparatus for scheduling block device input/output requests, which relates to the field of computer memories. The method comprises: generating a block device input/output request firstly, wherein the block device input/output request comprises a write operation request; then judging whether the generated block device input/output request can be combined with block device input/output requests in a request queue; and if the generated block device input/output request cannot be combined with block device input/output requests in a request queue, sending the generated block device input/output request to a foremost position of the request queue when a destination device of the generated block device input/output request is a solid state disk or an SD card. By means of the method and apparatus for scheduling the block device input/output requests, the efficiency of write operation is improved.

Abstract: Provided are methods and adapter devices for buffering write transactions directed to a large space. In various implementations, an adapter device may include a sequential address buffer and a memory. A region of the memory may be configured as a data block, which may be associated with an address range. The address range may correspond to a region of an address space of a target device. The adapter device may be configured to receive a write transaction, the write transaction having an address and data. The adapter device may further write the address to the sequential address buffer. The adapter device may further determine that the address is within the address range, and to write the data to the data block. The adapter device may further, upon the occurrence of an event, write the data from the data block to the region of the address space of the target device.

Abstract: A system can include a plurality of first server modules interconnected to one another via a communication network, each first server module including a first switch, at least one main processor, and at least one computation module coupled to the main processor by a bus, each computation module including a second switch, and a plurality of computation elements; wherein the second switches of the first server modules form a switching plane for the ingress and egress of network packets independent of any main processors of the first server modules.

Abstract: A computer program product, system, and computer-executable method for managing meta volumes in a data storage system, the computer program product, system, and computer-executable method comprising receiving one or more data storage characteristics, analyzing the one or more data storage characteristics, based on the analyzing, creating a policy responsive to the data storage characteristics, and allocating a meta volume based on the policy.

Abstract: A cooking management system is described that identifies a customer and orders a product for the customer based at least on current temporal data. The cooking management system identifies customers associated with previous product requests that occurred during a predetermined range of time based at least on a comparison of current temporal data with temporal data associated with the previous product requests. The cooking management system causes presentation of identifiers of the identified customers on a display. Responsive to determining that the identifier for a particular customer has been selected, the cooking management system automatically causes a cooking device to prepare a product for the particular customer based at least on customer data associated with the particular customer.

Abstract: According to an embodiment, a memory device includes a nonvolatile memory and a controller. The controller receives, from a host device, a write request for writing data in the nonvolatile memory, and then performs data writing based on the write request. When a writing order confirmation request, which is issued for confirmation of fact that data writing is performed based on one or more of the write requests that are already sent, is received from the host device, the controller performs data writing based on the write requests received before receiving the writing order confirmation request and then sends to the host device a response with respect to the writing order confirmation request.

Abstract: Examples may include techniques to use chip select signals for a dual in-line memory module (DIMM). In some examples, the chip select signals are used with either a first encoding scheme for clock enable (CKE) functionality or a second encoding scheme for on-die termination (ODT) functionality to enable memory devices on the DIMM to be accessed or controlled according to commands received with the chip select signals.

Abstract: A network device stores information associated with a packet in a queue. The network device sends an interrupt to a host to notify the host of completion of processing the packet. A Memory-Mapped Input/Output (MMIO) write transaction is received that includes a pointer update associated with the queue and an interrupt unmasking value. The pointer is updated and the interrupt is unmasked based on receiving the single MMIO write transaction.

Abstract: Described herein are systems and methods for improving performance of single-frequency (single-point, single-bin) discrete Fourier transform (DFT) detectors by elimination of systematic errors from the detector output. Calibration procedures known in the art for practical implementations of such detectors do not provide adequate reduction of these systematic errors thus reducing utilization of these detectors in useful applications and products. The described methods, systems and devices allow such detectors to measure both DC and AC signals and, in latter case, considerably expand the operation frequency range without any additional hardware. These methods enable wide practical applications of DFT detectors across diverse variety of fields: from monitoring health of mechanical structures and fluid properties to impedimetric measurements in electrochemistry, monitoring of corrosion and bioimpedance.

Abstract: A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.

Abstract: Systems and methods for utilization of notification or ordering commands are disclosed that can enable more efficient processing of flush requests from software programs and increase data consistency in storage devices. A data storage device or system may include a non-volatile memory, a memory comprising a data cache and a controller. The controller may be configured to receive an ordering command requesting commitment to the non-volatile memory of cached data items associated with a first identifier prior to commitment of cached data items associated with a second identifier, and to delay commitment of the second data item to the non-volatile memory until commitment of the first data item to the non-volatile memory, based at least in part on the ordering command. The controller may be further configured to select data items from the data cache for commitment to the non-volatile memory in accordance with native command queuing (NCQ).

Abstract: A numerical control apparatus includes an API interface section that accepts invocation of an API function, an API control section that executes the process of the API function based on the invocation of the API function, and processing period estimation means for estimating if the execution of the API function is completed in a predetermined period, and the API control section does not execute but terminates the process of the API function when the processing period estimation means estimates that the execution of the API function will not be completed in the predetermined period.

Abstract: Parallel processing files on a distributed file system, responds to a request to process the file, by partitioning the file into a set of predetermined sized blocks by a single coordinator and assigns blocks to a reader in a set of readers. Block assignments are recorded to a control table accessible to all readers. The set of readers search the control table for a row assigned to a respective reader. Responsive to locating the row, the respective reader changes a state of the row to in progress updating an associated timestamp. The respective reader scans the control table for an available set of the blocks, when all blocks currently assigned are exhausted and dynamically re-assigns an available block from another owning reader to itself and changes ownership to itself. When no rows are available, the respective reader completes processing and returns an end of file indication to the single coordinator.

Abstract: A data storage device which exchanges multi-stream data with a host includes a nonvolatile memory device; a buffer memory configured to temporarily store data to be stored in the nonvolatile memory device or data read from the nonvolatile memory device; and a storage controller configured to receive from the host an access command for accessing segments of the multi-stream data, the accessing including reading the segments of the multi-stream data from or writing the segments of the multi-stream data to the nonvolatile memory device, wherein the storage controller is configured to store the access-requested segments in the buffer memory, the access-requested segments being the segments of data for which access is requested in the access command, the multi-stream data including a plurality of data streams that correspond respectively to a plurality of multi-stream indexes, the first multi-stream index being one of a plurality of multi-stream indexes.

Abstract: A semiconductor device includes: various types of memories; an interface configured to transmit memory characteristic information of the memories to a host, receive information needed to control operations of the memories from the host, and perform interfacing between the host and the memories; and a controller configured to control operations of the memories in response to information received from the host, and control an operation of the interface.

Abstract: A mechanism is described for facilitating dynamic pipelining of workload executions at graphics processing units on computing devices. A method of embodiments, as described herein, includes generating a command buffer having a plurality of kernels relating to a plurality of workloads to be executed at a graphics processing unit (GPU), and pipelining the workloads to be processed at the GPU, where pipelining includes scheduling each kernel to be executed on the GPU based on at least one of availability of resource threads and status of one or more dependency events relating to each kernel in relation to other kernels of the plurality of kernels.

Abstract: A configurable storage drive includes multiple types of storage such as magnetic media and solid state storage and can implement any of multiple valid configuration modes. A user of the configurable storage drive can select the particular configuration mode so desired to achieve, for example, a desired number of input and output transactions per second. In one example, a service provider network includes multiple such configurable storage drives and customers of the service provider can configure their respective storage drives independently and differently from the other service provider customers. The service provider can opt to provide for selection to its customers all or only a subset of the possible valid configuration modes for selection by the customers. For example, storage drive configuration modes that would result in higher power consumption levels by the storage drives might not be offered to the customers.

Abstract: Approaches are described for updating code and/or instructions in one or more computing devices. In particular, various embodiments provide approaches for updating the microcode of one or more processors of a computing device without requiring a restart of the computing device and without disrupting the various components (e.g., applications, virtual machines, etc.) executing on the computing device. The microcode updates can be performed on host computing devices deployed in a resource center of a service provider (e.g., cloud computing service provider), where each host computing device may be executing a hypervisor hosting multiple guest virtual machines (or other guest applications) for the customers of the service provider.

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

Abstract: An ordering system receives release requests to release packets, where each packet has an associated sequence number, but the system only releases packets sequentially in accordance with the sequence numbers. The system includes a Ticket Order Release Command Dispatcher And Sequence Number Translator (TORCDSNT) and a plurality of Ticket Order Release Bitmap Blocks (TORBBs). The TORBBs are stored in one or more transactional memories. In response to receiving release requests, the TORCDSNT issues atomic ticket release commands to the transactional memory or memories, and uses the multiple TORBBs in a chained manner to implement a larger overall ticket release bitmap than could otherwise be supported by any one of the TORBBs individually. Special use of one flag bit position in each TORBB facilitates this chaining. In one example, the system is implemented in a network flow processor so that the TORBBs are maintained in transactional memories spread across the chip.

Abstract: A storage device, such as a NAND flash device, includes a controller that assigns host read commands to a high priority queue and all other I/O commands including host write commands to a low priority queue. The controller executes any commands in the high priority queue before executing commands in the low priority queue. Block write commands are broken into page write commands that are added to the low priority queue, thereby enabling any host read commands to be interleaved with execution of the page write commands, rather than waiting for completion of a block write command. Coherency between overlapping commands is performed by a host device coupled to the controller such that no checking of coherency is performed by the SSD controller.

Abstract: Techniques are described herein for loading a user-mode component associated with a kernel-mode component based on an asynchronous procedure call (APC) built by the kernel-mode component. The APC is provided to the main thread of a user-mode process while that user-mode process loads, causing the user-mode process to load the user-mode component. The APC also causes allocation of memory at a location adjacent to that of the user-mode process and stores instructions at the allocated memory. The user-mode component then atomically hooks function(s) of the user-mode process, including modifying a single instruction or set of instructions of the function(s) to jump to the allocated memory. When that modified instruction is executed and jumps to the allocated memory, the instructions at the allocated memory request loading of the user-mode component, which receives data from the hooked function. The user-mode component then provides that data to the kernel-mode component.

Abstract: Various example embodiments herein disclose a method of managing input/output (I/O) queues by a Non-Volatile Memory Express (NVMe) controller. The method includes receiving a single command from a host to perform a creation of the I/O queues or deletion of the I/O queues. Further, the method includes processing a queue identifier, a queue size, and combination of the queue identifier and queue size indicated in the single command. Furthermore, the method includes performing the creation of the I/O queues or deletion of the I/O queues, in a host memory.