Buffer Space Allocation Or Deallocation Patents (Class 710/56)
  • Patent number: 12120549
    Abstract: Methods and apparatus configured to obtain a decision-point value, and send, for a logical channel group (LCG) having a quantity of data pending an uplink transmission, a long buffer status report in response to the decision-point value exceeding a threshold value, or a short buffer status report in response to the decision-point value being equal to or less than the threshold value are disclosed. The decision-point value may be a buffer status report-type determinative value, which may be based on a peak power envelope of a wireless communication device, a data transmission rate historically obtained by the wireless communication device, a number of component carriers available for a complete upload of a buffer holding data, a cost function, an amount of data associated with the LCG that is pending the uplink transmission, a type of the wireless communication device, or a latency of communications of the wireless communication device.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: October 15, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Nitin Agarwal, Sitaramanjaneyulu Kanamarlapudi, Joe Thomas, Girish Khandelwal, Deepak Wadhwa, Dinesh Kumar Devineni, Thang Tu, Gangaram Patidar, Talha Patel, Farhad Tavassoli
  • Patent number: 12073873
    Abstract: Exemplary methods, apparatuses, and systems include allotting an initial amount of volatile memory to a write buffer. The write buffer stores batches of data to be written to non-volatile memory. In response to detecting a trigger to update the write buffer configuration, the volatile memory allotted to the write buffer is reduced.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: August 27, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Karl D. Schuh, William Richard Akin
  • Patent number: 12014079
    Abstract: An operation method of a universal flash storage (UFS) host configured to control a UFS device includes configuring a turbo write buffer of the UFS device; sending a first query request UFS protocol information unit (UPIU) including reconfiguration information about the turbo write buffer to the UFS device, during driving the UFS device; and receiving a first response UPIU associated with the first query request UPIU from the UFS device, wherein, the first query request UPIU is a request that causes a size of the turbo write buffer of the UFS device to be changed from a first size to a second size different from the first size.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: June 18, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngjoon Jang, Minji Kim, Seungil Kim, Hyung-Kyun Byun
  • Patent number: 11930500
    Abstract: The present invention relates to a method of transmitting a buffer status report (BSR) by a wireless node in a wireless communication system. In particular, the method includes the steps of: receiving first logical channel group (LCG) configuration information including identities of LCGs from a network; generating the BSR including a LCG field; and transmitting the BSR to the network, wherein a length of the LCG field is configured according to a highest value of the identities of LCGs.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: March 12, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Gyeongcheol Lee, Sunyoung Lee, Seungjune Yi
  • Patent number: 11899936
    Abstract: This application relates to a data transmission circuit, a method, and a storage device. The data transmission circuit includes a delay module and a mode register data processing unit. The delay module delays a first preset time when receiving a mode register read command, and generates delayed read command. The mode register data processing unit is connected to the delay module, and reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: February 13, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Enpeng Gao, Kangling Ji, Zengquan Wu
  • Patent number: 11782851
    Abstract: A method includes determining a traffic pattern of access requests within a queue or a system, or both and dynamically adjusting, within a particular range, a queue depth of the queue based on the determined traffic pattern of access requests to balance bandwidth and latency associated with executing the access requests.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, Kirthi Ravindra Kulkarni, Laurent Isenegger
  • Patent number: 11753026
    Abstract: A vehicle control device includes a plurality of IC units, while maintaining the operational reliability. The vehicle control device includes an IC unit for performing image processing on outputs from cameras; an IC unit for performing recognition processing of an external environment of the vehicle; and an IC unit for performing judgment processing for cruise control of the vehicle. A control flow is provided so as to allow the IC unit to transmit a control signal to the IC units and. The control flow is provided separately from a data flow configured to transmit the output from the cameras, the image data, and the external environment data.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: September 12, 2023
    Assignees: MAZDA MOTOR CORPORATION, NXP B.V.
    Inventors: Masato Ishibashi, Kiyoyuki Tsuchiyama, Daisuke Hamano, Tomotsugu Futa, Daisuke Horigome, Atsushi Tasaki, Yosuke Hashimoto, Yusuke Kihara, Eiichi Hojin, Arnaud Van Den Bossche, Ray Marshall, Leonardo Surico
  • Patent number: 11755241
    Abstract: A storage device includes a buffer memory configured to temporarily store data; a plurality of nonvolatile memory devices; a storage controller circuit configured to generate buffer memory status information by monitoring a status of the buffer memory and operating in a congestion control mode of setting a buffer memory data transmission authority of a nonvolatile memory based on the generated buffer memory status information; and a first interface circuit configured to communicate with the storage controller circuit and the plurality of nonvolatile memory devices, wherein the first interface circuit is connected to a network based on an Ethernet interface.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: September 12, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Junbum Park
  • Patent number: 11697413
    Abstract: A vehicle control device includes: a signal processing IC unit that outputs image processing data; a recognition processing IC unit that performs recognition processing of the external environment of a vehicle to output external environment data obtained through the recognition processing; a judgment processing IC unit that performs judgment processing for cruise control of the vehicle; a power management unit capable of controlling an on or off state of a recognition function of the external environment of the vehicle in the recognition processing IC unit according to the conditions of the vehicle; and a bypass path for enabling data communications from the signal processing IC unit to the judgment processing IC unit without performing the recognition processing of the external environment of the vehicle by the recognition processing IC unit.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: July 11, 2023
    Assignees: MAZDA MOTOR CORPORATION, NXP B.V.
    Inventors: Eiichi Hojin, Kiyoyuki Tsuchiyama, Masato Ishibashi, Daisuke Hamano, Tomotsugu Futa, Daisuke Horigome, Atsushi Tasaki, Yosuke Hashimoto, Yusuke Kihara, Arnaud Van Den Bossche, Ray Marshal, Leonardo Surico
  • Patent number: 11693809
    Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: July 4, 2023
    Assignee: Liquid-Markets-Holdings, Incorporated
    Inventors: Seth Gregory Friedman, Alexis Nicolas Jean Gryta, Thierry Gibralta
  • Patent number: 11675540
    Abstract: A system includes a storage device and a computational storage processor. The storage device includes media. The computational storage processor is configured to, after issuance of a single command from a host device, receive data corresponding to the command, process the data as the data is received using a filter program and provide results data from the processed data.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: June 13, 2023
    Assignee: Seagate Technology LLC
    Inventor: Marc Timothy Jones
  • Patent number: 11516702
    Abstract: The present disclosure disclosed a method of determining a buffer status report (BSR). The method comprises obtaining, by a user equipment (UE) from a buffer, data item to be sent; determining, by the UE, a size of the data item to be sent; determining, by the UE, a minimum number of required logical channel groups (LCGs) based on the data item to be sent; and determining, by the UE, at least one BSR with flexible length based on the size of the data item to be sent and the minimum number of the required LCGs. Information of the at least one BSR with flexible length includes the minimum number of the required LCGs, LCG identifiers (LCG IDs) respectively associated with the minimum number of the required LCGs, and at least one buffer area corresponding to the LCG IDs.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 29, 2022
    Assignee: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Ruyan Wang, Yaping Cui, Dapeng Wu, Puning Zhang, Shushan Si
  • Patent number: 11500589
    Abstract: The present disclosure generally relates to aborting a command efficiently using the host memory buffer (HMB). The command contains pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: November 15, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Judah Gamliel Hahn
  • Patent number: 11477295
    Abstract: A system and method for enhancing operability of client-server computing system is herein disclosed. A system includes a first computing device. The first computing device includes a file type association module. The file type association module determines, as part of a remote computing session, whether to associate a file type with an application program on the first computing device or an application program on a second computing device. The file type association module causes the file type to associate with the application program on one of the first and second computing devices.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: October 18, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael A. Provencher, Kent E. Biggs, Thomas J. Flynn
  • Patent number: 11379151
    Abstract: Aspects of a storage device are provided which use flow control to prevent stalling during processing of read requests for a large read command. A controller of the storage device receives a read command for data from a host device, stores in a queue read requests for a portion of the data, and reads the portion of the data from a memory based on the read requests. The controller may store other read requests in the queue for other portions of the data when a number of read requests in the queue does not meet a threshold. Otherwise, the controller refrains from storing other read requests in the queue for other portions of the data when the number of read requests in the queue meets the threshold. The controller may operate similarly with subsequent sequential commands, but may continue to store read requests in the queue for subsequent random commands.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vishwas Saxena, Abhijit K Rao
  • Patent number: 11360698
    Abstract: An electronic control unit for a vehicle including a nonvolatile memory capable of erasing and writing data electrically and two buffers to acquire, by communication, divided data obtained by dividing a program by predetermined size. Then, in parallel with using the two buffers alternately to receive divided data, the electronic control unit for a vehicle uses one buffer that is not used to receive divided data to write the received divided data into the nonvolatile memory.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 14, 2022
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Yusuke Abe, Koji Yuasa, Toshihisa Arai
  • Patent number: 11341052
    Abstract: A device includes an interconnect and a plurality of devices connected to the interconnect. The plurality of devices includes a first interface connected to the interconnect and a second interface connected to the interconnect. The plurality of devices further includes a first memory bank connected to the interconnect and a second memory bank connected to the interconnect. The plurality of devices further includes an external memory interface connected to the interconnect and a controller configured to establish virtual channels among the plurality of devices connected to the interconnect.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 24, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Matthew David Pierson, Timothy David Anderson, Joseph Zbiciak
  • Patent number: 11315611
    Abstract: A memory system includes a stacked memory device and a controller. The stacked memory device includes a base die and a plurality of memory dies stacked on the base die. Each of the plurality of memory dies has a plurality of channels, and the base die is configured to function as an interface for transmitting signals and data of the pluralities of channels. The controller controls the stacked memory device such that first and second data move control operations are sequentially performed to transmit moving data from a target channel of the pluralities of channels to a destination channel of the pluralities of channels. The first data move control operation is performed to store the moving data in the target channel into the base die, and the second data move control operation is performed to write the moving data stored in the base die into the destination channel.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 11284301
    Abstract: Systems and methods are provided for flow control in a wireless communication system. In certain aspects, an apparatus for wireless communications comprises an interface configured to receive, from a wireless node, one or more parameters specifying a memory at the wireless node, and an indication of an amount of free memory space in the memory at the wireless node. The apparatus also comprises a processing system configured to determine a number of data units to be transmitted to the wireless node based on the indication of the amount of free memory space and the one or more parameters, wherein the interface is further configured to output data units for transmission to the wireless node, wherein a number of the data units output for transmission to the wireless node equals the determined number of data units.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 22, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Solomon Trainin, Ran Hay, Alecsander Petru Eitan
  • Patent number: 11169714
    Abstract: Systems, methods, and media for efficient file replication are provided herein. According to some embodiments, exemplary methods may include detecting a write operation occurring within an operating system of the computing system, identifying block parameters for the write operation, as well as one or more of buffering and batching the write operation, and transmitting the write operation to a replication receiver system.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: November 9, 2021
    Assignee: eFolder, Inc.
    Inventors: Kong Li, Robert Petri, Nitin Parab
  • Patent number: 11144467
    Abstract: Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Yanru Li, Ali Taha, Chia-Hung S. Kuo
  • Patent number: 11079938
    Abstract: A system comprises a plurality of computing devices that are communicatively coupled via a network and have a file system distributed among them, and comprises one or more file system request buffers residing on one or more of the plurality of computing devices. File system choking management circuitry that resides on one or more of the plurality of computing devices is operable to separately control: a first rate at which a first type of file system requests (e.g., one of data requests, data read requests, data write requests, metadata requests, metadata read requests, and metadata write requests) are fetched from the one or more buffers, and a second rate at which a second type of file system requests (e.g., another of data requests, data read requests, data write requests, metadata requests, metadata read requests, and metadata write requests) are fetched from the one or more buffers.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 3, 2021
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel, Kanael Arditti, Tomer Filiba
  • Patent number: 11026117
    Abstract: A method for transmitting signals by a user equipment (UE) in a wireless communication system is disclosed. The method comprises skipping buffer status report (BSR) triggering procedure when a logical channel belongs to a specific logical channel group; receiving an uplink grant allowed to be used for transmission of buffer size information of the specific logical channel group; and transmitting buffer size information of the specific logical channel group based on the uplink grant.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: June 1, 2021
    Assignee: LG Electronics Inc.
    Inventors: Sunyoung Lee, Jayeong Kim, Eunjong Lee
  • Patent number: 10970085
    Abstract: A method and apparatus of a device for resource management by using a hierarchy of resource management techniques with dynamic resource policies is described. The device terminates several misbehaving application programs when available memory on the device is running low. Each of those misbehaving application programs consumes more memory space than a memory consumption limit assigned to the application program. If available memory on the device is still low after terminating those misbehaving application programs, the device further sends memory pressure notifications to all application programs. If available memory on the device is still running low after sending the memory pressure notifications, the device further terminates background, idle, and suspended application programs. The device further terminates foreground application programs when available memory on the device is still low after terminating the background, idle, and suspended application programs.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: April 6, 2021
    Assignee: Apple Inc.
    Inventors: Andrew D. Myrick, Dmitriy B. Solomonov, Lionel D. Desai
  • Patent number: 10966116
    Abstract: To provide a technology of quickly transmitting a buffer status for a reduction of uplink transmission latency. Provided is a user equipment including: a transmission and reception unit that transmits and receives radio signal to and from a base Station; and a buffer status report transmission unit that transmits, to the base station, a speculative buffer status report indicating a buffer status that is expected in a subsequent subframe.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 30, 2021
    Assignee: NTT DOCOMO, INC.
    Inventors: Shimpei Yasukawa, Satoshi Nagata
  • Patent number: 10936480
    Abstract: Intelligent memory brokering for multiple process instances, such as relational databases (e.g., SQL servers), reclaims memory based on value, thereby minimizing cost across instances. An exemplary solution includes: based at least on a trigger event, determining a memory profile for each of a plurality of process instances at a computing node; determining an aggregate memory profile, the aggregate memory profile indicating a memory unit cost for each of a plurality of memory units; determining a count of memory units to be reclaimed; identifying, based at least on the aggregate memory profile and the count of memory units to be reclaimed, a count of memory units to be reclaimed within each process instance so that a total cost is minimized to reclaim the determined count; and communicating, to each process instance having identified memory units to be reclaimed, a count of memory units to be reclaimed within the process instance.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Manoj Syamala, Vivek Narasayya, Junfeng Dong, Ajay Kalhan, Shize Xu, Changsong Li, Pankaj Arora, Jiaqi Liu, John M. Oslake, Arnd Christian König
  • Patent number: 10901892
    Abstract: Systems, methods and/or devices are used to enable locality grouping during garbage collection of a storage device. In one aspect, the method includes, at a storage controller for the storage device: performing one or more operations for a garbage collection read, including: identifying one or more sequences of valid data in a source unit, wherein each identified sequence of valid data has a length selected from a set of predefined lengths; and for each respective sequence, transferring the respective sequence to a respective queue of a plurality of queues, in accordance with the length of the respective sequence; and setting a global flag to flush all open queues; and performing one or more operations for a garbage collection write, including: identifying open respective queues for writing to a destination unit; and writing from the open respective queues to the destination unit.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: January 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Neil D. Hutchison, Steven Theodore Sprouse, Shakeel I. Bukhari
  • Patent number: 10892879
    Abstract: Apparatus and method are provided to enhance scheduling request to multiple schedulers with inter base station carrier aggregation. In one novel aspect, the UE monitors and detects one or more SR triggering event. The UE selects one or more base stations based on predefined criteria and sends the SR to the selected one or more base stations. In one embodiment, at least one radio bearer of the UE is associated with multiple cell groups (CGs) in different base stations with association priorities. The association priorities may be configured by the network, derived based on predefined UE configurations, derived from load information received by the UE, or derived from radio measurements. In one novel aspect, the UE upon detecting SR failure triggered on a triggering radio bearer, sends SR failure indication to a RRC layer or associates the triggering radio bearer with a different base station.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: January 12, 2021
    Assignee: HFI Innovation INC.
    Inventors: Yuanyuan Zhang, Chia-Chun Hsu, Per Johan Mikael Johansson
  • Patent number: 10832727
    Abstract: A setting unit is configured to set first write processing for writing second data in a hard disk, or second write processing for writing the second data in the hard disk and reading data that is written by writing of the second data, and a change unit is configured to change the write processing set in the setting unit. The change unit changes the write processing set in the setting unit from the first write processing to the second write processing, based on determination that the first data is greater than or equal to a threshold by a determination unit.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 10, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ryohei Yamada
  • Patent number: 10819612
    Abstract: Computer-implemented systems and methods automatically identify computers that act as load balancers on a digital communications network, using data collected from one or more computers on that network. Once a load balancer has been identified, the communications between two hosts may be connected across the identified load balancer, thereby making it possible to better analyze the behavior of hosts and applications on that network.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 27, 2020
    Assignee: Zscaler, Inc.
    Inventors: John O'Neil, Thomas Evan Keiser, Jr., Peter Smith
  • Patent number: 10764407
    Abstract: Aggregate socket resource management is presented herein. A system can comprise a processor; and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising: determining a present aggregate amount of data associated with processing requests from a socket; setting a defined aggregate data limit on the present aggregate amount of data; and in response to determining changes in a difference between the defined aggregate data limit and the present aggregate amount of data, modifying a defined data capacity limit on a data capacity of a receive buffer of the socket. In an example, the determining of the changes in the difference between the defined aggregate data limit and the present aggregate amount of data comprises reducing/increasing the defined data capacity limit in response to the difference being determined to be decreasing/increasing.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 1, 2020
    Assignee: EMC CORPORATION
    Inventor: John Gemignani, Jr.
  • Patent number: 10740228
    Abstract: Systems, methods and/or devices are used to enable locality grouping during garbage collection of a storage device. In one aspect, the method includes, at a storage controller for the storage device: performing one or more operations for a garbage collection read, including: identifying one or more sequences of valid data in a source unit, wherein each identified sequence of valid data has a length selected from a set of predefined lengths; and for each respective sequence of the one or more sequences of valid data in the source unit, transferring the respective sequence to a respective queue of a plurality of queues, in accordance with the length of the respective sequence; and performing one or more operations for a garbage collection write, including: identifying full respective queues for writing to a destination unit; and writing from the full respective queues to the destination unit.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 11, 2020
    Assignee: Sandisk Technologies LLC
    Inventors: Neil D. Hutchison, Steven Theodore Sprouse, Shakeel I. Bukhari
  • Patent number: 10728321
    Abstract: Automatically sharing resources between devices is provided. A communication channel is established with a trusted data processing system over a network. In response to establishing the communication channel, a list of resources available for sharing between the data processing system and the trusted data processing system is shared via the communication channel. It is determined whether a match for a resource requested by the trusted data processing system exists in the list. In response to determining that a match for the resource requested by the trusted data processing system exists in the list, a matching resource is automatically shared with the trusted data processing system via the communication channel.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jose Cano Zapata, Cesar Augusto Rodriguez Bravo, Edgar A. Zamora Duran
  • Patent number: 10659396
    Abstract: Techniques are disclosed for managing data within a reconfigurable computing environment. In a multiple processing element environment, such as a mesh network or other suitable topology, there is an inherent need to pass data between processing elements. Subtasks are divided among multiple processing elements. The output resulting from the subtasks is then merged by a downstream processing element. In such cases, a join operation can be used to combine data from multiple upstream processing elements. A control agent executes on each processing element. A memory buffer is disposed between upstream processing elements and the downstream processing element. The downstream processing element is configured to automatically perform an operation based on the availability of valid data from the upstream processing elements.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 19, 2020
    Assignee: Wave Computing, Inc.
    Inventor: Christopher John Nicol
  • Patent number: 10582527
    Abstract: Apparatus and method are provided to enhance scheduling request to multiple schedulers with inter base station carrier aggregation. In one novel aspect, the UE monitors and detects one or more SR triggering event. The UE selects one or more base stations based on predefined criteria and sends the SR to the selected one or more base stations. In one embodiment, at least one LC of the UE is associated with multiple BSs with association priorities. In one embodiment, the association priorities are configured by the network. In other embodiments, the association priorities are derived based on predefined UE configurations, or are derived from load information received by the UE, or are derived from radio measurements. In one novel aspect, the UE upon detecting SR failure triggered on a triggering LC, sends SR failure indication to a RRC layer or associates the triggering LC with a different base station.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: March 3, 2020
    Assignee: HFI Innovation INC.
    Inventors: Yuanyuan Zhang, Chia-Chun Hsu, Per Johan Mikael Johansson
  • Patent number: 10445156
    Abstract: A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 15, 2019
    Assignee: Solarflare Communications, Inc.
    Inventors: Steven Leslie Pope, Derek Edward Roberts, David James Riddoch, Greg Law, Steve Grantham, Matthew Slattery
  • Patent number: 10437718
    Abstract: A method of prefetching data is provided including monitoring sequences of memory addresses of data being accessed by a system, whereby sequences of m+1 memory addresses each are continually identified; and for each identified sequence: converting, upon identifying said each sequence, memory addresses of said each sequence into m relative addresses, whereby each of the m relative addresses is relative to a previous memory address in said each sequence, so as to obtain an auxiliary sequence of m relative addresses; upon converting said memory addresses, feeding said auxiliary sequence of m relative addresses as input to a trained machine learning model for it to predict p relative addresses of next memory accesses by the system, where p?1; and prefetching data at memory locations associated with one or more memory addresses that respectively correspond to one or more of the p relative addresses predicted.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andreea Anghel, Peter Altevogt, Gero Dittmann, Cedric Lichtenau
  • Patent number: 10423462
    Abstract: Embodiments of the present invention provide systems and methods for dynamically allocating data to multiple nodes. The method includes determining the usage of multiple buffers and the capability factors of multiple servers. Data is then allocated to multiple buffers associated with multiple active servers, based on the determined usage and capability factors, in order to keep the processing load on the multiple servers balanced.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mi W. Shum, DongJie Wei, Samuel H. K. Wong, Xin Ying Yang, Xiang Zhou
  • Patent number: 10394641
    Abstract: An apparatus and method are described for handling memory access operations, and in particular for handling faults occurring during the processing of such memory access operations. The apparatus has processing circuitry for executing program instructions that include memory access instructions, and a memory interface for coupling the processing circuitry to a memory system. The processing circuitry is switchable between a synchronous fault handling mode and an asynchronous fault handling mode. When in the synchronous fault handling mode the processing circuitry applies a constraint on execution of the program instructions such that a fault resulting from a memory access operation processed by the memory system will be received by the memory interface before the processing circuitry has allowed program execution to proceed beyond a recovery point for the memory access instruction associated with the memory access operation.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: August 27, 2019
    Assignee: ARM Limited
    Inventor: Simon John Craske
  • Patent number: 10390256
    Abstract: A communication method according to an embodiment, comprising: transmitting, from a base station to a radio terminal, a list indicating association between an identification of a logical channel group and a priority; generating, by the radio terminal, a buffer status report for direct communication; and transmitting, from the radio terminal to the base station, the buffer status report. The buffer status report includes an index of an destination identifier, an identifier of the logical channel group, and a buffer amount associated with the identifier of the logical channel group. In the generating the buffer status report, the radio terminal generates the buffer status report based on the list.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: August 20, 2019
    Assignee: KYOCERA Corporation
    Inventors: Takahiro Saiwai, Hiroyuki Adachi, Noriyoshi Fukuta, Masato Fujishiro
  • Patent number: 10296437
    Abstract: A method is described that includes receiving an application and generating a representation of the application that describes specific states of the application and specific state transitions of the application. The method further includes identifying a region of interest of the application based on rules and observations of the application's execution. The method further includes determining specific stimuli that will cause one or more state transitions within the application to reach the region of interest. The method further includes enabling one or more monitors within the application's run time environment and applying the stimuli. The method further includes generating monitoring information from the one or more monitors. The method further includes applying rules to the monitoring information to determine a next set of stimuli to be applied to the application in pursuit of determining whether the region of interest corresponds to improperly behaving code.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: May 21, 2019
    Assignee: FireEye, Inc.
    Inventors: Osman Abdoul Ismael, Dawn Song, Ashar Aziz, Noah Johnson, Prashanth Mohan, Hui Xue
  • Patent number: 10298491
    Abstract: In response to a path monitoring task for a particular source/destination pair, a network controller determines whether stored information includes paths for the particular source/destination pair. When the stored information includes paths for the particular source/destination pair, a subset of source ports is selected that covers all the paths for the particular source/destination pair. A probe message is sent to cause an ingress switch to send probe packets using the subset of source ports. Paths for the particular source/destination pair are computed based on received probe packets. A determination is made whether a topology for the data center network has changed by comparing the paths computed based on the receive probe packets for the particular source/destination pair with the paths included in the stored information for the particular source/destination pair.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 21, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Deepak Kumar, Yi Yang, Carlos M. Pignataro, Nagendra Kumar Nainar
  • Patent number: 10282236
    Abstract: Embodiments of the present invention provide systems and methods for dynamically allocating data to multiple nodes. The method includes determining the usage of multiple buffers and the capability factors of multiple servers. Data is then allocated to multiple buffers associated with multiple active servers, based on the determined usage and capability factors, in order to keep the processing load on the multiple servers balanced.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mi W. Shum, DongJie Wei, Samuel H. K. Wong, Xin Ying Yang, Xiang Zhou
  • Patent number: 10284488
    Abstract: Aggregate socket resource management is presented herein. A system can comprise a processor; and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising: determining a present aggregate amount of data associated with processing requests from a socket; setting a defined aggregate data limit on the present aggregate amount of data; and in response to determining changes in a difference between the defined aggregate data limit and the present aggregate amount of data, modifying a defined data capacity limit on a data capacity of a receive buffer of the socket. In an example, the determining of the changes in the difference between the defined aggregate data limit and the present aggregate amount of data comprises reducing/increasing the defined data capacity limit in response to the difference being determined to be decreasing/increasing.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 7, 2019
    Assignee: EMC CORPORATION
    Inventor: John Gemignani, Jr.
  • Patent number: 10282293
    Abstract: A memory access method includes: receiving, by the switch, a data packet; matching a flow table on the data packet, where the flow table includes at least one flow entry, where the flow entry includes a matching field and an action field, and the at least one flow entry includes a first flow entry, where a matching field of the first flow entry is used to match source node information, destination node information, and a protocol type in the data packet, and an action field of the first flow entry is used to indicate an operation command for a storage device embedded in the switch; and when the data packet successfully matches the first flow entry, performing an operation on the storage device according to the operation command in the action field of the successfully matched first flow entry.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 7, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yidong Tao, Rui He, Xiaowen Dong
  • Patent number: 10255122
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Brian T. Lewis, Rajkishore Barik, Tatiana Shpeisman
  • Patent number: 10200485
    Abstract: A system transmits selected news feed stories to a client device in advance of receiving a request for news feed stories. As a result, stories are immediately available for viewing when a user interacts with the system. The system selects news feed stories to push based on criteria such as a likelihood that a user will interact with a story and the sizes of pushed stories. For example, the system selects news feed stories such that a total size of stories selected does not exceed a threshold value based on local memory at the client device. The system may determine a scheduled time at which the stories are selected and pushed. The scheduled time is based on factors including patterns of network connection speed or past user interactions, for example, a time range of the day during which the user most frequently viewed pushed stories.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: February 5, 2019
    Assignee: Facebook, Inc.
    Inventors: Christopher John Marra, Alexander A. Sourov, Alexandru Petrescu, Syed Shahbaz Ahmed, Lars Seren Backstrom
  • Patent number: 10169154
    Abstract: A system and method for data storage by shredding and deshredding of the data allows for various combinations of processing of the data to provide various resultant storage of the data. Data storage and retrieval functions include various combinations of data redundancy generation, data compression and decompression, data encryption and decryption, and data integrity by signature generation and verification. Data shredding is performed by shredders and data deshredding is performed by deshredders that have some implementations that allocate processing internally in the shredder and deshredder either in parallel to multiple processors or sequentially to a single processor. Other implementations use multiple processing through multi-level shredders and deshredders. Redundancy generation includes implementations using non-systematic encoding, systematic encoding, or a hybrid combination.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Douglas R. de la Torre, David W. Young
  • Patent number: 10089038
    Abstract: First in, first out (FIFO) memory queue architecture enabling a plurality of writers and a single reader to use the queue without mutual exclusive locking. The FIFO queue is implemented using an array. A write counter value associated with the array provides a reservation value to each writer that is mutually exclusive of the value provided to every other writer. A read counter value associated with the array prevents writers from writing over data messages stored in the array that are yet to be read by the single reader.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 2, 2018
    Assignee: Schneider Electric Software, LLC
    Inventors: Rade Ranković, Collin Miles Roth
  • Patent number: RE50067
    Abstract: A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 30, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Akihisa Fujimoto