Abstract: Systems for managing a multi-level cache in high-performance computing. A method is practiced over a multi-tier caching subsystem that comprises a first cache tier of random access memory, and a second cache tier that comprises a block-oriented device. The solid-state drive device is a block-oriented device comprising a plurality of blocks having a minimum block size. Cache entries are initially stored in the first cache, including cache entries that are smaller than the minimum block size of the block-oriented device. During cache operations such as first tier eviction, a plurality smaller entries are packed into blocks of the minimum block size before being spilled into the second tier. If an entry in the packed block is accessed again, the entire packed block is brought into the first tier. A key structure is maintained to track individual invalidated entries in a packed block without invalidating other entries in the packed block.

Abstract: Dynamic sharing of RAM in a software-defined communication system includes storing program code in a flash memory, categorizing parts of the code into groups of transmit categories according to when a part of the code needs to be copied into a section of a RAM and then executed during a first state of a TX state machine and according to how another part of the code can be later fit into the same section and then executed during a second state. Similarly, parts of the code are categorized into groups of receive categories according to when a part of the code needs to be copied into a section of RAM and then executed during a first state of a RX state machine and according to how another part of the code can be later fit into that section and then executed during a second state of the RX state machine, to reduce the amount of RAM without sacrificing speed performance.

Abstract: Disclosed are systems and methods for protecting transmission of audio data from microphone to application process. An exemplary method includes receiving a request from a software process to obtain an audio stream from an audio endpoint device; allocating a data buffer for the software process; processing and encrypting audio data received from the audio endpoint device by audio processing objects; storing the encrypted audio data in the allocated data buffer; installing an interceptor of a API function call for the software process; and decrypting the encrypted audio data from the allocated data buffer by the software process using the interceptor of the API function call.

Abstract: A computer-implemented method for storing data in a storage area, includes: storing a first data unit in a first area of the storage area, in response to a request to store a first data unit having a first attribute in the storage area, when at least one data unit having the first attribute is stored in the first area; and generating, a second area by reducing the first area, when no data unit having the second attribute is stored in the storage area in response to a request to store a second data unit having a second attribute in the storage area; furthermore, storing the second data unit in the second area.

Abstract: Method for providing sound to at least one user, involves supplying audio signals from an audio signal source to a transmission unit; compressing the audio signals to generate compressed audio data; transmitting compressed audio data from the transmission unit to at least one receiver unit; decompressing the compressed audio data to generate decompressed audio signals; and stimulating the hearing of the user(s) according to decompressed audio signals supplied from the receiver unit. During certain time periods, transmission of compressed audio data is interrupted, and instead, at least one control data block is generated by the transmission unit in such a manner that audio data transmission is replaced by control data block transmission, thereby temporarily interrupting flow of received compressed audio data, each control data block includes a marker recognized by the at least one receiver unit as a control data block and a command for control of the receiver unit.

Abstract: A method, computer program product, and system for dynamically distributing data for parallel processing in a computing system, comprising allocating a data buffer to each of a plurality of data partitions, where each data buffer stores data to be processed by its corresponding data partition, distributing data in multiple rounds to the data buffers for processing by the data partitions, where in each round the data is distributed based on a determined data processing capacity for each data partition, and where a greater amount of data is distributed to the data partitions with higher determined processing capacities, and periodically monitoring usage of each data buffer and re-determining the determined data processing capacity of each data partition based on its corresponding data buffer usage.

Abstract: A method, computer program product, and system for dynamically distributing data for parallel processing in a computing system, comprising allocating a data buffer to each of a plurality of data partitions, where each data buffer stores data to be processed by its corresponding data partition, distributing data in multiple rounds to the data buffers for processing by the data partitions, where in each round the data is distributed based on a determined data processing capacity for each data partition, and where a greater amount of data is distributed to the data partitions with higher determined processing capacities, and periodically monitoring usage of each data buffer and re-determining the determined data processing capacity of each data partition based on its corresponding data buffer usage.

Abstract: This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.

Abstract: A method is described that includes receiving an application and generating a representation of the application that describes specific states of the application and specific state transitions of the application. The method further includes identifying a region of interest of the application based on rules and observations of the application's execution. The method further includes determining specific stimuli that will cause one or more state transitions within the application to reach the region of interest. The method further includes enabling one or more monitors within the application's run time environment and applying the stimuli. The method further includes generating monitoring information from the one or more monitors. The method further includes applying rules to the monitoring information to determine a next set of stimuli to be applied to the application in pursuit of determining whether the region of interest corresponds to improperly behaving code.

Abstract: Systems and techniques are disclosed for receiving one or more recipient identifiers and a destination location from a user or an application. A uniform resource locator may be generated and may include a destination ID corresponding to the destination location. An entry containing the one or more recipient identifiers may be generated in an access control list for the destination location. A recipient may request access to the destination location by selecting the uniform resource locator. A recipient identifier may be determined for the recipient requesting the access and may be compared to entries in the access control list. If the recipient identifier matches an entry in the access control list, then the recipient may be granted access to the destination location.

Abstract: A memory system includes a memory device including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data and a plurality of page buffers respectively corresponding to the planes; and a controller suitable for transferring write data stored in a write buffer thereof to a first page buffer of a first chip, releasing the write buffer and a first plane corresponding to the first page buffer in the first chip after the transfer to the first page buffer, and programming the write data in the first planes after the release from the first plane.

Abstract: An electronic device displays a first video stream on a display. While displaying the first video stream on the display, the device allocates, in accordance with a historical pattern of video stream switching of a particular user, available bandwidth for receiving data at the device at least between receiving the first video stream and preloading a second, non-displayed video stream. The device receives the first video stream and preloads the second, non-displayed video stream in accordance with the allocated available bandwidth. The device receives a request to display the second video stream on the display. In response to receiving the request to display the second video stream on the display, the device displays the preloaded second video stream on the display.

Abstract: Embodiments of the present disclosure relate to methods and systems for hybrid testing, combining the optimization features of functional testing brought forth to security testing. One disclosed method may include receiving a list of input points associated with a software unit under test and assigning, by a processor, risk values to the input points based on one or more risk rating factors. The risk values may reflect security risk associated with the input points. The method may further include providing, to the software unit under test, input values indicative of a functional test for input points assigned values reflecting a low security risk and input values indicative of a security test for input points assigned values reflecting a high security risk. The method may further include executing a security test for the software unit under test using the input values.

Abstract: An apparatus having a circuit and a processor is disclosed. The circuit may be configured to (i) generate a plurality of sets of coefficients by compressing a block in a picture in a video signal at a plurality of different sizes of coding units in a coding tree unit and (ii) generate an output signal by entropy encoding a particular one of the sets of coefficients. Each set of coefficients may be generated in a corresponding one of a plurality of pipelines that operate in parallel. The processor may be configured to select the particular set of coefficients in response to the compressing.

Abstract: A technique for allocating a uplink data volume 504 to uplink data pending for transmission in a telecommunications device is provided. As to a method aspect of the technique, a grant of the uplink data volume is received. A portion 502 of the granted uplink data volume is reserved for transmission of a buffer status report, which is to be provided by a Data Link layer 300 of the telecommunications device. A size of the buffer status report depends on a number of channels for which uplink data is pending. If an unreserved portion 503 of the granted uplink data volume is not sufficiently sized for the pending uplink data, the unreserved portion and at least a part of the reserved portion are allocated to at least a portion of the pending uplink data when the allocation corresponds to a reduction of a number of channels for which uplink data is pending so that the buffer status report is at least reduced in size.

Abstract: In an example implementation, a method includes receiving an indication to reclaim memory from a cache, the cache including a plurality of data buckets each configured to store one or more records and corresponding access bits. The method also includes selecting a data bucket from the cache, and processing the selected data bucket. Processing the selected data bucket includes determining access bits of the selected data bucket that are clear, and expunging data records corresponding to those access bits from the cache. Processing the selected data bucket also includes determining access bits of the selected data bucket that are set and do not correspond to records relevant to outstanding requests by a process utilizing the cache, and clearing those access bits. The method also includes repeating selecting and processing data buckets until a stop criterion is satisfied.

Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from multiple hosts, manages traffic among the hosts, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.

Abstract: A method for dynamically adjusting a cache buffer of a solid state drive includes receiving data, determine if the data are continuous according to logical allocation addresses of the data, increasing a memory size of the cache buffer, searching the cache buffer for same data as at least one portion of the data, modifying and merging of the at least one portion of the data with the same data already temporarily stored in the cache buffer, temporarily storing the data in the cache buffer.

Abstract: Embodiments provide a method for streaming media and a media controller. The method includes: receiving, by a media controller, a media streaming request sent by a user equipment, and allocating an index to the user equipment, wherein the index is used to indicate an address of a corresponding buffer in the media controller to which data to be streamed is stored; binding the streaming request and the index of the user equipment and storing in a table, and sending the them to a media server so that the media server controls, according to the table, a storage device to send the data to be streamed to an address of a buffer corresponding to the index; and receiving then streaming the data to be streamed that is requested by the streaming request to the corresponding user equipment by querying the table.

Abstract: A method of garbage collection in a storage device including a central processing unit (CPU), a self-organized fast release buffer (FRB), and a non-volatile memory, the method including receiving a command to perform garbage collection in a first block stripe of the non-volatile memory from the CPU, the command including a second block stripe to write to and valid logical block numbers (LBNs) corresponding to a first codewords (CWs) stored in the first block stripe, allocating space in a buffer memory of the FRB for storage of the first CWs, storing the first CWs into the allocated space in the buffer memory, transferring a second CWs to a plurality of physical addresses in the second block stripe of the non-volatile memory, and sending the valid LBNs and the plurality of physical addresses to the CPU to update a logical-to-physical table, wherein the second CWs is based on the first CWs.

Abstract: A system, method and computer program product for controlling the processing of requests for web page resources from a web server are provided. The method comprises monitoring a run level of the web server; receiving requests for one or more web page resources; determining a priority of received requests based on a run level value associated with a requested resource and the run level of the web server; and processing the requests by the web server according to the determined priority. In dependence on the current load on the web server, requests for low priority resources can be given a low processing priority, with processing capability focussed on requests for higher priority web resources.

Abstract: A packet transfer processing device includes common processing units that perform processing common to inbound processing of a packet received from an access network for transfer to a core network and outbound processing of a packet received from the core network for transfer to the access network, an input destination switching unit that selects common processing units to which the received packets are to be input, an output destination switching unit that outputs packets processed by the common processing units to a destination network, an individual processing switching unit that selects a common processing unit to connect to an individual processing unit that performs individual processing not performed by the common processing units as part of inbound processing, and a control unit that controls the input destination switching unit, the individual processing switching unit, and switching supply/shutoff of power to the common processing units.

Abstract: In one embodiment, a computer program product for modifying a virtual storage access method (VSAM) data set during open time, the computer program product including a computer readable storage medium having computer readable program code embodied therewith, the embodied computer readable program code including computer readable program code configured to open a VSAM data set, and computer readable program code configured to modify a VSAM control block structure for the VSAM data set while the VSAM data set is open during an open time in which static data set characteristics and/or job parameters have been defined for the VSAM data set, wherein the computer readable program code configured to modify the VSAM control block structure includes computer readable program code configured to interact with the VSAM data set within a VSAM dynamic address space using at least one of: a VSAM console interface and a VSAM programming interface.

Abstract: A method and system for managing consistent data objects are included herein. The method includes detecting an operation to store a consistent data object. Additionally, the method includes detecting an attribute for the consistent data object. Furthermore, the method includes storing the consistent data object based on the attribute. In addition, the method includes determining an additional format of the consistent data object is to be stored. The method also includes generating a second consistent data object based on the additional format and storing the second consistent data object.

Abstract: Techniques for estimating processor load by using queue depth information of a peripheral adapter provides processor loading information that can be used to adapt interrupt latency to improve performance in a processing system. A mathematical function of the depth of one or more queues of the adapter is compared to its historical value in order to provide an estimate of processor load. The estimated processor load can then be used to set a parameter that controls the frequency of an interrupt generator. The mathematical function may be the ratio of the transmit queue depth to the receive queue depth and the historical value may be predetermined, user-settable, obtained during a calibration interval or obtained by taking a long-term average of the mathematical function of the queue depths.

Abstract: A method of reading host data from a storage device including a central processing unit (CPU), a self-organized fast release buffer (FRB), and a non-volatile memory, the storage device being in communication with a host, the method including receiving, by the FRB, a command to read host data stored in the non-volatile memory from the CPU, the host data being stored in the non-volatile memory as one or more codewords (CWs), allocating space, by the FRB, in a buffer memory of the FRB for storage of the one or more CWs, storing, by the FRB, the one or more CWs into the allocated space in the buffer memory, extracting, by the FRB, the host data from the stored one or more CWs, and transferring, by the FRB, the host data to the host.

Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is reset, the host computing device may include a PCI communication path for maintaining communication between the system resources and the I/O devices. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state. The host may monitor the errors generated by a plurality of master PHBs and select a master PHB that satisfies an error threshold. The second PHB (i.e., a servant PHB) and the selected master PHB are synchronized, and the second PHB is coupled to the PCI communication path between the master PHB and a PCI switch. The master PHB can then be reset while the second PHB maintains PCI communication between the host and the I/O devices.

Abstract: A virtual tape library includes a local, non-tape based storage, a store to store a data structure which associates emulated tape storage elements with the local storage or a remote storage, a first interface to provide access to the local storage, in response to tape library commands identifying emulated tape storage elements associated with the local storage, and a second interface to provide access to the remote storage, in response to tape library commands identifying emulated tape storage elements associated with the remote storage.

Abstract: A system and method can support input/output (I/O) virtualization in a computing environment. The system can comprise a free buffer pool in a memory. An I/O device operates to use the free buffer pool to store disk read data received from a physical host bus adaptor (HBA). The free buffer pool can contain a two-dimensional linked list and a one-dimensional linked list. Each entry of the two-dimensional linked list contains multiple packet buffers in consecutive memory locations, and each entry of the one-dimensional linked list contains a single packet buffer.

Abstract: Methods and devices are provided for memory management. One embodiment includes creating a memory control block including a number of sub-blocks, where the number of sub-blocks are capable of storing at least one data structure in a memory device. The method also includes scanning the control block for a free-able data structure having a defined data structure property, marking the free-able data structure as free-able in a bit map, and de-allocating the free-able data structure.

Abstract: A first virtual machine executing in a first computer server is replicated to a second virtual machine executing in a second computer server, which is connected to the first computer server over a network. Virtual disks of the first virtual machine are transmitted to the second server, where each transmitted virtual disk corresponds to one of the virtual disks of the second virtual machine, the virtual disks of the first virtual machine having a format different from the format of the virtual disks of the second virtual machine. A plurality of updates to the virtual disks of the first virtual machine is captured, and contiguous data blocks from the virtual disks of the first virtual machine that are subject to the captured updates are identified. The identified contiguous data blocks are then transmitted to the second server for storage in the virtual disks of the second virtual machine.

Abstract: Techniques are disclosed for reducing perceived read latency. Upon receiving a read request with a scatter-gather array from a guest operating system running on a virtual machine (VM), an early read return virtualization (ERRV) component of a virtual machine monitor fills the scatter-gather array with data from a cache and data retrieved via input-output requests (IOs) to media. The ERRV component is configured to return the read request before all IOs have completed based on a predefined policy. Prior to returning the read, the ERRV component may unmap unfilled pages of the scatter-gather array until data for the unmapped pages becomes available when IOs to the external media complete. Later accesses to unmapped pages will generate page faults, which are handled by stunning the VMs from which the access requests originated until, e.g., all elements of the SG array are filled and all pages of the SG array are mapped.

Abstract: A solid state drive (SSD), includes: a plurality of solid state memory devices, each solid state memory device including a plurality of memory blocks arranged in a plurality of planes; a storage; and an SSD controller configured to: write data to memory blocks in a predefined sequence, detect a defective memory block in the plurality of solid state memory devices, mark the detected memory block as defective and store an address of a next non-defective memory block, and in response to data to be written to the marked memory block, the controller skips the marked memory block and writes the data to the next non-marked memory block.

Abstract: Described are techniques for processing data operations. A read request for first data is received at a data storage system. It is determined whether the read request results in a cache hit whereby the first data is stored in a cache of the data storage system, or whether the read request otherwise results in a cache miss. If the read request results in a cache miss, processing is performed to determine determining whether to perform cacheless read processing or deferred caching processing to service the read request. Determining whether to perform cacheless read processing or deferred caching processing is performed in accordance with criteria including a measurement indicating a level of busyness of a back-end component used to retrieve from physical storage any portion of the first data not currently stored in the cache.

Abstract: A tracking buffer apparatus is disclosed. A tracking buffer apparatus includes lookup logic configured to locate entries having a transaction identifier corresponding to a received request. The lookup logic is configured to determine which of the entries having the same transaction identifier has a highest priority and thus cause a corresponding entry from a data buffer to be provided. When information is written into the tracking buffer, write logic writes a corresponding transaction identifier to the first free entry. The write logic also writes priority information in the entry based on other entries having the same transaction identifier. The entry currently being written may be assigned a lower priority than all other entries having the same transaction identifier. The priority information for entries having a common transaction identifier with one currently being read are updated responsive to the read operation.

Abstract: A method and system are presented for providing deterministic inter-core, inter-process, and inter-thread communication between a reader and a writer. The reader and writer communicate by passing data through a shared memory using double buffering of double buffers. The shared memory includes a first double buffer and a second double buffer. Both double buffers include a first low level buffer and a second low level buffer. Using double buffering of the double buffers, both the reader and the writer may simultaneously access the shared memory.

Abstract: A system, method, and computer program product are provided for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information associated with the difference is stored in the memory. To this end, the write operations may be reduced, utilizing the difference information.

Abstract: A system and method to reduce and/or eliminate crosstalk between various data paths of a data bus within integrated circuits (i.e., chips). The system and method can transmit both delayed and non-delayed data in respective transmission paths, store the delayed and non-delayed data upon receipt, and delay the reading of the delayed and non-delayed data from the storage unit to compensate for the delay implemented on the transmission of the delayed data.

Abstract: A method implemented in a network for enhancing transmission is disclosed. The network contains a number of network devices, and at least one network device provides traffic scheduling function to schedule transmission of packets. The method starts with arrival of a packet. In response to arrival of the packet, the network device determines whether a timer has expired, whether a congestion level has reached a congestion threshold, whether the packet is a high priority packet, and whether a burst accumulation counter has reached an accumulation threshold. The packet is transmitted, along with any packet waiting for transmission, in response to at least one of the conditions are satisfied: the timer has expired, the congestion level has reached the congestion threshold, the packet is a high priority packet, and the burst accumulation counter has reached the accumulation threshold.

Abstract: Reduction of data packet losses on updating of an address table, stored in a computer of a local network is provided. The address table comprises allocations of computer addresses, valid in the local network, to computer addresses valid in the Internet for transmission of data packets, whereby an address allocation stored in the address table is erased after expiry of a validity timer and the address allocation is firstly requested again and inserted in the address table when a data packet is transmitted to an address internet-valid address of a computer in the local network. During the updating of the address allocation, data packets for transmission are buffered in a buffer memory, the size of the buffer memory being configured corresponding to the expected load of the local network. The size of the buffer memory matches the expected load on the local network.

Abstract: A unique device name is assigned to each of a plurality of shared storage devices in a cluster configuration database defining membership of nodes in a cluster. A particular node among the nodes defined by the cluster configuration database as a member of the cluster searches the cluster configuration database for a device identifier matching a device identifier of a shared storage device hosted by the particular node. In response to finding a matching device identifier in the cluster configuration database, the particular node renames, in a local configuration maintained at the particular node, a storage device associated with the matching device identifier with the unique name assigned to that storage device in the cluster configuration database.

Abstract: Systems and methods are disclosed for processing a queue associated with a request. An example system includes an input/output (I/O) interface that receives a request associated with a channel. The example system also includes an association module that determines whether a condition is satisfied. When the condition is determined to not be satisfied, the association module, after a hardware device completes processing the request, decrements an in-flight counter that represents a first amount of data in the channel. When the condition is determined to be satisfied, the association module, before the hardware device completes processing the request, decrements the in-flight counter.

Abstract: The components of communication network device ingress systems and methods cooperate to manage information ingress and prevent denial of service attempts. A classifier classifies incoming information. A classification filter filters the information on a classification basis to prevent denial of service. The classification filter includes a classification filter counter for tracking the flow of information associated with the classification filter. A zero value in the classification filter counter indicates that a buffer capacity limit associated with the classification is reached. The counter permits information to flow to a packet buffer if the classification filter counter value is not zero and discards information if the classification filter counter value is zero. In one exemplary implementation the classification filter counter decrements a classification filter counter value when the information is placed in the buffer.

Abstract: A method for exchanging message data in a distributed computer system between a sending and a receiving hardware system. The sending hardware system includes a first memory system and a receiving hardware system which includes a second memory system with a second data buffer and a second memory region. The sending hardware system and the receiving hardware system are coupled via a non-transparent bridge unit. The method includes allocating empty memory, writing information about the empty memory, copying payload data directly from the sending hardware system to the empty memory locations, and writing information about the copied payload data to the second data buffer of the second memory system inside the receiving hardware system. A computer program product for carrying out the method is also provided.

Abstract: A buffer controller includes a first write pointer generation module for generating a first write pointer that points to a first sequence of write locations in a buffer memory, that directs an input module to store a sequence of samples of a real-time signal in a buffer memory. A read pointer generation module generates a plurality of read pointers for a corresponding plurality of output modules, wherein each of the plurality of read pointers points to a sequence of read locations in the buffer memory, in a buffer order, that contain the sequence of samples.

Abstract: Systems and techniques are disclosed that include in one aspect a computer implemented method storing a received stream of data elements in a buffer, applying a boundary condition to the data elements stored in the buffer after receiving each individual data element of the stream of data elements, and producing one or more data elements from the buffer based on the boundary condition as an output stream of data elements sorted according to a predetermined order.

Abstract: This disclosure describes techniques to improve a user experience in a Wireless Display (WD) system. The WD system includes a source device that provides media data to one or more sink devices. The techniques are directed toward reducing end-to-end latency in the WD system while improving video playback quality at the sink devices. More specifically, the techniques include customized buffering at the sink devices based on application awareness for the media data. The techniques include learning the type of application for the media data, and adjusting the size of buffers in the processing pipeline to achieve an appropriate balance between smoothness and latency for the application type. For example, when the media data is for a video playback application, the techniques include increasing the buffer size to increase smoothness in the video playback application.

Abstract: A router has multiple channel inputs and multiple channel outputs and a switch core for selectively connecting at least two of the channel outputs to respective channel inputs. Each channel output is connected to an output signal path containing a FIFO register and the router is configured so that first and second channel outputs are connected to a pair of channel inputs respectively. The router configuration is changed so that the first and second channel outputs are connected to first and second channel inputs respectively. The FIFO registers in the output signal paths of the first and second channel outputs are forced to equal fullness.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: One or more out-of-band input signals (GPIO) are handled and efficiently embedded into a USB capture stream. In order to conserve resources, the state of the input signals can be sent only when a change occurs. The signals are accurately time-stamped, and then presented within the context of the captured USB data. In order to provide maximum visibility, if the digital inputs occur during a normally filtered multi-packet sequence, the filter is canceled and the surrounding packets will also be sent to an analysis computer. Furthermore, because digital inputs may happen during a USB packet, the digital inputs are queued in a FIFO buffer until there is an opportunity to send the digital inputs. Even though the state of the inputs may be sent at a later time, the state of the inputs may be time-stamped when the state of the inputs is perceived by the analyzer.