Abstract: A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device.

Abstract: A storage system and method for storing information in memory nodes. The storage or memory nodes include a communication buffer. Flow of information to the storage nodes is controlled based upon constraints on the communication buffer. In one embodiment, communications between a master controller and a storage node have a determined maximum latency.

Abstract: Gain Saturation (GS) for MRFME is where searching in more previous frames offers very limited or even no performance gain. Similarly, gain aggregation (GA) is where significant gain can be obtained by searching more frames. By dynamically determining, while encoding, if either condition applies, and changing the search range accordingly, complexity is reduced and speed can be increased.

Abstract: A plurality of server access requests is received from a plurality of clients via at least one input port of an arbiter. One or more of a plurality of servers that are available for access by the plurality of clients are identified. One or more of the plurality of clients are selected based on identifying the one or more available servers and based on a selection sequence that includes each of the plurality of clients from which one of the plurality of server access requests has been received. Data indicative of a requested service is forwarded from each of the one or more selected clients to a corresponding one of the one or more available servers.

Abstract: Embodiments of the invention are directed to a storage subsystem comprising a non-volatile solid-state memory array and a controller. In one embodiment, the controller includes a system operation module configured to manage system memory operations and a queue configured to receive memory commands from a host system and the system operation module. The controller is configured to execute, in the memory array, memory commands from the queue in a sequence that is based at least in part on a throttling ratio provided by the system operation module.

Abstract: The present disclosure relates to real-time data management for a power grid and presents a real-time data management system, a system, method, apparatus and tangible computer readable medium for accessing data in a power grid, a system, method, apparatus and tangible computer readable medium for controlling a transmission delay of real-time data delivered via a real-time bus, and a system, method, apparatus and tangible computer readable medium for delivering real-time data in a power grid. In the real-time data management system of the present disclosure, a unified data model covering various organizations and various data resource is designed and a management scheme for clustered data is used to provide a transparent and high speed data access. Besides, multi-bus collaboration and bus performance optimization approaches are utilized to improve efficiency and performance of the buses.

Abstract: A method and system are disclosed for network adaptor optimization and interrupt reduction. The method may also build an outbound buffer list based on outgoing data and add the outgoing data to an outbound buffer queue. Furthermore, the method may set a buffer state from an empty state to a primed state to indicate that the outgoing data is prepared for transmitting and signal a network adaptor with a notification signal.

Abstract: A proxy manages write operations between devices that initiate write operations and one or more storage devices that store data for the write operations. A write log buffers the data for the write operations while the proxy waits for acknowledgments back from the storage device. The proxy is configured to copy at least some of the data from the write log into an overflow log when the data from the write operations is about to overflow the write log. The proxy device is further configured to maintain data consistency by delaying or blocking read operations until associated data from previously received write operations is acknowledged by the storage device.

Abstract: There is provided a mechanism for reporting buffer status information to a communication network control element when transmission via both a licensed and an unlicensed spectrum is conducted and offloading of traffic is executed. After an offloading value indicating the amount of traffic which can be offloaded from a transmission over a licensed spectrum to a transmission over an unlicensed spectrum is estimated, the UE determines a buffer size of at least one transmission buffer used in a transmission over the licensed spectrum and the unlicensed spectrum. Then, buffer status information is sent to the eNB wherein the estimated offloading value is considered. The eNB can then allocate resources for the transmission over the licensed band while benefits by the offloading to the unlicensed band are considered in the resource allocation.

Abstract: In an information-processing apparatus including a plurality of modules and a first arbiter which arbitrates bus-access requests of the plurality of modules, at least one of the plurality of modules includes a plurality of submodules and a second arbiter which arbitrates bus-access requests of the plurality of submodules and transmits at least one of the bus-access requests of the plurality of submodules to the first arbiter.

Abstract: A storage server in a distributed content storage and access system provides a mechanism for dynamically establishing storage resources, such as buffers, with specified semantic models. For example, the semantic models support distributed control of single buffering and double buffering during a content transfer that makes use of the buffer for intermediate storage. In some examples, a method includes examining characteristics associated with a desired transfer of data, such as a unit of content, and then selecting characteristics of a first storage resource based on results of the examining. The desired transfer of the data is then affected to use the first storage resource element.

Abstract: A system and method can provide a flexible buffer management interface in a distributed data grid. The buffer manager in the distributed data grid can receive a request from a requester for a buffer in the distributed data grid, wherein the request contains at least one parameter that provides an indication on the size of the requested buffer. Then, the buffer manager can allocate a buffer based on the indication in the request and provide the allocated buffer to the requester, wherein an actual size of the buffer is determined by the buffer manager.

Abstract: Data is buffered for concurrent writing to tape. For a magnetic tape drive having a magnetic head with multiple sets of transducers; a drive mechanism configured to pass a magnetic tape past the magnetic head; interfaces from two different hosts; and at least one buffer configured to buffer data; and a control; the buffering comprises receiving data from two different hosts at the interfaces; buffering the received data in separate buffer space of the buffer(s) associated with each host, and adjustably size the separate buffer space for each host in accordance with a data transfer rate of the host associated with the separate buffer space; and concurrently writing data from the separate buffer spaces with the magnetic head to separate partitions of the magnetic tape.

Abstract: A computer implemented method to transfer data from a data source to a data sink is provided. The method includes the steps of allocating a first buffer to the data source and locking the first buffer so as to enable only the data source to transfer data to the first buffer. The method further includes the steps of unlocking the first buffer and granting access to the data sink to read from the first buffer. The method also includes the steps of allocating a second buffer to the data source, locking the second buffer and enabling the data source to write data to the second buffer while enabling the data sink to read data from the first buffer, thereby pipelining data transfer from the data source to the data sink.

Abstract: Techniques are described for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information is stored in coalescing memory buffers. To this end, the write operations may be reduced, utilizing the difference information.

Abstract: Embodiments of a system that includes a switch and a buffer-management technique for storing signals in the system are described. In this system, data cells are dynamically assigned from a host buffer to at least a subset of switch-ingress buffers in the switch based at least in part on the occupancy of the switch-ingress buffers. This buffer-management technique may reduce the number of switch-ingress buffers relative to the number of input and output ports to the switch, which in turn may overcome the limitations posed by the amount of memory available on chips, thereby facilitating large switches.

Abstract: A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorize the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritize respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.

Abstract: Aspects of the disclosure pertain to a system and method for providing dynamic y-buffer size adjustment for retained sector reprocessing (RSR). The system and method implement dynamic y-buffer size adjustment for RSR for promoting improved Sector Failure Rate (SFR) performance of the system. The system is a read channel system.

Abstract: A system and method for dynamically reassigning buffer space during to maximize IO performance of virtual lanes is set forth. More specifically, the system and method for dynamically reassigning buffer space takes buffer space from unused virtual lanes and reassigns the unused buffer space to used virtual lanes, e.g., when changes occur to an IO configuration. For example, in an embodiment that supports four virtual lanes where only two virtual lanes are in use, the system and method reassign the buffer space from the other two unused virtual lanes for use by the two virtual lanes in use.

Abstract: An input/output unit for a computer system that is interfaced with a memory unit having a plurality of partitions manages completions of read requests in the order that they were made. A read request buffer tracks the order in which the read requests were made so that read data responsive to the read requests can be completed and returned to a requesting client in the order the read requests were made.

Abstract: According to various embodiments, apparatuses and methods to communicate buffer allocation information are presented. The disclosed apparatuses and methods may include transmitting a buffer message by a wireless USB device to a wireless USB host, which may indicate an available storage space in a buffer of the USB device to store data from the USB host. The buffer message may be transmitted independent of whether or not the USB device has received a request message (e.g., from the USB host) for information relating the available storage space in the buffer. Additionally, the buffer message may be transmitted independent of any data exchange mechanism between the USB host and the USB device. The USB device may receive a data packet from the USB host, and transmit a data packet acknowledgement message including data packet status information, and information regarding the available storage space in the buffer.

Abstract: A memory block reclaiming judging apparatus and a memory block managing system are disclosed in the present invention. The memory block reclaiming judging apparatus comprises a peripheral information accessing unit, a data packet information recording unit, a data calculating unit, and a comparing and judging unit, wherein the data calculating unit is configured to calculate remaining scheduling times of a data packet-and write the remaining scheduling times of the data packet into the data packet information recording unit, and meanwhile set a flag for indicating acquirement of information of the required scheduling times as valid; the comparing and judging unit is configured to generate a memory block reclaiming instruction, reset the remaining scheduling times of the data packet in the data packet information recording unit to an initial value, and set the flag for indicating acquirement of information of the required scheduling times as invalid.

Abstract: A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU, The method thus distinguishes between A-MSDU outside of the block ACK. agreement, which is mandatory, from A-MSDU under the block ACK agreement, which is optional. The method thus complies with the IEEE 802.11n specification while enabling the recipient to intelligently allocate memory during block ACK operations.

Abstract: Systems and methods are described including dynamically configuring a shared buffer to support processing of at least two video read streams associated with different video codec formats. The methods may include determining a buffer write address within the shared buffer in response to a memory request associated with one read stream, and determining a different buffer write address within the shared buffer in response to a memory request associated with the other read stream.

Abstract: A system improves bandwidth used by a data stream. The system receives data from the data stream and partitions the data into bursts. At least one of the bursts includes one or more idles. The system selectively removes the idles from the at least one burst and transmits the bursts, including the at least one burst.

Abstract: Provided is a memory switching control apparatus using an open serial interfacing scheme capable of enhancing flexibility, reliability, availability, performance in a data communication processes between a memory and a processing unit and an operating method thereof. The memory switching control apparatus includes: one or more processor interfacing units which perform interfacing with one or more processing units; one or more memory interfacing units which have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units.

Abstract: A method, system and article of manufacture are disclosed for registering and deregistering memory pages in a computer system. The method comprises the steps of hoisting register and deregister calls in a given routine where temporal locality is present to overlap computation and communication; using software pipelined registration and deregistration where spatial locality is observed; and using intra-procedural and inter-procedural analysis by a compiler of the computer system to deregister dynamically allocated buffers. The preferred embodiment of the invention is based on an optimizing compiler. The compiler is used to extract information such as addresses of buffers which are being reused repeatedly (temporal locality), preferably in a loop. The compiler may also find information about spatial locality, such as arrays whose indexes are used in a well-defined manner in a series of messages, for example, array pages being accessed in a pre-defined pattern in a loop.

Abstract: Disclosed are a method and a computer program storage product for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. A plurality of downstream processing elements and an upstream processing element are associated with at least one input buffer. Each of the downstream processing elements consumes data packets produced by the upstream processing element received on an output stream associated with the upstream processing element. A fastest input rate among each downstream processing element in the plurality of downstream processing elements is identified. An output rate of the upstream processing element is set to the fastest input rate that has been determined for the plurality of downstream processing elements.

Abstract: The invention concerns a method for scheduling packets belonging to a plurality of flows received at a router. It is also provided the system for carrying out the method. According to the invention, a single packet queue is used for storing said packets, said single packet queue being adapted to be divided into a variable number of successive sections which are created and updated dynamically as a function of each received packet, each section being of variable size and a section load threshold for each flow of said plurality of flows being allocated to each section. The method further comprises insertion (S11; S22; S210; S222; S230) of each received packet of a given flow in one of said successive sections as a function of said given flow and of the corresponding section load threshold.

Abstract: A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.

Abstract: An A/D converter that is attached to a programmable controller (PLC) and sequentially converts an analog value inputted from outside into a digital value. The A/D converter includes: a shared memory that can read-access from a CPU unit that controls the entire PLC and includes a log storage area with a ring buffer configuration for sequentially logging the digital value and a parameter storage area for storing a head pointer serving as a parameter indicating a position where a next log data is stored; and a logging executing unit that writes a digital value in an address indicated by the head pointer in the log storage area as log data and updates the head pointer.

Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract: An adaptive multi-thread buffer supports multiple writer process and reader processes simultaneously without blocking. Writer processes are assigned a reserved write slot using a writer index that is incremented for each write request. When a reserved write slot is not null, the buffer is resized to make room for new data. Reader processes are assigned a reserved read slot using a reader index that is incremented for each read request. When data is read out to the reader process, the read slot content is set to null. When a writer process attempts to write null data to a write slot, the buffer replaces the null write data with an empty value object so that content of the buffer is null only for empty slots. When an empty value object is read from a slot, the buffer replaces the content with null data to send to the reader process.

Abstract: A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU. The method thus distinguishes between A-MSDU outside of the block ACK agreement, which is mandatory, from A-MSDU under the block ACK agreement, which is optional. The method thus complies with the IEEE 802.11n specification while enabling the recipient to intelligently allocate memory during block ACK operations.

Abstract: Herein described are at least a system and a method for regulating data flow in a data pipeline that may be used in a video processing system. The system comprises a processor, one or more data buffers, and one or more processing stations. The one or more data buffers may be used to buffer corresponding processing stations. Each of the one or more processing stations may comprise a switching circuitry that is used to inhibit data transmission when a hold signal is received from the processor. The processor may send the signal in response to a feedback control signal generated by the one or more processing stations. The method may comprise determining if the processing time of a processing station exceeds a specified time. The method further comprises generating a feedback control signal to a processor if the specified time is exceeded.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.

Abstract: This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Abstract: This invention provides an information processing method and apparatus, which can set all extent sizes of data divisionally recorded on a disk to be equal to or larger than the minimum recording unit, and can guarantee continuous reproduction of the divisionally recorded data. Of data divisionally recorded on a recording medium (5), data which corresponds to an end portion of that data and cannot be recorded as a recording area equal to or larger than a minimum recording unit specified in the recording medium (5) due to the presence of a recording area (6) of another data, that has already been recorded on the recording medium (5), is re-recorded on a recording area equal to or larger than the minimum recording unit. At this time, new data is generated by combining data less than the minimum recording unit, and data recorded in another recording area, and the new data is re-recorded on a new recording area.

Abstract: Methods and devices for buffer allocation based on priority levels are disclosed to avoid or mitigate conflicts that can degrade performance or otherwise interfere with Quality of Service (QoS) requirements in a multiple channel memory system. In one embodiment, the methods and devices disclosed herein may be used to detect various transactions that have identical priorities and the same or similar QoS requirements and then allocate buffers for different ones of the various detected transactions that are scheduled to occur in a given time interval to different independent memory channels, thereby avoiding or mitigating memory access conflicts in the given time interval.

Abstract: A buffer management mechanism in a multi-core processor for use on a modem in a telecommunications network is described herein. The buffer management mechanism includes a buffer module that provides buffer management services for one or more Layer 2 applications, wherein the buffer module at least provides a user space application interface to application software running in user space. The buffer management mechanism also includes a buffer manager that manages a plurality of separate pools of tokens, wherein the tokens comprise pointers to memory areas in external memory. In addition, the buffer management mechanism includes a custom driver that manages Data Path Acceleration Architecture (DPAA) resources including buffer pools and frame queues to be used for user plane data distributing.

Abstract: Embodiments of the present invention provide a buffer manager and a buffer management method based on an address pointer linked list. In the embodiments, address pointers of all buffer blocks in a buffer are divided into several groups, lower bits of address pointers in each group are used to record a linked list between the address pointers in the same group, and an address pointer which is pointed by one predetermined address pointer of each group and is in a different group is further recorded to upbuild a linked list between the groups. Thereby, an address linked list can still be stored without a RAM with a width equal to a pointer depth and with a depth equal to the total number of buffer blocks in the buffer as required by the conventional art, which greatly reduces hardware resources required.

Abstract: A data processing apparatus is provided comprising a buffer for buffering data contained in a data stream generated by a data stream generator and received by a data stream receptor. Buffer occupancy tracking circuitry is provided and configured to maintain a high buffer utilisation value providing an indication of a high buffer occupation level for a given time period during utilisation of the buffer. Alternatively, in an apparatus where the buffer is implemented in dedicated memory, the buffer occupancy tracking circuitry is configured to store a programmable buffer size limit controlling a maximum allowable buffer storage capacity.

Abstract: An image scanning device includes a scanning unit configured to execute image scanning of a document and thereby generate image data, at least one processing unit configured to successively process the image data outputted from the scanning unit, a transmission unit configured to transmit the image data outputted from the processing unit, a storage unit, in which multiple buffer areas to be used for transferring the image data among the scanning unit, the at least one processing unit and the transmission unit are allocated, an acquisition unit configured to acquire information on usage status of each of the buffer areas, and a changing unit configured to change storage area allocation at least between two of the buffer areas based on the usage status acquired by the acquisition unit.

Abstract: The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.

Abstract: The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.

Abstract: Disclosed is an electronic device featuring a multi buffer scheme for processing incoming signals. For example, two buffers can be used. A processor can read and process stored signals from a first buffer while an incoming data module can concurrently store signals in a second buffer. Once, the processor is done, it can move on to the second buffer and process signals stored therein while the incoming data module stores signals in the first buffer. Also provided is a flagging scheme for allowing the processor and the incoming data module to control their respective access to the various buffers, so that only one of them accesses a single buffer at any time.

Abstract: A method for sending buffer status information includes checking if a quality of service (QoS) parameter is defined for a first logical channel and at least one condition of the set of predetermined conditions associated with a logical channel group is fulfilled. If the QoS parameter is defined and at least one condition of the set is fulfilled, the method includes setting a number of bits in a media access control header according to a first semantic. The bits carry buffer status information, and the first semantic—is based on the QoS parameter of the first logical channel. Otherwise, the method includes setting the number of bits carrying the buffer status information according to a second semantic that is based on an amount of data available for transmission across the logical channel group.

Abstract: Data is buffered for concurrent writing to tape. For a magnetic tape drive having a magnetic head with multiple sets of transducers; a drive mechanism configured to pass a magnetic tape past the magnetic head; interfaces from two different hosts; and at least one buffer configured to buffer data; and a control; the buffering comprises receiving data from two different hosts at the interfaces; buffering the received data in separate buffer space of the buffer(s) associated with each host, and adjustably size the separate buffer space for each host in accordance with a data transfer rate of the host associated with the separate buffer space; and concurrently writing data from the separate buffer spaces with the magnetic head to separate partitions of the magnetic tape.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional memory buffer in an audio playback device to buffer both output and input data. An application processor coupled to the bi-directional memory buffer is responsive to an indication to write data to the bi-directional memory buffer reads a defined size of input data from the bi-directional memory buffer. The input data read from the bi-directional memory buffer is replaced with output data of the defined size. In response to a mode-change signal, the defined size of data is changed that is read and written from and to the bi-directional memory buffer. The buffer may allow the application processor to enter a low-powered sleep mode more frequently.