Abstract: A variable latency interface and method for managing variable latency. An apparatus includes a storage device controller and a read/write channel coupled to the storage device controller by a variable latency interface. The variable latency interface includes a media control component configured for read and write operations. The variable latency interface also includes a data transfer component configured for read and write operations. A read or write operation in the media control component is offset from a respective read or write operation in the data transfer component by a latency period.

Abstract: Herein described are at least a method and a system for prioritizing the transmission of one or more types of signals through a serial port. Various aspects of the present invention may be implemented using a serial port interface module that facilitates communication between any two devices. In a representative embodiment, the two devices comprise a disk drive controller and a disk drive motor controller used in a hard disk drive. In a representative embodiment, the method and the system are used in the hard disk drive for prioritizing the transmission of multirate voice coil motor (VCM) updates and other asynchronous data signals between the disk drive controller and disk drive motor controller through the serial port.

Abstract: A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: The invention relates to a method for setting an operating parameter in a peripheral IC. In this method, the operating parameter is transmitted from a central IC via a bus connection to the peripheral IC. The method is characterized in that the operating parameter is initially buffered in a preregister in the peripheral IC, and in that the buffered operating parameter is transferred into a working register only if a transfer signal is sent from the central IC via the bus connection. This method has the advantage that, for example in the case of rapidly changing receive conditions in a send/receive unit, adjustment of the send or receive gain setting is very flexible, and it is easy to avoid an incorrect setting due to a detected signal fluctuation. The invention also relates to a device for carrying out said method.

Abstract: The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access signals with first timings to access the first NAND flash IC, and generates a plurality of second access signals with second timings to access the second NAND flash IC, wherein the first timings are different from the second timings. The first NAND flash integrated circuit then accesses data stored therein according to the first access signals. The second NAND flash integrated circuit then accesses data stored therein according to the second access signals.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional buffer in an audio playback device to buffer both output and input data. The audio buffer includes two modes of operation. The first mode replaces large segments of data at a first rate, and the second mode replaces smaller segments of data at a second rate, higher than the first rate. The first mode may make efficient use of the buffer for the output, data while the second mode may provide low latency for the buffering of the input data.

Abstract: Methods and systems for improving communication throughput of a link between SAS/SATA devices. The link, initially established at a first signal rate, is one of a SATA link and a SAS link. A SAS/SATA device increments one of the at least one counter based on an error sensed on the link. Based on the at least one counter, the SAS/SATA device determines whether to maintain the first signal rate. The link is re-established at a second signal rate based on the determination such that the second signal rate is lower than the first signal rate.

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: A method, apparatus, and computer program product for processing a chain linked transport control channel program in an I/O processing system is provided. The method includes receiving a first command message at a control unit specifying a first predetermined sequence number for performing a first set of one or more commands as part of an I/O operation. The method further includes receiving a second command message specifying a second predetermined sequence number for performing a second set of one or more commands as part of the I/O operation. The method also includes comparing the sequence numbers to a next expected predetermined sequence number to determine an order of performing the commands. The method additionally includes executing the commands in the determined order to perform the I/O operation.

Abstract: An apparatus, system, and method are disclosed for converting a synchronous interface into an asynchronous interface. The apparatus includes a receive module, a generate module, and a return module. The receive module receives a request for a transaction from a synchronous requester, the generate module generates a delaying object and a forwarding interface compatible with the requested return type, and the return module returns the delaying object with the forwarding interface to the requester. Additionally, services for implementing such an apparatus, system, and method are disclosed. Implementation of the apparatus, system, and method provide for increased computing performance, reduced application run time, and decreased usage of computing resources.

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract: Systems, methods, and apparatus for facilitating communications between an external controller and Fieldbus devices are described. A primary linking device in communication with the controller and one or more Fieldbus devices may be configured to direct the communication of a timing message to the controller and determine whether a response to the timing message has been received from the controller. Based upon the determination, the primary linking device may direct a switching of communications control to a secondary linking device.

Abstract: A method of operating an automation system with a plurality of automation devices connected for communication with a central unit is provided. Each automation device handles communication in accordance with a send clock. The central unit stores for each automation device accessible for communication information about the send clock for this device in a database. Further, the central unit handles communication with the automation devices according to their individual send clock.

Abstract: A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.

Abstract: A system comprising a scheduler, a first core, and a second core. The scheduler may be configured to prioritize a plurality of input/output (IO) requests. The first core may be configured to process one of the plurality of IO requests based on the prioritizing of the plurality of IO requests. The second core may be configured to process a different one of the plurality of IO requests based on the prioritizing of the plurality of IO requests.

Abstract: Systems and methods (600) for controlling an electronic device (100) with an active processing module (308) having a first and second input/output interface (502, 504). The methods involve interfacing the active processing module and a computing device using the first input/output interface of the active processing module. Thereafter, the active processing module is programmed using a user interface of the computing device. The method also involves interfacing the active processing module and the electronic device using at least the second input/output interface of the active processing module. Subsequently, the operations of the electronic device are controlled using a processing unit (506) of the active processing module and/or a processing unit (424) of the electronic device.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock generated by the internal oscillator. In the processing device, a clock control circuit that switches a system clock between the internal clock and the external clock in accordance with the interface is provided. When the system clock is switched, the switching is performed after the CPU is set in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart the operation.

Abstract: A processor having a core configured to control a keyboard and a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard. A controller is configured to transfer signals from one or more registers through at least one of the pins, intermittently with signals transferred to the keyboard.

Abstract: An article of manufacture, an apparatus, and a method for providing extended measurement word data from a control unit to a channel subsystem of an I/O processing system are disclosed. The article of manufacture includes at least one computer usable medium having computer readable program code logic. The computer readable program code logic performs a method including receiving a command message from the channel subsystem at the control unit, and initiating a timing calculation sequence of a plurality of time values in response to receiving the command message at the control unit. The computer readable program code logic also populates extended measurement word data at the control unit including the plurality of time values, and outputs the extended measurement word data from the control unit to the channel subsystem.

Abstract: Described is a technology by which a virtual hard disk is able to continue servicing virtual disk I/O (reads and writes) while a meta-operation (e.g., copying, moving, deleting, merging, compressing, defragmenting, cryptographic signing, lifting, dropping, converting, or compacting virtual disk data) is performed on the virtual disk. The servicing of virtual disk I/Os may be coordinated with meta-operation performance, such as by throttling and/or prioritizing the virtual disk I/Os. Also described is performing a meta-operation by manipulating one or more de-duplication data structures.

Abstract: Methods and arrangements to model an asynchronous interface are disclosed. Embodiments include transformations, code, state machines or other logic to generate a skew pattern for a semi-static or time-constrained, asynchronous interface and employ the skew pattern in data transfers during a time interval in which the asynchronous interface. Embodiments may than alter the skew pattern in at the expiration of the time interval. In many embodiments, changes to the skew pattern may be substantially non-deterministic. In other embodiments, chances to the skew pattern may follow a heuristic or other dynamic or pre-determined pattern.

Abstract: System and method for controlling the presentation of information, such as dynamically displayed text, includes a computer with a display device and one or more sets of electrode plates and capacitive field sensors arranged facing each other on a substantially flat and substantially stationary surface, such as a table top. The method includes forming capacitive fields between the electrodes and sensors by electrically charging the electrode plates. The sensors monitor for gestural movements made by a user's hands within the fields by detecting changes in voltage levels of the fields. In response to detected gestural movements, the computer adjusts the manner in which the information is presented in the display device, such as the display rate, information source, font size and contrast control.

Abstract: A control device for a USB interface including at least one first terminal for inputting the data to be transmitted and at least one second terminal for the transmission of the packet data on a bus; the packet data include one end-of-packet signal. The USB interface includes one circuit for the data transmission on said at least one second terminal; the USB interface is adapted to receive as an input a signal for the activation of the transmission circuit when data are received from the at least one first terminal and the transmission circuit includes a bias circuit. The control device includes a circuit for the detection of an end-of packet signal on said bus and a control circuit adapted to activate the bias circuit of the transmission circuit if said end-of-packet signal is detected by said detection circuit.

Abstract: An external storage device includes a media control section (10), a monitoring section (20), an interface section (30) and a power control section (40). The media control section (10) drives a recording media and performs data access to the recording media. The monitoring section (20) monitors whether the data access by the media control section (10) can be performed or not. The interface section (30) performs communication with a host device. When the monitoring section (20) detects that the data access can not be performed, the power control section (40) limits power supply to the interface section (30). When the monitoring section (20) detects that the data access can be performed, the power control section (40) re-starts the power supply.

Abstract: Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.

Abstract: The present invention provides a hardware implemented connection monitoring system. A timer array establishes an input timer and an output timer for each connection between the processor and each I/O connection. A state machine periodically steps through the timer array to update the accumulated values of the timers and to monitor if any of the timers has reached a preset, timer done value. If a timer reaches the timer done value, the state machine loads the timer status into an event buffer and generates an interrupt for the processor. The processor reads the event buffer, identifies whether the expired timer was an input timer or an output timer, and takes action accordingly.

Abstract: According to an embodiment on the present invention, a method for controlling a voice recorder is disclosed. The voice recorder is for recording a voice session between an origination device and a destination device. The method can be conveniently executed at a computing apparatus coupled to the origination device and to the voice recorder. The method comprises receiving at least one of a user identifier associated with a user of the origination device and a destination identifier associated with the destination device. The method further comprises generating a voice recording trigger using at least one of data associated with the user identifier and data associated with the destination identifier. The voice recording trigger is then transmitted to the voice recorder to enable the voice recorder to control recording of the voice session between the origination device and the destination device.

Abstract: A system controller includes a memory controller and a host interface residing in different clock domains. There is a time delay between the time when the memory controller issues a read command to a memory and the data becoming present and available at the host interface. The memory controller generates an alarm message at or near the time that it issues the read command. The alarm message indicates to the host interface the time that the data is available for transfer to a host.

Abstract: A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a periodic authorization signal to cause the memory access controller to remove the inhibition and write a predetermined amount of data to the memory through a data bus, and 2) releasing the data bus following writing of the predetermined amount of data to the memory by inhibiting the memory access controller from writing further data.

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract: A buffer management apparatus that sequentially receives L (L>1) types of data and transmits the L types of data to an external device, including: a reception unit that receives data; M (M<L) data storage units, each including a buffer area; an interval storage unit that, for each type of data, stores reception interval information; M timing units, that each time an elapsed time from a last storing of data in a corresponding data storage unit, and a control unit that, if all of the data storage units have been allocated, in particular, to different types of data, according to a judgment result based on the elapsed times and the reception interval information, either stores the received data in at least one of the data storage units in place of previously stored data, or transmits the received data to the external device.

Abstract: A storage system constituted such that power saving to an administrator-desired storage device can be performed from a management device. That is, the storage system comprises a power-saving indication receiving section for receiving from a management console a power-saving indication specifying at least one storage device of a plurality of RAID groups, a plurality of logical units, and a plurality of physical storage devices; and a power-saving controller for saving on power to one or more physical storage devices corresponding to the storage device specified in this power-saving indication.

Abstract: Coprocessor systems for using a main microprocessor DMA channel to write to a port to control a coprocessor system are provided. In certain examples, coprocessor systems are described using a main CPU counter to trigger a DMA channel to perform a single byte transfer to a port used to control coprocessor command timing.

Abstract: A device and a method for exchanging information with registers of a physical layer component. The method includes allocating at least one receive buffer for receiving the status information; associating at least one receive buffer descriptor with the at least one receive buffer; sending to a physical layer component a request to read status information stored in a selected status register of the physical layer component; and writing the status information to the at least one receive buffer descriptor.

Abstract: An interface circuit comprising: a first output circuit configured to allow an access signal to be input thereto and output the access signal to a storage circuit, the access signal capable of being changed to one logic level or the other logic level for accessing the storage circuit; a second output circuit configured to output the access signal outputted from the first output circuit; and a comparison circuit configured to compare the number of times a logic level of the access signal inputted to the first output circuit is changed and the number of times a logic level of the access signal outputted from the second output circuit is changed, and output a comparison signal indicating whether predetermined access has been performed based on the access signal inputted to the first output circuit, after at least a part of the access signal is inputted to the first output circuit.

Abstract: The system according to the present invention for data transfer between microcomputer devices contains a standard protocol controller, a generally known ethernet controller, for example, as a coupling device instead of the known multipart RAM. Instead of a parallel data connection, the microcomputer devices are coupled to one another via a standardized, serial data connection, for example, ethernet. Using functions of ethernet switches already known, a number of microcomputer devices in the system may be increased.

Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.

Abstract: A disk drive is disclosed including a disk comprising a plurality of refresh zones, and a head actuated over the disk. The disk drive further comprises control circuitry for receiving access commands from a host. The control circuitry refreshes a refresh zone in a plurality of segments with an interval between each segment, and processes at least one of the access commands during the interval between at least two of the segments, wherein a size of each segment and the interval ensures an average throughput of access commands received from the host does not fall below a first threshold.

Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: An I/O module samples an industrial process to acquire data indicative of performance of the industrial process. The I/O module has an internal memory in which the data from multiple samples is stored until readout by, or produced to, an industrial controller. The I/O module assigns a time-stamp identifier to the stored samples thereby providing time information to the industrial controller for the stored data when read out by the industrial controller.

Abstract: In one embodiment, the present invention includes a method for transmitting a frame information structure (FIS) message from a host controller or receiving a FIS message at the host controller, transmitting a synchronization signal from the host controller to a port multiplier coupled to the host controller via a link and sustaining a transmit ready signal from the host controller to the port multiplier to thereby lock the link between the host controller and the port multiplier after sending the synchronization signal, and transmitting multiple command FIS messages from the host controller to the port multiplier in a back-to-back manner, where the back-to-back command FIS messages are directed to different devices. Other embodiments are described and claimed.

Abstract: Visualization for active execution tracing pertains to one or more tools used to capture and analyze events leading to a point-of-failure during execution of a function or at least a portion of an application, program, process, or other assemblage of programmable and executable code.

Abstract: In one embodiment, an apparatus includes a driver and a receiver. The driver has an output, wherein the output of the driver has an associated output termination. In addition, the receiver has an input, wherein the input of the receiver has an associated input termination. An interface between the output of the driver and the input of the receiver operates according to a set of one or more timing parameters, wherein the input termination, the output termination, and the set of timing parameters correspond to a bandwidth for data transfer or frequency for data transfer across the interface between the output of the driver and the input of the receiver.

Abstract: Interconnect circuitry for a data processing apparatus is disclosed.

Abstract: A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.

Abstract: A data transmission method for use with a wireless mouse includes the following steps. Firstly, a mouse displacement data including a horizontal displacement and a vertical displacement is periodically transmitted from a wireless signal emitter to a wireless signal receiver in every wireless transmission time interval T1. Then, the horizontal displacement and the vertical displacement of the mouse displacement data are partitioned to acquire plural horizontal sub-displacements and plural vertical sub-displacements, respectively. Afterwards, one of the plural horizontal sub-displacements and one of the plural vertical sub-displacements are periodically transmitted from the wireless signal receiver to the computer system in every wired transmission time interval T2. By the data transmission method, the wired report rate is increased without largely increasing power consumption, and the moving trajectory of the wireless becomes smoother.

Abstract: A master station has a master-station transmission circuit that extracts a serial monitor signal so as to convert a control data signal into monitor data by changing a duty ratio of negative and positive voltage-level periods, converting the control signal into a serial pulsing voltage signal, transmitting a monitor data signal that is superimposed on the serial pulsing voltage signal, and detecting the presence or absence of a signal of a current that flows during the negative and positive voltage-level periods. A plurality of slave stations respectively have a slave-station transmission circuit that identifies a duty ratio of the positive and negative voltage-level periods relative to each serial pulsing voltage signal, that extracts a control data signal so as to output the data to a controllable unit of the slave station.

Abstract: According to some embodiments, an apparatus may be capable of exchanging information with t potential universal serial bus endpoints, where t is an integer greater than 1. Moreover, x endpoint state machines may be established, where x is an integer greater than 1 and less than t. A first endpoint state machine may then be assigned to a first potential endpoint having a pending work item. Before the apparatus has completed the pending work item associated with the first potential endpoint, the first endpoint state machine may be flushed, and the first endpoint state machine may be re-assigned to a second potential endpoint.