Abstract: The mobile device for providing a haptic function includes a vibration unit which generates vibration for a tactile effect as the haptic function; and a control unit which includes a platform providing an application programming interface (API) corresponding to the haptic function and having a plurality of parameters, executes an application prepared by the API, determines a characteristic of the vibration based on the plurality of parameters set up in the application, and controls the vibration unit to generate the vibration having the determined characteristic.

Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.

Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.

Abstract: The invention is directed towards a processing apparatus for a portable communication device. The apparatus includes: a central processing unit, first and second digital signal processing units, a first dual port memory unit adapted to store data shared between the central processing unit and the first digital signal processing unit, and a second dual port memory unit adapted to store data shared between the central processing unit and the second digital signal processing unit. The first dual port memory unit is adapted to store data shared between the first and second digital signal processing units without using the central processing unit.

Abstract: Systems, methods, and apparatus for facilitating communications between an external controller and Fieldbus devices are described. A primary linking device in communication with the controller and one or more Fieldbus devices may be configured to direct the communication of a timing message to the controller and determine whether a response to the timing message has been received from the controller. Based upon the determination, the primary linking device may direct a switching of communications control to a secondary linking device.

Abstract: Described is a technology by which a virtual hard disk is able to continue servicing virtual disk I/O (reads and writes) while a meta-operation (e.g., copying, moving, deleting, merging, compressing, defragmenting, cryptographic signing, lifting, dropping, converting, or compacting virtual disk data) is performed on the virtual disk. The servicing of virtual disk I/Os may be coordinated with meta-operation performance, such as by throttling and/or prioritizing the virtual disk I/Os. Also described is performing a meta-operation by manipulating one or more de-duplication data structures.

Abstract: A system is disclosed comprising a processor, a trace module, a second buffer, and a bridge. The trace module has a first buffer configured to receive trace data from the processor at a first clock frequency. The second buffer is configured to receive trace data from the first buffer at a second clock frequency. The bridge is configured to receive trace data from the second buffer and output the trace data received from the second buffer at a third clock frequency. The second clock frequency is greater than the first clock frequency and the third clock frequency.

Abstract: A data communication control device. The data communication control device includes, a controller comprising a first data storing part, the first data storing part including multiple channels, each channel being applied to store a command for data transfer based on a destination of data, the controller executing the command stored in the channel from the head to transfer data and, an overall controller storing the command in the channel of the first data storing part when the number of commands in a certain channel is not over a upper limit, and stopping to store the command in the channel of the first data storing part and creating a second data storing part and storing the command in the second data storing part when the number of commands in a certain channel is over the upper limit.

Abstract: Disclosed are a method and a computer program storage product for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. A plurality of downstream processing elements and an upstream processing element are associated with at least one input buffer. Each of the downstream processing elements consumes data packets produced by the upstream processing element received on an output stream associated with the upstream processing element. A fastest input rate among each downstream processing element in the plurality of downstream processing elements is identified. An output rate of the upstream processing element is set to the fastest input rate that has been determined for the plurality of downstream processing elements.

Abstract: An interface system is used for interfacing a synchronous circuit with an asynchronous circuit, wherein the synchronous circuit generates, in response to a clock signal, a first control signal for indicating that a first data signal contains valid data, and wherein the asynchronous circuit generates, according to an asynchronous communication protocol, a second control signal indicating the state of transmission of a second data signal.

Abstract: Methods for controlling read data buffering are disclosed. In one of the methods core operations are performed in response to a receipt of a read command from a master controller and an internal or external communication buffer of a data storage node is selected to forward information to the master controller. The data storage node is selected based upon constraints and contents of one or more communication buffers. Information is forwarded from the selected internal or external communication buffer to the master controller.

Abstract: An information processing apparatus registers, in a reservation list, transmission reservation data including a transmission start time and a transmission completion time of charging counter information that is a type of operation information to be regularly transmitted according to a predetermined cycle. The information processing apparatus then registers, in the reservation list, with respect to other types of the operation information to be regularly transmitted (e.g., firmware information), transmission reservation data including a transmission start time and a transmission completion time that are determined so that the operation information is regularly transmitted in a different period than regular transmission of operation information corresponding to transmission reservation data already registered in the reservation list.

Abstract: A “bump” occurs when two devices at the same place at the same time indicate their intention to establish a connection for transferring information. A process for validating bumps is described.

Abstract: A synchronization device includes a receiver that receives data from at least two synchronization devices establishing synchronization, and extracts synchronization information and register selection information from the received data, a transmitter that transmits data to each of the at least two synchronization devices establishing synchronization among a plurality of synchronization devices, a first and a second receiving state register that each stores the extracted synchronization information, a second receiving state register that stores the extracted synchronization information, and a controller that stores the extracted synchronization information into the first receiving state register and the second receiving state register alternately based on the register selection information, and controls the transmitter to transmit data including the register selection information to each of the at least two synchronization devices when the extracted synchronization information is completed in one of the first a

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: To increase the number of analog inputs at low cost, an analog input system includes: one or more analog slave units each connected to a bus to which a CPU unit is connected, and each including an A/D-conversion device converting an analog value outputted by an external device into a first digital value, a buffer memory buffering a second digital value to be transferred to the CPU unit, and a nonvolatile storage device containing specific information of its own unit; and an analog master unit connected to the bus and including an operation section performing operation processing based on the specific information stored in the storage device with the first digital value being used as an input, to calculate the second digital value, the master unit performing on each of the slave input units the operation processing and processing of transferring the calculated second digital value to the buffer memory.

Abstract: A method for data exchange via a bus system, wherein an amount of data determined for data exchange is composed of a plurality of data packets, which data packets are to be transmitted in a predetermined sequence from a second participant of the bus system to a first participant of the bus system, wherein, for data exchange, a first data query is sent from the first participant to the second participant, and wherein, as a reply to the first data query, a first data packet is sent from the second participant to the first participant. Especially after the first participant has received the first data packet, a second data query is sent from the first participant to the second participant via the bus system, and as a reply to the second data query, a second data packet is sent from the second participant to the first participant. The second data packet is either the first data packet or a data packet following the first data packet in the predetermined sequence.

Abstract: A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.

Abstract: A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network (18). Sync signals (46, 56) are generated for each of producer and consumer circuits (12P, 12C) from the address information encoded into requests that communicate the data streams output by the producer circuit (12P) and expected by the consumer circuit (12C). The sync signals (46, 56) for the producer and consumer circuits (12C) are then used to selectively modify the data stream output by the producer circuit (12P) to a format expected by the consumer circuit (12C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (12C) expects more data than output by the producer circuit (12P), and discarding data communicated by the producer circuit (12P) when the consumer expects less data than that output by the producer circuit (12P).

Abstract: A communication speed control application sets the initial communication mode of the USB controller to a full speed mode through a USB driver. If a data transfer start request is received from a USB device using application and if the requested communication speed is a high speed communication mode, the communication speed mode of the USB controller is changed to a high speed mode through the USB driver. The USB application estimates the transfer rate required for the data transfer to be executed and, if the estimated transfer rate is higher than the full speed mode or the transfer rate resulting from subtraction of a predetermined margin from the full speed, the requested communication speed is set to the high speed or is set to full speed otherwise.

Abstract: An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.

Abstract: There is provided a method of context aware data-centric storage for dynamically changing a data storage range comprising: collecting data from entire sensor nodes, after establishing a data storage range of an entire sensor network, dividing areas, and transmitting a message of data storage range information to the entire sensor nodes by a base station; storing the collected data in a storage sensor node by determining whether there is a node responsible for storing the collected data to carry out operation depending on the determination result; determining whether the data storage has not been carried out for a period of time longer than a specified time in each sensor node after storing the data; and to determining whether the scale of invalid range is not smaller than ?.

Abstract: There is provided a content transmission apparatus including a reception unit for performing a receiving process for receiving, from a content output apparatus, a transmission instruction that is based on an output order of pieces of content data, a transmission unit for starting transmission of content data to the content output apparatus in response to the transmission instruction, and a control unit for controlling a time interval for causing the reception unit to perform the receiving process, according to wait information indicating a status of wait until transmission of the content data to the content output apparatus is to be started.

Abstract: This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Abstract: A computer includes first and second processors, first and second I/O devices, a shared memory, and an interrupt controller. The first processor issues a control command for causing the first I/O device to read target data from the first apparatus and store the target data in the shared memory. The first I/O device reads the target data from the first apparatus and, transfers the target data to the shared memory, and generates an I/O complete interrupt. The interrupt controller delivers the generated I/O complete interrupt to the second processor. When the second processor receives the I/O complete interrupt, the second processor issues a control command for causing the second I/O device to read the target data from the shared memory and send the target data to the second apparatus. The second I/O device reads the target data from the shared memory and sends the target data to the second apparatus.

Abstract: Embodiments of the invention are generally directed to adaptive interconnection for multimedia devices. An embodiment of an apparatus includes an apparatus that includes one or more ports, the one or more ports including one or more adaptable ports, where each adaptable port includes a receptacle to accept a plug of a connector element, the receptacle including multiple electrical contacts. The apparatus further includes an adaptable port device to process data including multimedia data received at the one or more adaptable ports, where the adaptable port device is to detect a multimedia signal format for multimedia data received at each of the adaptable ports, and adapt each of the adaptable ports to be compatible with the detected multimedia signal format for the adaptable port.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: The present invention concerns a data transfer system for transferring data signals between a system input and a system output, and associated products. The system comprises a first data consuming set, receiving the data signals (SGNL1) from the system input, writing them therein and reading them for sending them towards a second data consuming set, the second set receiving the data signals (SGNL0), writing them therein and reading them for sending them (SGNL2) to the system output, and transfer means transferring the data signals from the first to the second data consuming set. The first set incorporates within the data signals to be transmitted, read requests (rd_req1) for reading the data signals from the first data consuming set. The transfer means carry those read requests with the data signals, and the second set receives them for synchronization between the first and second sets.

Abstract: A plurality of devices are operated by storing at a device a first ID number received at a first port of the device and a second ID number received at a second port of the device. The device receives a data command through at least one of the first and second ports. The data command has a command ID number. The device executes the data command when at least one of the command ID number is equal to the first ID number when the data command is received at the first port and the command ID number is equal to the second ID number when the data command is received at the second port.

Abstract: An exemplary signal collection system includes a signal transmitting module, a computer, and a data collection card. The signal transmitting module includes a signal source and a delay chip. The delay chip receives a first path high-speed signal output from the signal source and transmits the first path high-speed signal to the data collection card in real time. The computer sends a delay command to the data collection card and the data collection card transfers the delay command to the delay chip. The delay chip generates a second path high-speed signal by delaying the first path high-speed signal in response to the delay command and transmits the second path high-speed signal to the data collection card. The data collection card transmits the high-speed signals output from the delay chip to the computer. A signal collection method based upon the signal collection system is also provided.

Abstract: A method of facilitating communications between a computer device and a smart card reader having an associated smart card, the computer device including a smart card resource manager and a smart card reader service, the smart card reader service acting as a relay for commands between the smart card resource manager and the smart card reader, the method comprising: receiving from the smart card resource manager a first command for setting a protocol for communications with the smart card; and responding, prior to receiving a reply from the smart card to the first command, to the smart card resource manager with a message indicating that the smart card has successfully received the first command.

Abstract: A computer-implemented method may include determining a number of virtual functions that each port of a hardware input/output adapter is capable of supporting. The computer-implemented method may include assigning a first portion of internal resources of the hardware input/output adapter to each port of the hardware input/output adapter. The computer-implemented method may also include, for a particular port of the hardware input/output adapter, assigning a second portion of the internal resources to each virtual function that the particular port is capable of supporting. The second portion of the internal resources may be a subset of the first portion of the internal resources. The computer-implemented method may further include configuring a virtual function prior to a runtime to use the assigned second portion of the internal resources.

Abstract: An electronic device is adapted to be connected to a plurality of peripheral devices, and includes a storage unit and a control circuit. The storage unit records a preset time and a control list. The control list lists at least a selected one of the electronic device and the peripheral devices, and an operation mode therefor. The control circuit detects whether the preset time matches a reference time, and if so, controls operation of the selected one of the electronic device and the peripheral devices according to settings in the control list.

Abstract: A method and apparatus for predictive switching an output have been disclosed.

Abstract: A television with at least one connection, either wired or wireless. Detection of an active device connected to the connection results in proper software and hardware configuration of the television to properly communicate with the device and provide, for example, proper user interface support and access to the device.

Abstract: A motherboard assembly includes a motherboard having an expansion slot and a storage device interface, and a serial advanced technology attachment dual in-line memory module (SATA DIMM) with a circuit board. A control chip and a storage chip are arranged on the circuit board. Two voids are defined in a top side of the circuit board. A first extending board is formed on the top side of the circuit board between the voids. An edge connector is arranged on the first extending board and connected to a power supply. The edge connector includes power pins connected to the control chip and the storage chip. A second extending board is extended from an end edge of the circuit board and includes a connector connected to the storage device interface of the motherboard. A bottom side of the second extending board is in alignment with a bottom side of the circuit board.

Abstract: In some embodiments of the present invention, host systems and/or devices are made to be capable of employing asynchronous or synchronous modes. For example, for storage devices capable of finishing I/O requests in a sufficiently small amount of time, e.g., a few microseconds, host system software may perform the storage I/O request synchronously by polling for a completion.

Abstract: A process is provided for transferring a first sequence control and/or first data into a first control device and a second sequence control and/or second data into a second control device in a motor vehicle. The transfer is carried out by way of a first data bus while using a first transmission protocol which has a data frame with a predetermined frame format or message format, and the transfer as a whole takes place by the transmission of a plurality of data frames. In a first step, by way of a first data frame, a portion of the first sequence control and/or of the first data is transmitted to the first control device. In a second step, by way of the second data frame, a portion of the second sequence control and/or of the second data is transmitted to the second control device.

Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.

Abstract: Some of the embodiments of the present disclosure provide a method for operating a first in first out (FIFO) memory system in different clock domains, the method comprising receiving a write request in a first clock domain; generating, by a write shift and truncation module in response to receiving the write request, a shifted series of binary numbers such that the shifted series of binary numbers is a reduced sub-set of a first series of binary numbers; and generating, by a binary to Gray conversion module, a series of Gray code numbers corresponding to the shifted series of binary numbers. Other embodiments are also described and claimed.

Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.

Abstract: A system and method for enabling legacy media access control (MAC) to do energy efficient Ethernet (EEE). A backpressure mechanism is included in an EEE enhanced PHY that is responsive to a detected need to transition between various power modes of the EEE enhanced PHY. Through the backpressure mechanism, the EEE enhanced PHY can indicate to the legacy MAC that transmission of data is to be deferred due to a power savings initiative in the EEE enhanced PHY.

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.

Abstract: A method of machine control can include providing at least a system master signal, selectively synchronizing at least sub-system master signal to the system master signal based on the value of the system master signal, and carrying out at least one operation based on the value of the other master signal. For example, a machine controller may provide a system virtual master signal and synchronize one or more module virtual master signals to the system virtual master based on the system virtual master count value. One or more components of the module may operate based on the count value of the module virtual master signal. The use of an asynchronous control method may advantageously increase the flexibility of the machine. Because the operation of the components of the machine may depend on respective virtual master signals, a machine using asynchronous control methods may advantageously continue operating one component or module in the event of a fault involving other components.

Abstract: A computer program product is provided for performing input/output (I/O) processing at a host computer system. The computer program product is configured to perform: generating an address control structure for each of a plurality of consecutive data transfer requests specified by an I/O operation, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW) that includes an Offset field indicating a relative order of a data transfer request; generating and storing in local channel memory at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests and including an Expected Offset field indicating a relative order of an expected data transfer request; receiving a transfer request from the network interface and comparing the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order.

Abstract: A data transfer system includes a PCI Express transaction layer having an input for serially receiving posted and non-posted request packets and completion packets; an application layer coupled to the PCI Express transaction layer for receiving posted and non-posted request packets and completion packets from the PCI Express transaction layer; a first transmission interface coupling the application layer to the PCI Express transaction layer; and a second transmission interface coupling the application layer to the PCI Express transaction layer. The PCI Express transaction layer transmits posted and non-posted request packets to the application layer over the first transmission interface and transmits completion packets to the application layer over the second transmission interface.

Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.