Synchronous Data Transfer Patents (Class 710/61)
  • Patent number: 10897595
    Abstract: A system includes a downstream facing port (DFP) coupled to a video source, an upstream facing port (UFP) coupled to a video sink, and a cable. The cable includes a first end that is connected to the DFP and a second end that is connected to the UFP. The cable is configured to carry a differential auxiliary transmission signal and detect polarity in the differential auxiliary transmission signal.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: January 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charles Michael Campbell, Anwar Sadat, Mark Edward Wentroble
  • Patent number: 10732670
    Abstract: A real-time clock module includes a clocking circuit configured to generate clocking data based on a clock signal, an output terminal, a memory circuit configured to store output control information for controlling an output of a signal from the output terminal and output value information in which a value of the signal output from the output terminal is set, and an interface circuit configured to receive a setting value of the output control information and a setting value of the output value information. When the setting value of the output control information is a first setting value, the real-time clock module outputs a first signal based on the setting value of the output value information from the output terminal.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: August 4, 2020
    Assignee: Seiko Epson Corporation
    Inventor: Toshiya Usuda
  • Patent number: 10168979
    Abstract: A technique provides a sync notification to indicate when a shared screen view of a presenter device has been delivered to an audience. The technique involves generating a sync time estimation based on communications with a set of audience devices, and detecting occurrence of an update to the shared screen view of the presenter device. The technique further involves outputting, after the sync time estimation has elapsed since the detected occurrence of the update, the sync notification on the presenter device to indicate when the shared screen view of the presenter device has been delivered to the audience. Such a technique is well suited for a variety of online collaboration systems such as online conference systems, online webinar systems, online meeting systems, and so on.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 1, 2019
    Assignee: GetGo, Inc.
    Inventors: Yogesh Moorjani, Ashish V. Thapliyal
  • Patent number: 9940288
    Abstract: The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include operatively connecting one or more lane modules of an integrated circuit (IC) to form one or more links. The method may further include associating a FIFO reset generator with each of the one or more lane modules and receiving a signal from the FIFO reset generator at a synchronization FIFO. The method may also include aligning, at the synchronization FIFO, one or more enqueue pointers and dequeue pointers.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: April 10, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Loren Blair Reiss, Fred Staples Stivers, Scott Gerald Bare
  • Patent number: 9804633
    Abstract: A method for indirectly measuring the clock rate of a media rendering subsystem, in a media rendering device that has a separate hardware clock for rendering the media, by using the rate at which data requests are made of the CPU in the media rendering device and using the CPU clock to provide additional accuracy in measuring the clock rate.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: October 31, 2017
    Assignee: Blackfire Research Corporation
    Inventors: Ravi U Rajapakse, Ian McIntosh
  • Patent number: 9667406
    Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: May 30, 2017
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Richard E. Perego, Craig E. Hampel
  • Patent number: 9436396
    Abstract: A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The storage controller is configured to receive a read request targeted to the data storage medium, and identify at least a first storage device of the plurality of storage devices which contains data targeted by the read request. In response to either detecting or predicting the first storage device will exhibit variable performance, the controller is configured to generate a reconstruct read request configured to obtain the data from one or more devices of the plurality of storage devices other than the first storage device.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: September 6, 2016
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, John Hayes, Bo Hong, Feng Wang, Ethan Miller, Craig Harmer
  • Patent number: 9429980
    Abstract: A processor according to embodiments comprises an on-board sample rate converter for converting a source audio signal that is sampled at a first sampling rate to an output audio signal that is sampled at a second sampling rate. The sample rate converter utilizes a master clock signal in converting the audio signal. The sample rate converter selects the master clock signal from available reference clock signals, such as an on-chip system clock or a bus interface clock, and scales the frequency of the selected clock signal to generate the master clock signal with the frequency of the second sampling rate.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: August 30, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Yong Yuenyongsgool, Igor Wojewoda, Sergey Pavlov, Anton Alkhimenok, Kim Otten
  • Patent number: 9348782
    Abstract: An electronic device assembly includes a main device, and a plurality of peripheral devices. The main device includes a first connector. Each of the plurality of peripheral devices includes two second connectors. Each first connector and second connector includes various types of interfaces, and the plurality of peripheral devices is coupled to the main device via the various types of interfaces; each peripheral device is coupled to another peripheral device via the second connector, to connect the plurality of peripheral devices one by one in series.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: May 24, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Ching-Chung Lin
  • Patent number: 9216070
    Abstract: A user-guided configuration routine for use with a remote catheter guidance system configured to calibrate of one or more medical devices of the remote catheter guidance system with minimal user input. The user-guided configuration routine being configured to determine the appropriate configuration steps from diagnostic data received from the remote catheter guidance system or from a user.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: December 22, 2015
    Assignee: St. Jude Medical, Atrial Fibrillation Division, Inc.
    Inventors: Kulbir S. Sandhu, Venkata Adusumilli, Devanshi Shah, Jimmy Quoc Hy Duong
  • Patent number: 9213487
    Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: December 15, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Narasimhan Vasudevan, Li Pan, Michael Thomas Fertsch, Nan Chen
  • Patent number: 9128711
    Abstract: A computer system is provided. In one embodiment, the computer system includes a memory, a peripheral device, a central processing unit (CPU), and a peripheral device controller. The CPU stores information about the data transmission in a descriptor in the memory when data transmission between the CPU and the peripheral device is required. The peripheral device controller reads the descriptor from the memory at an access frequency, records whether the descriptor read from the memory requests for data transmission as a recording result, and adjusts the access frequency according to the recording result.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: September 8, 2015
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Shanna Pang, Zhiqiang Hui, Chin-Hwaun Wu, Cheng-Wei Huang
  • Patent number: 9118678
    Abstract: A method for indirectly measuring the clock rate of a media rendering subsystem, in a media rendering device that has a separate hardware clock for rendering the media, by using the rate at which data requests are made of the CPU in the media rendering device and using the CPU clock to provide additional accuracy in measuring the clock rate.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: August 25, 2015
    Assignee: Blackfire Research Corporation
    Inventors: Ravi U Rajapakse, Ian McIntosh
  • Patent number: 9065560
    Abstract: A method for checking the operation of a PSI5 reception unit in a motor vehicle controller is presented, wherein the PSI5 reception unit receives signals from a connected PSI5-compliant PSI5 transmission unit, wherein a check signal transmission unit is provided and this check signal transmission unit sends a prescribed check signal to the PSI5 reception unit at prescribed check times at which no signal can be expected from the PSI5 transmission unit, in particular—together with the sending of one or more synchronization pulses to the transmission unit—the check signal transmission unit sends the check signal in this defined period.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: June 23, 2015
    Assignee: Continental Automotive GmbH
    Inventor: Reinhard Hamperl
  • Patent number: 9030245
    Abstract: Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 12, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Mototada Sakashita, Satoshi Morishita, Yoshinori Matsui, Yasushi Matsubara
  • Patent number: 9026698
    Abstract: Techniques and mechanisms for providing access to a function with an input/output (I/O) device. In an embodiment, a main memory of a computer system including the I/O device stores a function-context data structure associating a function with a context for an access to the function. The I/O device stores a configuration for the I/O device to provide the function. In another embodiment, the software process exchanges information with the function-context data structure for the access to the function. The I/O device performs a synchronization of the function-context data structure and the configuration data structure with respect to one another, wherein the function-context data structure operates as a register level interface which interfaces the I/O device and the software process with one another.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Annie Foong, Debendra Das Sharma
  • Patent number: 9009371
    Abstract: A device is described for establishing communication between a first device and a second device. In one implementation, a first internal interface of the first device couples to a first external interface of the second device while a second internal interface of the first device couples to a second external interface of the second device. A first unidirectional data channel may be opened for incoming data using the first internal interface. A second unidirectional data channel may be opened for outgoing data using the second internal interface. The pair of unidirectional data channels is established, allowing data transfer between the devices. These channels allow for asynchronous-like transmission of data, in that transmission and corresponding receipt of data may take place at irregular intervals.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 14, 2015
    Assignee: Amazon Technologies, Inc.
    Inventor: Richard William Mincher
  • Patent number: 9009380
    Abstract: A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus. At least two buffers are configured to store data. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, with the counting value of the SOF counter being compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves or exceeds the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 14, 2015
    Assignee: VIA Technologies, Inc.
    Inventors: Jiin Lai, Chin-Sung Hsu, Terrance Shiyang Shih, Jinkuan Tang, Buheng Xu, Hui Jiang
  • Publication number: 20150089098
    Abstract: A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony.
    Type: Application
    Filed: December 1, 2014
    Publication date: March 26, 2015
    Inventor: Peter Graham FOSTER
  • Patent number: 8990457
    Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Tomofumi Iima
  • Patent number: 8990605
    Abstract: A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: March 24, 2015
    Assignee: Spansion LLC
    Inventors: Clifford Alan Zitlaw, Wendy P. Lee-Kadlec, Feng Liu
  • Publication number: 20150067202
    Abstract: In a method for synchronizing a control unit and at least one peripheral unit having actuators and/or sensors, the control unit and the peripheral unit exchange data with each other via a serial interface. The control unit transmits data to the at least one peripheral unit which is processed in the peripheral unit for the operation of the actuators and/or sensors, and at least one synchronization character is transmitted from the control unit to the peripheral unit for the synchronization. In this context, the synchronization character is appended by the control unit to a first data sequence of a data stream to be transmitted from the control unit to the peripheral unit, and the transmission of a second data sequence to be transmitted after the first data sequence is delayed in time on the part of the control unit, so that the second data sequence is transmitted by the control unit to the peripheral unit following the synchronization character.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 5, 2015
    Inventor: Robert Wastlhuber
  • Publication number: 20150039791
    Abstract: A system for synchronising the operation of a measurement instrument having a microcontroller, a local oscillator and function circuitry to an external timebase is provided. The system includes a USB Host Controller; an interrupt generator adapted to respond to ITPs by generating respective interrupts and passing the interrupts to the microcontroller; and a timer for measuring an interval between receptions of the ITPs in a time domain of the local oscillator.
    Type: Application
    Filed: September 15, 2014
    Publication date: February 5, 2015
    Inventor: Peter Graham FOSTER
  • Patent number: 8943351
    Abstract: A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 27, 2015
    Assignee: Chronologic Pty. Ltd.
    Inventor: Peter Graham Foster
  • Patent number: 8935443
    Abstract: The description generally relates to a system designed to synchronize the rendering of a media file between a master device and a sister device. The system is designed so that a media file is simultaneously rendered on a master device and a sister device beginning from identical temporal starting points.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: January 13, 2015
    Assignee: Empire Technology Development LLC
    Inventors: Gene Fein, Edward Merritt
  • Patent number: 8935444
    Abstract: A method of controlling a plurality of external devices is performed on a computer which is set up with a plurality of remote control processes corresponding to the plurality of the external devices, and a management process for managing the remote control processes while communicating with the remote control processes. The management process is called to display icons corresponding to the remote control processes in a display field provided by the management process. Further, the management process acts when a specified operation is applied to one of the icons on the display field for sending a screen open instruction to one of the remote control processes corresponding to the icon to which the specified operation is applied. The remote control process which receives the screen open instruction is activated to display a control screen for use in remotely controlling the corresponding external device.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: January 13, 2015
    Assignee: Yamaha Corporation
    Inventors: Tatsuya Umeo, Takao Yamamoto, Masaaki Okabayashi, Hideo Miyamori
  • Patent number: 8918667
    Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: December 23, 2014
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
  • Patent number: 8914564
    Abstract: A method of controlling a port in an apparatus includes receiving an instruction for execution by a processor. The method further includes executing the instruction, by writing a value to a storage location corresponding to the port, and by initializing a count operation. The method further includes proceeding with the count operation until a final count value is reached, and providing to the port the value written to the storage location.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: December 16, 2014
    Assignee: Silicon Laboratories Inc.
    Inventor: Thomas Saroshan David
  • Patent number: 8914563
    Abstract: An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: December 16, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Bradley Martin, Thomas Saroshan David, Alan Lee Westwick
  • Patent number: 8909828
    Abstract: According to one embodiment, an electronic device including, a display, an audio output module, a transmission module, a first detection module, a second detection module, a third detection module, and a controller configured to control at least one of the timing of the transmission of the audio signal by the transmission module and the timing of the output of the first reproduction output by the audio output module in accordance with the time difference detected by the third detection module, and to switch whether or not to control the timing in accordance with the positional relationship between the electronic device and the partner device.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Minemura
  • Publication number: 20140351459
    Abstract: A synchronization method is provided for a peripheral apparatus. The peripheral apparatus comprises a first peripheral device and a second peripheral device, wherein the first peripheral device is coupled to a host and the first peripheral device runs in a first operation mode. The synchronization method comprises the following steps: when a second peripheral device is coupled to the host, the second peripheral device obtains a synchronization signal from the host; and the second peripheral device runs in a second operation mode based on the synchronization signal, wherein the second operation mode is same as the first operation mode.
    Type: Application
    Filed: May 21, 2013
    Publication date: November 27, 2014
    Applicant: DEXIN CORPORATION
    Inventor: YUAN-JUNG CHANG
  • Patent number: 8898354
    Abstract: Devices and methods for generating timing signals at a rate that matches a rate of remotely generated timing signals are provided. In some embodiments, a host generates timing signals in accordance with a USB specification, such as keep-alives, start-of-frame packets, or ITPs. An upstream facing port transmits the timing signals over a network to a downstream facing port. The downstream facing port generates and transmits timing signals to a USB device at a predetermined rate, and alters the predetermined rate based on an analysis of the rate at which timing signals are received from the upstream facing port.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: November 25, 2014
    Assignee: Icron Technologies Corporation
    Inventor: Keith Kejser
  • Patent number: 8892791
    Abstract: An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link from the controller to each module. Each communication link includes a data out line, a data in line and a clock line, where each clock line is derived from one clock source.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: November 18, 2014
    Assignee: Keysight Technologies, Inc.
    Inventors: James P. McKim, Jr., John W. Hyde, Marko Vulovic, Buck H. Chan, John F. Kenny, Richard A. Carlson
  • Patent number: 8874812
    Abstract: A method for communicating media between a host and a display system. In one embodiment the method comprises acquiring, by the host and via a wireless connection between the host and the display system, display information of the display system; generating, by the host, an image sequence at a resolution and a frame rate, the resolution and the frame rate determined from the display information; communicating, from the host to the display system and via the wireless connection, an encoding of the image sequence; and displaying, by the display system, a decoding of the encoding.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: October 28, 2014
    Assignee: Teradici Corporation
    Inventors: David Victor Hobbs, Ian Cameron Main
  • Publication number: 20140281062
    Abstract: Techniques and mechanisms for providing access to a function with an input/output (I/O) device. In an embodiment, a main memory of a computer system including the I/O device stores a function-context data structure associating a function with a context for an access to the function. The I/O device stores a configuration for the I/O device to provide the function. In another embodiment, the software process exchanges information with the function-context data structure for the access to the function. The I/O device performs a synchronization of the function-context data structure and the configuration data structure with respect to one another, wherein the function-context data structure operates as a register level interface which interfaces the I/O device and the software process with one another.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: David J. Harriman, Annie Foong, Debendra Das Sharma
  • Patent number: 8832339
    Abstract: Synchronous interfaces on a first device are configured such that a first synchronous interface is set to a slave mode while a second synchronous interface is set to a master mode. A second device with two synchronous interfaces may then be coupled to the first device with the corresponding synchronous interfaces in master mode and slave mode, respectively. A pair of unidirectional synchronous data channels is established, allowing data transfer between the devices. These channels allow for asynchronous-like transmission of data, in that transmission and corresponding receipt of data may take place at irregular intervals.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 9, 2014
    Assignee: Amazon Technologies, Inc.
    Inventor: Richard William Mincher
  • Patent number: 8825889
    Abstract: A system and method is provided for rate limiting network traffic flow of an untrusted application. A master module in a server environment manages network traffic flow restrictions. A slave module executes client applications in the server environment. A services module in the server environment executes a trusted application to validate the client application to the master module. A traffic restriction module on the master module sets network traffic restrictions when validation has not been received for the client application on the slave blade, and receives client application validations from the trusted application to unrestrict network traffic flow for the client application on the slave blade.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: September 2, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael R. Smith, Sean E. Humphress, Dante Vitale
  • Patent number: 8826057
    Abstract: A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of inputs electrically coupled to outputs of a corresponding plurality of delay elements in the data pipeline. The latency selection circuit is configured to pass a data pipeline signal from an output of a selected one of the plurality of delay elements in response to a latency control signal. A synchronization circuit is provided, which is electrically coupled to an output of the latency selection circuit. This synchronization circuit, which includes first and second unequal timing paths therein, is responsive to a clock that synchronizes capture of the data pipeline signal selected by the latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured data pipeline signal as active.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: September 2, 2014
    Assignee: Integrated Device Technology Inc.
    Inventors: Bruce Lorenz Chin, David Stuart Gibson
  • Patent number: 8806091
    Abstract: A signal generating apparatus, applicable in a universal serial bus (USB) device, includes: a first determining circuit for receiving a data signal to determine if the data signal is generated by the universal serial bus device, and generating a first determined result; a second determining circuit coupled to the first determining circuit for receiving the data signal and the first determined result to determine a transmitting mode corresponding to the data signal according to the first determined result, and generating a second determined result; and a frequency generating circuit coupled to the second determining circuit for generating a first clock signal utilized for synchronizing the data signal according to the second determined result.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: August 12, 2014
    Assignees: Silicon Motion Inc., Silicon Motion Inc.
    Inventor: Chin-Hsien Yen
  • Patent number: 8799541
    Abstract: According to one embodiment, a transmitter including an AV transmission unit including a first transmission unit which transmits video/audio data according to a method 1, and a second transmission unit which transmits video/audio data according to a method 2, with a clock signal inserted in a data signal, and a communication unit which performs the information communication with the receiver by a predetermined standard signal, a communication channel switch unit which transfers a video clock signal to a clock terminal of an HDMI if the video/audio data is transmitted by the first transmission unit, or transfers a first predetermined standard signal output from the communication unit if the video/audio data is transmitted by the second transmission unit, while the communication channel switch unit transfers a second predetermined standard signal received by an HPD/RSV terminal of the HDMI even in transmission by any of the first and second transmission units.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: August 5, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Doi, Nobuaki Suzuki, Masahiko Mawatari
  • Patent number: 8781297
    Abstract: A method for providing a content entity from a storage disc is described. The storage disc comprises at least one further content entity. Each content entity comprises a main menu and at least one submenu accessible via the main menu. The storage disc further comprises an entity selection menu. The entity selection menu comprises a link to the main menu of the content entity to be provided. The method comprises providing the entity selection menu for reproduction, receiving a selection of the content entity to be provided, detecting that the storage disc comprises a plurality of content entities, mapping a pre-defined start address to a different start address and providing the selected content entity for reproduction based on the different start address. The pre-defined start address is mapped to a different start address of the storage disc associated with the main menu of the selected content entity to be provided.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 15, 2014
    Assignee: Nero AG
    Inventor: Richard Lesser
  • Patent number: 8775701
    Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 8, 2014
    Assignee: Altera Corporation
    Inventor: Ryan Fung
  • Patent number: 8751705
    Abstract: According to one embodiment, an electronic device including, a display, an audio output module, a transmission module, a first detection module, a second detection module, a third detection module, and a controller configured to control at least one of the timing of the transmission of the audio signal by the transmission module and the timing of the output of the first reproduction output by the audio output module in accordance with the time difference detected by the third detection module, and to switch whether or not to control the timing in accordance with the positional relationship between the electronic device and the partner device.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Minemura
  • Patent number: 8719474
    Abstract: An interface, for communication between an internal device and an external device, includes two bus lines of a bus for bidirectional data transfer and at least a first control line, by means of which a control signal can be transferred from the external device to the internal device.
    Type: Grant
    Filed: December 19, 2009
    Date of Patent: May 6, 2014
    Assignee: Faro Technologies, Inc.
    Inventors: Martin Ossig, Reinhard Becker, Andreas Ditte
  • Patent number: 8706262
    Abstract: A system program causes, as an execution preparation process for a control operation of a PLC, execution of a process for generating a reception buffer for storing received input data, and execution of a process for generating, for each input data referred to by a control program, an input synchronization buffer used by the control program as a reference target for the input data. The system program causes, as an execution control process for the control operation of the PLC, execution of an input copy process for copying the received input data from the reception buffer to the input synchronization buffer corresponding to the input data, and execution of a control program start process for starting execution of the control program.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: April 22, 2014
    Assignee: Omron Corporation
    Inventors: Yoshihide Nishiyama, Shigeyuki Eguchi, Osamu Hamasaki, Tatsuya Kojima
  • Patent number: 8688874
    Abstract: A method of controlling one or more devices in data communication with a common controller to perform one or more functions, each of the devices having a synchronous clock, a synchronized real time clock register and a memory, the method comprising: arming the devices such that the devices commence performing the functions synchronously, receive and store to their respective memory data acquired as a result of performing the functions and store to their respective memory time stamp information indicative of the time of acquisition of the acquired data; a trigger device in data communication with the common controller responding to a command to perform the functions by sending a first message to the host controller that includes data indicative of a time of receipt of the command; the host controller responding to the first message by sending the devices a second message including data indicative of the time of receipt by the further device of the command; and the devices responding to the second message by re
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: April 1, 2014
    Assignee: Chronologic Pty. Ltd.
    Inventor: Peter Foster
  • Patent number: 8656073
    Abstract: A method according to one embodiment includes receiving, at an I/O Handler, an instruction to initiate a backup operation on data associated with an application running on multiple servers; and stretching communication between instances of the application and data storage volumes associated therewith during initiating the backup operation. Additional systems, methods, and computer program products are also disclosed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ofer Elrom, Eran Raichstein, Gregory John Tevis
  • Patent number: 8656072
    Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: February 18, 2014
    Assignee: Sanmina-SCI Corporation
    Inventors: Jonathan R. Hinkle, Paul Sweere
  • Patent number: 8645603
    Abstract: In one embodiment, a main circuit board includes a plurality of expansion slots that are operative to receive a corresponding plurality of expansion cards. The plurality of expansion slots include at least one first expansion slot configured at a first position on the main circuit board, that is operative to connect to at least one corresponding first expansion card. At least one second expansion slot configured at a second position on the main circuit board, and the second expansion slot is operative to connect to at least one corresponding second expansion card. The plurality of expansion cards includes at least one secondary expansion card that is different from the main circuit board and that is configured to be operatively coupled to at least one of the plurality of expansion slots. One or more particular expansion slots are selected for connecting one or more corresponding particular expansion cards, based on the size, dimensions, and/or function of the particular expansion cards to be connected.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: February 4, 2014
    Assignee: Itron, Inc
    Inventors: Charles W. Melvin, Jr., Phillip Warren, Michael Dempsey
  • Patent number: 8607089
    Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: December 10, 2013
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Robert W. Faber