Abstract: In one embodiment, electronic circuitry comprises a first circuit capable of transmitting and receiving signals, a second circuit capable of transmitting and receiving signals, and an insulation element. The first circuit has a first terminal to which a first clock signal is input, increases the frequency of the first clock signal to generate a second clock signal, and transmits the second clock signal. The insulation element transmits the second clock signal obtained from the first circuit to the second circuit as a third clock signal. The second circuit receives the third clock signal from the insulation element, and transmits a first data signal in response to the third clock signal. The insulation element transmits the first data signal obtained from the second circuit as a second data signal. The first circuit receives the second data signal from the insulation element.

Abstract: Profile switching for memory overclocking is described. In accordance with the described techniques, a memory is operated according to a first memory profile. During operation of the memory according to the first memory profile, a request is received to operate the memory according to a second memory profile. Responsive to the request, operation of the memory is switched to operate according to the second memory profile without rebooting. In one or more implementations, at least one of the first memory profile or the second memory profile comprises an overclocking memory profile that configures the memory to operate in an overclocking mode. In one or more implementations, the memory is trained to operate according to the overclocking memory profile prior to operating the memory according to the first memory profile.

Abstract: The present technology relates to an information processing apparatus, information processing method, transmission apparatus, and transmission method, capable of improving the convenience of a voice AI assistance service used in cooperation with content. The convenience of the voice AI assistance service used in cooperation with the content can be improved by providing an information processing apparatus including a control unit configured to control a timing of a voice response upon using a voice AI assistance service in cooperation with content on the basis of voice response time information indicating time suitable for the voice response to an utterance of a viewer watching the content. The present technology can be applied to a system in cooperation with a voice AI assistance service, for example.

Abstract: A method for controlling operations of an asynchronous FIFO memory includes: determining a current depth of the asynchronous FIFO memory according to at least one of a clock ratio, a burst length and a continuous transmission length, where the clock ratio is a ratio of a frequency of a first clock signal used by a master device to a frequency of a second clock signal used by a slave device; configuring one or more entries of the asynchronous FIFO memory to be used according to the current depth; and controlling a plurality of FIFO clock signals provided to the asynchronous FIFO memory according to the current depth. One FIFO clock signal corresponds to one entry, and one or more FIFO clock signals corresponding to one or more entries that are not configured according to the current depth are disabled.

Abstract: Systems, methods, computer program products, and apparatuses for low latency, fully reconfigurable hardware logic for ensemble classification methods, such as random forests. An apparatus may comprise circuitry for an interconnect and circuitry for a random forest implemented in hardware. The random forest comprising a plurality of decision trees connected via the interconnect, each decision tree comprising a plurality of nodes connected via the interconnect. A first decision tree of the plurality of decision trees comprising a first node of the plurality of nodes to: receive a plurality of elements of feature data via the interconnect, select a first element of feature data, of the plurality of elements of feature data, based on a configuration of the first node, and generate an output based on the first element of feature data, an operation, and a reference value, the operation and reference value specified in the configuration of the first node.

Abstract: A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.

Abstract: Systems and/or methods can include a ring based inverter chain that constructs multi-bit flip-flops that store time. The time flip-flops serve as storage units and enable pipeline operations. Single cells used in time series analysis, such as dynamic time warping are rendered by the time-domain circuits. The circuits include time flip-flops, Min, and ABS circuits. A and the matrix can be constructed through the single cells.

Abstract: A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.

Abstract: A system includes a downstream facing port (DFP) coupled to a video source, an upstream facing port (UFP) coupled to a video sink, and a cable. The cable includes a first end that is connected to the DFP and a second end that is connected to the UFP. The cable is configured to carry a differential auxiliary transmission signal and detect polarity in the differential auxiliary transmission signal.

Abstract: A real-time clock module includes a clocking circuit configured to generate clocking data based on a clock signal, an output terminal, a memory circuit configured to store output control information for controlling an output of a signal from the output terminal and output value information in which a value of the signal output from the output terminal is set, and an interface circuit configured to receive a setting value of the output control information and a setting value of the output value information. When the setting value of the output control information is a first setting value, the real-time clock module outputs a first signal based on the setting value of the output value information from the output terminal.

Abstract: A technique provides a sync notification to indicate when a shared screen view of a presenter device has been delivered to an audience. The technique involves generating a sync time estimation based on communications with a set of audience devices, and detecting occurrence of an update to the shared screen view of the presenter device. The technique further involves outputting, after the sync time estimation has elapsed since the detected occurrence of the update, the sync notification on the presenter device to indicate when the shared screen view of the presenter device has been delivered to the audience. Such a technique is well suited for a variety of online collaboration systems such as online conference systems, online webinar systems, online meeting systems, and so on.

Abstract: The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include operatively connecting one or more lane modules of an integrated circuit (IC) to form one or more links. The method may further include associating a FIFO reset generator with each of the one or more lane modules and receiving a signal from the FIFO reset generator at a synchronization FIFO. The method may also include aligning, at the synchronization FIFO, one or more enqueue pointers and dequeue pointers.

Abstract: A method for indirectly measuring the clock rate of a media rendering subsystem, in a media rendering device that has a separate hardware clock for rendering the media, by using the rate at which data requests are made of the CPU in the media rendering device and using the CPU clock to provide additional accuracy in measuring the clock rate.

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract: A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The storage controller is configured to receive a read request targeted to the data storage medium, and identify at least a first storage device of the plurality of storage devices which contains data targeted by the read request. In response to either detecting or predicting the first storage device will exhibit variable performance, the controller is configured to generate a reconstruct read request configured to obtain the data from one or more devices of the plurality of storage devices other than the first storage device.

Abstract: A processor according to embodiments comprises an on-board sample rate converter for converting a source audio signal that is sampled at a first sampling rate to an output audio signal that is sampled at a second sampling rate. The sample rate converter utilizes a master clock signal in converting the audio signal. The sample rate converter selects the master clock signal from available reference clock signals, such as an on-chip system clock or a bus interface clock, and scales the frequency of the selected clock signal to generate the master clock signal with the frequency of the second sampling rate.

Abstract: An electronic device assembly includes a main device, and a plurality of peripheral devices. The main device includes a first connector. Each of the plurality of peripheral devices includes two second connectors. Each first connector and second connector includes various types of interfaces, and the plurality of peripheral devices is coupled to the main device via the various types of interfaces; each peripheral device is coupled to another peripheral device via the second connector, to connect the plurality of peripheral devices one by one in series.

Abstract: A user-guided configuration routine for use with a remote catheter guidance system configured to calibrate of one or more medical devices of the remote catheter guidance system with minimal user input. The user-guided configuration routine being configured to determine the appropriate configuration steps from diagnostic data received from the remote catheter guidance system or from a user.

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract: A computer system is provided. In one embodiment, the computer system includes a memory, a peripheral device, a central processing unit (CPU), and a peripheral device controller. The CPU stores information about the data transmission in a descriptor in the memory when data transmission between the CPU and the peripheral device is required. The peripheral device controller reads the descriptor from the memory at an access frequency, records whether the descriptor read from the memory requests for data transmission as a recording result, and adjusts the access frequency according to the recording result.

Abstract: A method for indirectly measuring the clock rate of a media rendering subsystem, in a media rendering device that has a separate hardware clock for rendering the media, by using the rate at which data requests are made of the CPU in the media rendering device and using the CPU clock to provide additional accuracy in measuring the clock rate.

Abstract: A method for checking the operation of a PSI5 reception unit in a motor vehicle controller is presented, wherein the PSI5 reception unit receives signals from a connected PSI5-compliant PSI5 transmission unit, wherein a check signal transmission unit is provided and this check signal transmission unit sends a prescribed check signal to the PSI5 reception unit at prescribed check times at which no signal can be expected from the PSI5 transmission unit, in particular—together with the sending of one or more synchronization pulses to the transmission unit—the check signal transmission unit sends the check signal in this defined period.

Abstract: Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal.

Abstract: Techniques and mechanisms for providing access to a function with an input/output (I/O) device. In an embodiment, a main memory of a computer system including the I/O device stores a function-context data structure associating a function with a context for an access to the function. The I/O device stores a configuration for the I/O device to provide the function. In another embodiment, the software process exchanges information with the function-context data structure for the access to the function. The I/O device performs a synchronization of the function-context data structure and the configuration data structure with respect to one another, wherein the function-context data structure operates as a register level interface which interfaces the I/O device and the software process with one another.

Abstract: A device is described for establishing communication between a first device and a second device. In one implementation, a first internal interface of the first device couples to a first external interface of the second device while a second internal interface of the first device couples to a second external interface of the second device. A first unidirectional data channel may be opened for incoming data using the first internal interface. A second unidirectional data channel may be opened for outgoing data using the second internal interface. The pair of unidirectional data channels is established, allowing data transfer between the devices. These channels allow for asynchronous-like transmission of data, in that transmission and corresponding receipt of data may take place at irregular intervals.

Abstract: A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus. At least two buffers are configured to store data. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, with the counting value of the SOF counter being compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves or exceeds the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.

Abstract: A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony.

Abstract: A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: In a method for synchronizing a control unit and at least one peripheral unit having actuators and/or sensors, the control unit and the peripheral unit exchange data with each other via a serial interface. The control unit transmits data to the at least one peripheral unit which is processed in the peripheral unit for the operation of the actuators and/or sensors, and at least one synchronization character is transmitted from the control unit to the peripheral unit for the synchronization. In this context, the synchronization character is appended by the control unit to a first data sequence of a data stream to be transmitted from the control unit to the peripheral unit, and the transmission of a second data sequence to be transmitted after the first data sequence is delayed in time on the part of the control unit, so that the second data sequence is transmitted by the control unit to the peripheral unit following the synchronization character.

Abstract: A system for synchronising the operation of a measurement instrument having a microcontroller, a local oscillator and function circuitry to an external timebase is provided. The system includes a USB Host Controller; an interrupt generator adapted to respond to ITPs by generating respective interrupts and passing the interrupts to the microcontroller; and a timer for measuring an interval between receptions of the ITPs in a time domain of the local oscillator.

Abstract: A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.

Abstract: The description generally relates to a system designed to synchronize the rendering of a media file between a master device and a sister device. The system is designed so that a media file is simultaneously rendered on a master device and a sister device beginning from identical temporal starting points.

Abstract: A method of controlling a plurality of external devices is performed on a computer which is set up with a plurality of remote control processes corresponding to the plurality of the external devices, and a management process for managing the remote control processes while communicating with the remote control processes. The management process is called to display icons corresponding to the remote control processes in a display field provided by the management process. Further, the management process acts when a specified operation is applied to one of the icons on the display field for sending a screen open instruction to one of the remote control processes corresponding to the icon to which the specified operation is applied. The remote control process which receives the screen open instruction is activated to display a control screen for use in remotely controlling the corresponding external device.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: A method of controlling a port in an apparatus includes receiving an instruction for execution by a processor. The method further includes executing the instruction, by writing a value to a storage location corresponding to the port, and by initializing a count operation. The method further includes proceeding with the count operation until a final count value is reached, and providing to the port the value written to the storage location.

Abstract: An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.

Abstract: According to one embodiment, an electronic device including, a display, an audio output module, a transmission module, a first detection module, a second detection module, a third detection module, and a controller configured to control at least one of the timing of the transmission of the audio signal by the transmission module and the timing of the output of the first reproduction output by the audio output module in accordance with the time difference detected by the third detection module, and to switch whether or not to control the timing in accordance with the positional relationship between the electronic device and the partner device.

Abstract: A synchronization method is provided for a peripheral apparatus. The peripheral apparatus comprises a first peripheral device and a second peripheral device, wherein the first peripheral device is coupled to a host and the first peripheral device runs in a first operation mode. The synchronization method comprises the following steps: when a second peripheral device is coupled to the host, the second peripheral device obtains a synchronization signal from the host; and the second peripheral device runs in a second operation mode based on the synchronization signal, wherein the second operation mode is same as the first operation mode.

Abstract: Devices and methods for generating timing signals at a rate that matches a rate of remotely generated timing signals are provided. In some embodiments, a host generates timing signals in accordance with a USB specification, such as keep-alives, start-of-frame packets, or ITPs. An upstream facing port transmits the timing signals over a network to a downstream facing port. The downstream facing port generates and transmits timing signals to a USB device at a predetermined rate, and alters the predetermined rate based on an analysis of the rate at which timing signals are received from the upstream facing port.

Abstract: An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link from the controller to each module. Each communication link includes a data out line, a data in line and a clock line, where each clock line is derived from one clock source.

Abstract: A method for communicating media between a host and a display system. In one embodiment the method comprises acquiring, by the host and via a wireless connection between the host and the display system, display information of the display system; generating, by the host, an image sequence at a resolution and a frame rate, the resolution and the frame rate determined from the display information; communicating, from the host to the display system and via the wireless connection, an encoding of the image sequence; and displaying, by the display system, a decoding of the encoding.

Abstract: Techniques and mechanisms for providing access to a function with an input/output (I/O) device. In an embodiment, a main memory of a computer system including the I/O device stores a function-context data structure associating a function with a context for an access to the function. The I/O device stores a configuration for the I/O device to provide the function. In another embodiment, the software process exchanges information with the function-context data structure for the access to the function. The I/O device performs a synchronization of the function-context data structure and the configuration data structure with respect to one another, wherein the function-context data structure operates as a register level interface which interfaces the I/O device and the software process with one another.

Abstract: Synchronous interfaces on a first device are configured such that a first synchronous interface is set to a slave mode while a second synchronous interface is set to a master mode. A second device with two synchronous interfaces may then be coupled to the first device with the corresponding synchronous interfaces in master mode and slave mode, respectively. A pair of unidirectional synchronous data channels is established, allowing data transfer between the devices. These channels allow for asynchronous-like transmission of data, in that transmission and corresponding receipt of data may take place at irregular intervals.

Abstract: A system and method is provided for rate limiting network traffic flow of an untrusted application. A master module in a server environment manages network traffic flow restrictions. A slave module executes client applications in the server environment. A services module in the server environment executes a trusted application to validate the client application to the master module. A traffic restriction module on the master module sets network traffic restrictions when validation has not been received for the client application on the slave blade, and receives client application validations from the trusted application to unrestrict network traffic flow for the client application on the slave blade.

Abstract: A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of inputs electrically coupled to outputs of a corresponding plurality of delay elements in the data pipeline. The latency selection circuit is configured to pass a data pipeline signal from an output of a selected one of the plurality of delay elements in response to a latency control signal. A synchronization circuit is provided, which is electrically coupled to an output of the latency selection circuit. This synchronization circuit, which includes first and second unequal timing paths therein, is responsive to a clock that synchronizes capture of the data pipeline signal selected by the latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured data pipeline signal as active.

Abstract: A signal generating apparatus, applicable in a universal serial bus (USB) device, includes: a first determining circuit for receiving a data signal to determine if the data signal is generated by the universal serial bus device, and generating a first determined result; a second determining circuit coupled to the first determining circuit for receiving the data signal and the first determined result to determine a transmitting mode corresponding to the data signal according to the first determined result, and generating a second determined result; and a frequency generating circuit coupled to the second determining circuit for generating a first clock signal utilized for synchronizing the data signal according to the second determined result.

Abstract: According to one embodiment, a transmitter including an AV transmission unit including a first transmission unit which transmits video/audio data according to a method 1, and a second transmission unit which transmits video/audio data according to a method 2, with a clock signal inserted in a data signal, and a communication unit which performs the information communication with the receiver by a predetermined standard signal, a communication channel switch unit which transfers a video clock signal to a clock terminal of an HDMI if the video/audio data is transmitted by the first transmission unit, or transfers a first predetermined standard signal output from the communication unit if the video/audio data is transmitted by the second transmission unit, while the communication channel switch unit transfers a second predetermined standard signal received by an HPD/RSV terminal of the HDMI even in transmission by any of the first and second transmission units.

Abstract: A method for providing a content entity from a storage disc is described. The storage disc comprises at least one further content entity. Each content entity comprises a main menu and at least one submenu accessible via the main menu. The storage disc further comprises an entity selection menu. The entity selection menu comprises a link to the main menu of the content entity to be provided. The method comprises providing the entity selection menu for reproduction, receiving a selection of the content entity to be provided, detecting that the storage disc comprises a plurality of content entities, mapping a pre-defined start address to a different start address and providing the selected content entity for reproduction based on the different start address. The pre-defined start address is mapped to a different start address of the storage disc associated with the main menu of the selected content entity to be provided.

Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.