Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Abstract: A computer having capabilities for hierarchical storage of data, said computer including an interpreter that maps logical user read and write requests to physical block level read and write requests, and a hierarchical performance driver having a disk driver interface for receiving the block level read and write requests from the interpreter, the hierarchical performance driver issuing instructions to read and write data from plural data storage devices in response to block level read and write requests, plural data storage devices having different data access speeds, the hierarchical performance driver monitoring the rates of access of blocks of data stored on the data storage devices and transferring blocks of data accessed infrequently from a faster data storage device to a slower data storage device.

Abstract: A language processing unit comprising a syntax analyzing portion to input and analyze a source program, a code pattern registering portion, a code generating portion to generate operation codes to an analysis results by the syntax analyzing portion according to the selection results by a code size measuring portion and a code pattern selecting portion (15), and a code pattern selecting portion (15) to appropriately replace the generating codes with priority on execution time with generating codes with priority on making the size small, and an object module file output portion to output generated operation codes as an object module file.

Abstract: A data transfer system has a PC as a host computer, a terminal unit such as a printer and a parallel interface cable through which data is transferred between the PC and the terminal unit. The PC transfers a strobe signal as a rate detection signal which contains points of change to the terminal unit. The terminal unit receives the strobe signal and calculates the data processing rate of the PC on the basis of the points of change of the strobe signal. The PC adjusts the data transfer rate of the PC on the basis of a result of comparison of the data processing rate of the PC calculated by the terminal unit and a processing rate of the terminal unit.

Abstract: An improved method and apparatus for providing multimedia communication between and client device and a server. The improved method and apparatus allows for communication of information, such as audio or video information from an application program to be communicated through a standard application program interface to a device driver which, in turn communicates the information over a network to a server.

Abstract: A rotating disk data storage device havIng a buffer in the form of a semiconductor memory for temporarily storing data supplied from a host computer prior to transfer to a disk drive. For most efficient data transfer from buffer to disk, the storage device has a microprocessor controller which is preprogrammed to compute the average, or weighted average, of the time intervals at which at least three, preferably eight, latest consecutive data blocks are delivered from the host, the average being updated with the reception of each new data block from the host. The data is transferred from buffer to disk at time intervals each determined by multiplying the latest average time interval by a preselected coefficient. Data transfer from buffer to disk also occurs when the time interval between any two consecutive data blocks exceeds a predetermined limit, or when the amount of data stored in the temporary memory exceeds a predetermined limit.

Abstract: The invention comprises a configurable input/output buffer for an FPGA that can be configured to comply with any of two or more different I/O standards. Factors such as output drive strength, receiver type, output driver type, and output signal slew rate are configurably controlled. In some embodiments, the input power supply and the output power supply can be different from the core voltage supply. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad are configurably connected to the input reference voltage line. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage or a single output voltage supply is applied to each Input/Output Block (IOB), with IOBs grouped into sets.

Abstract: A computer is provided having a bus interface unit between a CPU bus and a memory bus. The bus interface unit includes a memory controller and a read/write queue manager. The memory controller dispatches, or removes read requests or write requests from respective read or write requests queues depending on various modes of operation. Typically, the read requests are dispatched or removed either singularly or as a programmed series of read requests prioritized over write requests unless the write request queue is almost full. If the write request queue is almost full, then write request are removed either singularly or in a series before servicing the read request queue. The number of read or write request being removed from their respective queues can be programmed within a configuration register operably coupled to a controller arranged between the read and write request queues. The memory controller determines how many requests will be serviced within possibly a lengthy series of requests.

Abstract: An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.

Abstract: A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while providing function and timing parameters to satisfy requirements of an asynchronous bus and more than one type of device which reside on the bus.

Abstract: A computer system includes a central processing unit directly coupled to a peripheral device. The peripheral device transmits and receives data from and to the central processing unit. An MMx unit within the CPU includes data buffers for storing data. Data from the multimedia device is stored in a receive buffer and subsequently retrieved by the MMx unit for processing. Data from the MMx unit is stored in a transmit buffer and subsequently retrieved by the multimedia device. The receive buffer may include a concatenator for combining data words received from the multimedia device into a multimedia data word. The transmit buffer may include a de-concatenator for dividing a multimedia data word into a plurality of data words for transmission to the multimedia device. The data buffers provide signals indicating the relative level of fullness or emptiness of the buffers. The signals are used to adjust the rate at which data is processed.