Abstract: A method using a Reflective Timing Signal to automatically adjust the timing parameters of an asynchronous bus to compensate for its physical extension.

Abstract: Use of a Thin protocol in an AV/C command is made possible. A TO (Thin Output) plug that conforms to the Thin protocol is provided in a disk camera which transmits data. In a similar manner, a TI (Thin Input) plug that conforms to the Thin protocol is provided in a printer which receives data.

Abstract: In accordance with the present invention, a method and apparatus are provided for efficiently transmitting data between stages of a decompression pipeline by implementing a control store register for minimizing the amount of data that is transferred among decompression units. The control store register is a register having memory locations that are associated with decompressed coefficients. As the coefficients are decompressed, a determination is made as to whether they contain zero or non-zero values. The result of that determination is stored in the control store register such that the processor performing the inverse quantization and inverse discrete cosine operations only retrieves non-zero coefficients. Therefore, data transmission is performed in an efficient manner.

Abstract: A frame-rate clock of a plurality of data buses is synchronized to a master clock signal. The master clock signal may be derived from the existing clock signals within the computer system or from data received from an external source. The master clock signal may also be used by an operating system scheduler to schedule tasks that generate or consume blocks of isochronous data. The drift of a device clock signal relative to a master clock signal is measured and used to synchronize the device clock signal. For example, a mechanism may monitor the level of data in a data buffer. The level of data in the data buffer is a measure of the drift between the clock generating the data and the clock consuming the data. Based upon the level of data in the buffer, synchronization information is provided to synchronize the rates of the clock signals that generate and consume the data.

Abstract: A handheld computer which contains an LCD display having a digitizing surface to allow pen input. Internal storage takes several forms, such as a large flash ROM area, battery-backed up RAM and an optional hard disk drive. Several alternative communication paths are available, such as the previously mentioned modem, a parallel printer port, a conventional serial port, a cradle assembly connected to the host computer, and various wireless short distance techniques such as radio frequency or infrared transmission. The computer can readily communicate with other sources, particularly to a host desktop computer, to allow automated synchronization of information between the host and the handheld system. Preferably the remote synchronization is performed at several user selectable levels. When the handheld computer is in a cradle and actively connected to the host computer, automatic capture of updated data in the host computer is performed.

Abstract: An apparatus is described for controlling data transfer operations between a main memory and other devices in a computer system. A memory controller receives data transfer request signals and associated latency identification values, each corresponding with a maximum time interval in which to service the respective data transfer requests. The latency identification values are periodically modified and compared to indicate the current highest priority request. In the event that service of a particular requested data transfer operation must be provided imminently, priority override circuitry is provided. In this way, those devices having particular latency requirements can be provided with timely access to the main memory, and need not have separately dedicated memory or buffers.

Abstract: A data transfer device for unidirectional serial data transfer from a transmitting device to a receiving device, in particular from a microcontroller to an output stage IC of a motor vehicle control unit. The data transfer device includes a P/S converter provided in the transmitting device for converting a parallel data stream made available in the transmitting device into a serial data stream with transfer frames of a predefined format and for transmitting the serial data stream to the receiving device over a data transfer channel. The data transfer device also includes an S/P converter provided in the receiving device for converting the transmitted serial data stream back into a parallel data stream, and a clock signal generating device for generating a clock signal and for sending the clock signal to the P/S converter and the S/P converter to perform the conversion operations continuously and in-phase.

Abstract: A method of handling read transactions to improve latency and promote streaming across a bridge. When an initiator returns to retrieve the read data associated with a previously enqueued transaction, the bridge will insert one or more wait states if the enqueued transaction is being mastered and no data has been received in a buffer of the bridge from the target, or if some but not a sufficient amount of data has been received from the target. The bridge continues to hold the initiator until the buffer contains sufficient read data whereupon the bridge will deliver the read data from the buffer to the initiator.

Abstract: Circuitry is described for transferring information from a first timing environment to a second timing environment. The circuitry comprises a dual port RAM having a first port which is responsive to a first timing signal and a second port which is responsive to a second timing signal, a first control circuit which is responsive to the first timing signal, for controlling storage of data in the dual port RAM through the first port and for generating a control signal indicating that data is stored in the dual port RAM. The circuitry also comprises a synchronizer for synchronizing the control signal to the second timing signal, and a second control circuit, which is responsive to the second timing signal and the synchronized control signal and is for controlling retrieval of stored data through the second port of the dual port RAM.

Abstract: A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively couples the controller and the multiple loads. In another embodiment, the invention transfers data between a memory controller and a RAM by coupling the controller and the RAM using a data bus and multiple clock lines. The invention transfers a read/write command from the controller to the RAM and then transfers data associated with the read/write command, clocking the data using one of the clock lines.

Abstract: Permission based flow control is implemented in a computer network having at least a downstream, intermediate and upstream network device by receiving credits at the intermediate network device from the downstream network device and granting credits from the intermediate network device to the upstream network device based at least in part upon the credits received at the intermediate network device from the downstream network device. Credit chaining as described above is employed to permit the granting of the right to transmit downstream to be predicated upon buffer availability downstream of the next downstream network device. Via the use of credit chaining, high utilization of network resources is achieved with minimal loss of data traffic.

Abstract: A method and apparatus for communicating signals between a source synchronous component and a non-source synchronous component of a system is described. The present invention provides a strobe signal from the source synchronous component that is delayed and used to latch data received from a non-source synchronous component. The amount of delay provided is determined based on the timing of data request cycles to the non-source synchronous component. Thus, the present invention allows data to be received by a source synchronous component from a component that does not generate a strobe signal used for latching received data that would be generated by a source synchronous component.

Abstract: A technique to provide device status information includes obtaining device status information, determining when a bus retry operation is being executed, and routing the device status information to a bus if a bus retry operation is being executed.

Abstract: The drift between a write pointer and a read pointer processing packets of data through a FIFO buffer is compensated for by adjusting the start of the read pointer relative to the write pointer. The FIFO buffer is sized to include a number of storage cells equal to the product of the maximum frequency offset between the write clock and read clock and the maximum number of data units in a packet. Initially the start of the read pointer is delayed, relative to the write pointer, by a portion of the number of storage cells in the FIFO. During the processing of a data packet it is determined whether the read pointer is drifting toward or away from the write pointer. If the read pointer is drifting away from the write pointer, for subsequent data packets, the read pointer is started almost immediately after the write pointer writes to the first storage cell in the FIFO.

Abstract: A technique for performing multiple simultaneous asynchronous input/output operations in a computer operating system. An input/output completion port object is created and associated with a file descriptor. When I/O services are requested on the file descriptor, completion is indicated by a message queued to the I/O completion port. A process requesting I/O services is not notified of completion of the I/O services, but instead checks the I/O completion port's queue to determine the status of its I/O requests. The I/O completion port manages multiple threads and their concurrency.

Abstract: An apparatus is employed for providing for efficient communication between high level and low level processing engines in a disk formatter for formatting a disk, the high-level engine outputting at least one instruction to control disk operations to the low-level engine which processes the instruction. The apparatus includes an instruction queue within the low-level engine. The instruction queue stores the instruction received by the low level processing engine from the high level processing engine, which outputs the instruction to the memory in accordance with a first clock signal generated by the high-level engine. The instruction queue outputs the instruction in accordance with a second clock signal of the low level processing engine which corresponds to a predetermined disk transfer rate. In accordance with another embodiment of the present invention, a method is also employed for providing for efficient communication between high and low level processing engines in a disk formatter for formatting a disk.

Abstract: A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.

Abstract: According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed. A data queue coupled to a command queue is arranged to store a time indicating when the data transfer will appear on the data bus between the controller for an already issued request to the target device as well as arranged to store the burst bit and the read/write bit (r/w). The system also includes a collision detector coupled to the data queue and the command queue arranged to detect the possible collisions on the data bus between the issued command that is stored in the command queue and already issued commands that are stored in the data queue. A queues and link controller is coupled to the collision detector and the data queue and the command queue and is arranged to store and reorder commands to be issued wherein the controller calculates the new issue time of commands as well as a time when the data appears on the data bus.

Abstract: A system for storing data. The system includes a host for processing the data. The system includes a buffer mechanism for storing data and producing interrupt signals to the host for informing the host there is data in the buffer mechanism for the host to process. The buffer mechanism adapting the production of interrupts based on the speed the host can process data. The host is in contact with the buffer mechanism. A method for serving data. The method includes the steps of storing data in a buffer mechanism. Then there is the step of sending an initial interrupt signal to a host from the buffer mechanism informing the host there is data in the buffer mechanism for the host to process. Next there is the step of transferring data in the buffer mechanism to the host. Then there is the step of processing data from the buffer mechanism with the host. Next there is the step of adapting when a subsequent interrupt signal is sent to the host based on the speed the host can process data.

Abstract: A method and apparatus for reliable interrupt reception over a buffered bus utilizes a non-delayed non-posted write transaction to write data over the bus from a peripheral device to host memory. Because there is no buffering delay in a non-delayed non-posted write transaction, at the completion of the write cycle the peripheral knows that the write transaction is complete and then sends an interrupt request to the host processor requesting the host processor to service the interrupt and process the contents of the host memory.

Abstract: An integrated circuit memory device includes a DQM input buffer controller that enables the DQM buffer to process the DQM mask signal during a row active period of a read operation and a write operation of an integrated circuit memory device, and during a latency period of the read operation and the write operation, and that disables the DQM buffer otherwise during the read operation and the write operation. Thus, the DQM buffer is enabled to process the DQM mask signal during those portions of the read and write operations in which the external DQM mask signal is received and the DQM buffer is otherwise disabled during the read and write operations. The controller can also disable the DQM buffer during a refresh operation of the memory device and a power-down operation of the memory device. Accordingly, reduced current consumption in the DQM buffers may be obtained by only enabling the DQM input buffers when a DQM mask signal is expected during the read and write operations of the memory device.

Abstract: A system is disclosed for improving the efficiency of data transactions by permitting the length of burst transactions to be modified based upon system performance. A bus interface unit monitors the response times of memory devices, and, if WAIT periods are required before the memory device responds, the bus interface unit increases the length of the burst. Preferably, the bus interface unit includes a table of historical response times of various memory ranges, and determines an optimal burst length for each memory range. When a data transaction is made to a particular memory location, the BIU accesses the table and asserts a BURST signal for a sufficient period of time to accomplish the optimal burst length. After the optimal burst length has been reached in the existing memory transaction, the BURST signal is deasserted to end the burst cycle.

Abstract: It is an object to provide a printer apparatus, a control method of such an apparatus, and a printer system, in which a proper control can be performed in consideration of a change in network load. When a load of a transmission path is measured and a data reception from a host is interrupted, a waiting time of the data is extended in accordance with the measured load, thereby realizing the object. The set operating conditions are transmitted to the host and are also automatically set into the other printers connected to the network to which the printer is connected via the host, thereby realizing the object.

Abstract: Disclosed is a device for the conversion of a series signal received in the form of a low-amplitude, high-frequency differential signal into n parallel signals. The device uses a scheme derived from that of a static memory cell as a sample-and-hold unit and amplifier. The device continues to perform well when the differential signal comprises noise in common mode.

Abstract: A command execution monitoring system includes a first unit which retains control parameters of an operation control command sent by one of host computers, the control parameters including an operation completion time. A second unit sequentially receives command entries sent for input/output devices by the host computers and retains the command entries in a table, each entry including a relative elapsed time measured from a time the entry is retained in the table. A third unit sets a time-out period of one of the host computers at the operation completion time retained by the first unit, so that execution of each of the entries in the table of the second unit is monitored based on a comparison between each of the relative elapsed times of the entries and the operation completion time.

Abstract: Response time is improved by a method and apparatus for pre-fetching application data over a network. A request for application data, such as Internet data, is received. The request is transmitted to a transparent network proxy, which issues requests over a communications network to fetch the requested data. The requested application data are received by the proxy and forwarded to a client layered service provider, which supplies the data to the application. If additional application data is received by the proxy, that data is also forwarded to the client layered service provider, where it is stored as pre-fetch data. If additional application data is requested by the application, the additional data can be supplied from the stored pre-fetch data, if available.

Abstract: A technique for controlling an interactive presentation is disclosed. In one embodiment, a processing device receives at least one of a plurality of commands, wherein each of the plurality of commands corresponds to a respective operation the performance of which is directly associated with controlling a particular aspect of the interactive presentation. The processing device processes each of the received commands such that each corresponding operation is performed to control a particular aspect of the interactive presentation.

Abstract: A network interface device includes a random access transmit buffer and a random access receive buffer for transmission and reception of transmission and receive data frames between a host computer bus and a packet switched network. The network interface device includes a memory management unit having read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memories between the read and write controllers. The synchronization circuit asynchronously monitors the amount of data stored in the random access transmit and receive buffer by asynchronously comparing write pointer and read pointer values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal.

Abstract: A clock signal loading device for a processor of a controller connected to a network and a clock signal loading method are provided. The device includes a first oscillator for generating a clock signal that can be loaded to the processor, a controllable clock signal changer for changing the clock signal generated by the first oscillator, and a control device connected to the network for generating a control signal for controlling the clock signal changer as a function of the communication signals transmitted over the network. This device and method allows the frequency of the clock signal needed by the processor to be tuned in a simple and flexible manner.

Abstract: The invention relates to a multi-output monolithic device, and particularly to a multi-output monolithic integrated circuit device without generating a simultaneous switch output (SSO) in communication or in a network, in which the plurality of output port will not switch from "0" to "1" or from "1" to "0" simultaneously to prevent insufficient power supply caused by a simultaneous switch, resulting in noise generation and errorous operations. A multi-bit shift register in used in the invention to make each output port have a different and to reduce the probability of the same output value on each output port, thereby reducing the influence of SSO. Then, a slightly different delay is made of each output port during output, so as to eliminate SSO.

Abstract: A method and computer program product are provided for paging control using a reference structure in a computer system. The reference structure is scanned to identify a next selected entry for an IO range building routine. The next selected entry is compared with a set hardlimit value. Responsive to the next selected entry being greater than the hardlimit value, the IO range building routine is exited. A shortlimit value is identified. The next selected entry is compared with the identified shortlimit value. Responsive to the next selected entry being greater than the identified shortlimit value, the IO range building routine is exited. A first array is used for storing entry IDs for selected entries found from scanning the reference structure and a second array is used for tracking blocks of storage used for the selected entries.

Abstract: An interface to transfer data between a memory controller hub and an input/output (I/O) hub of a chipset within a computer system. One embodiment of the interface includes a bi-directional data signal path and a pair of source synchronous strobe signals. The data signal path transmits data in packets via split transactions. In addition, the packets include a request packet and a completion packet, if necessary. Furthermore, in one embodiment, the request packets include a transaction descriptor.

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

Abstract: Semiconductor wafer fabrication equipment comprising a selecting device for selecting semiconductor wafers destined to a processor on the basis of a remaining process time applicable to that processor in the equipment, a transporting device for transporting the selected semiconductor wafers to the processor, another selecting device for selecting a processor or a storage device constituting a transport destination to which to transport processed semiconductor wafers, and another transporting device for transporting the semiconductor wafers to the destination processor or storage device in accordance with a transport control changeover code read from the processors and storage devices of the equipment.

Abstract: Enhanced is a data processing efficiency of a whole semiconductor integrated circuit. A multiplexer is provided on a main parallel data bus for transferring data between an internal device such as a CPU, a DRAM or the like and an external device. When the CPU cannot accept data from the external device, it sends a busy signal to an interface circuit. The interface circuit receives the busy signal and controls the multiplexer in such a manner that the data to be transmitted to the CPU are transferred to the DRAM. Thus, a data transfer rate of the semiconductor integrated circuit is enhanced.

Abstract: A computer system including synchronous dynamic random access memory (SDRAM) circuits that are capable of operating at different frequencies. A memory controller generates multiple clock signals with appropriate frequencies for use by the SDRAM memory devices. Asynchronous data queues are used to provide data transfers between the SDRAM memory and the processor or other bus master devices residing on a peripheral bus. Upon initialization, the computer system determines the type of SDRAM devices present and provides status information to the memory controller which, in response, generates appropriate clock signals to the SDRAM memory circuits.

Abstract: A method of and an apparatus for duplicating direct access storage devices (DASDs) such as hard disk drives (HDDs). The apparatus includes a portable HDD duplicator which can be connected to an existing personal computer (PC), and perform fast data duplication directly from a source HDD to a multiplicity of target HDDs simultaneously. The method includes the steps of providing direct data paths between the source HDD and the target HDDs and performing high speed data duplication and comparison functions by reading the source HDD and writing to the target HDDs at the same time.

Abstract: An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously been loaded into the storage circuit and that will not be output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.

Abstract: A method for downloading functions between a personal computer including one or more processors, a memory, an input/output unit and a communication unit, and a memory or input/output PCMCIA card having a buffer memory, a PCMCIA Interface is provided between the computer and the cared. The method loads into the buffer memory, through fast access to the memory, a function which is directly sent to the processor of the PCMCIA card for execution.

Abstract: A method and system for reducing system bus load due to bandwidth reclamation on a Universal Serial Bus. A device residing on a USB may not be able to accept or provide data at the maximum rate that such data can move over the USB. In such case, for bulk transfers and control transfers, the transactions are likely to be continually retried because reliable data delivery is guaranteed. This causes a drain on the system bus through put for transactions which cannot complete. By throttling the rate at which transfers to such devices occur, a significant reduction in the load on the system through put bus can be achieved.

Abstract: A simple and efficient serial interface transmission structure according to the invention comprises only 8 modes by which all required operations provided by the conventional serial interface are readily accomplished. Furthermore, a serial interface transmission structure according to the invention has the advantages of requiring a minimal amount of logic devices and input/output pins, being capable of automatically returning to an IDLE mode, being able to easily read/write data from/to devices which are connected thereto, and being able to continuously poll the status messages of the devices.

Abstract: An apparatus for synchronizing data retrieval is described. The apparatus comprises a storage media storing data, a storage control device coupled to the storage media for retrieving the data from the storage media, memory coupled to the storage control device for storing the data; and a scheduling unit coupled to the memory for scheduling retrieval of the data from the storage media before a specified time. A storage media for storing computer instructions is also described.

Abstract: A clock crossing FIFO capable of functioning regardless of relative clock frequencies on the write and read sides. Toggle signals are utilized to cross the clock boundaries. The number of write counts which have been accrued but not acknowledged by the read side are tracked, and this number is stored as of the issuance of a write toggle. Upon toggle receipt on the read side, this number is latched as a measure of the number of data units which can be read from the FIFO. At the same time, the toggle is returned to the write side for decrementing the number of write counts outstanding by the number conveyed to the read side. Similar circuitry is employed for conveying to the write side circuitry the number of data units which have been read by the read side circuitry. The presently disclosed FIFO and associated circuitry operates independent of relative clock speeds, and the particular size of the FIFO is scalable.

Abstract: An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: A reflex I/O card for an industrial controller receives enabling inputs from the executed control program and triggering inputs from an industrial process to provide outputs at a fixed delay in time or portion of a machine cycle after the inputs through dedicated hardware thus avoiding transmission delays and processing delays associated with the communication of information to a central processor and the execution of the control program.

Abstract: A method and apparatus for fencing the execution of commands. A fence command and an executable command are received in succession. The executable command is enqueued in a first queue together with an indication that the executable command succeeded the fence command. A synchronization value is enqueued in a second queue. The executable command is then delayed from being dequeued from the first queue until the synchronization value is advanced to the head of the second queue.

Abstract: A data outputting system realizes tacit viewing by representing pieces of peripheral data related to focused data to which a user pays attention at an appropriate timing. In the system, the data to which the user pays attention is selected by a data designating element as focused data from the plural pieces of data held by a database, and a focused data representing element makes the outputting element output the focused data. A peripheral data determining element selects the pieces of peripheral data from the plural pieces of data held by the database based on the degree of relation to the focused data, and a timing determining element determines the timing of representation of the peripheral data in accordance with the attributes of the focused data, the history of representation of the focused data in the past, the attributes of the user, and so on. Then a peripheral data representing element makes the outputting element output the pieces of peripheral data at the determined timing.

Abstract: A solution to the problem of undesired serialization of bus controlled instrument measurement delays for multiple instances of programmatically controlled measurement processes is to configure the bus operations and the control programs to allow the issuance of a command within the context of a first collection of such instruments, without having to wait for the corresponding data before issuing commands within the context of a second collection. This is done by instructing the equipment in the collection to signal that they have data instead of the more customary immediately issued "@ address talk", which is then followed by the delay needed by the equipment to make the measurement. Instead, the "have data" signals are associated with the devices that originated them and then the bus instructions that request the data are issued. In conjunction with this, the usual bus I/O commands in the controlling programs may be replaced with calls to a library that operates in just this fashion.

Abstract: An asynchronous latch including a finite state machine (301) and a level-sensitive latch (304) in a feedback path of the finite state machine. The input to the level-sensitive latch (304) is a signal generated by decoding the state of the finite state machine (301). The level-sensitive latch output is fed back to the finite state machine inputs to control next-state transitions. An asynchronous input line couples an asynchronous signal to the level-sensitive latch so that the asynchronous signal is used as a latching signal.