Abstract: A method and apparatus for determining a computer system usage profile, and transmitting the computer system usage profile to a server which targets content to the computer system in response to the usage profile is described. A basic input output system (BIOS) module and/or an operating system module obtain computer system usage profile information by tracking events such as the frequency of re-boots, the time required to boot-up and shut-down the operating system on the computer system, the amount of time the computer system is “used”, and the frequency and amount of time the computer system is connected to the Internet. This data is collected and communicated to a profile server. The profile server targets content such as messages with graphics or informational material, etc. to the computer system based upon the computer system usage profile. In one embodiment, the content is displayed during boot-up and shut-down of the operating system.

Abstract: A first frame deadline is calculated and attached to an I/O request for prioritizing and retrieving video data frames from a shared disk cluster. Disk adapters queue video data frame requests according to the deadline incorporated in the frame requests. Data frames are transmitted to a requesting end user utilizing the attached deadline time to schedule the frames according to a time priority. Alternatively, a “slack” time is computed and utilized to determine when the first frame and subsequent frames of the requested video data may be retrieved from disk and present in the video server's memory in order to avoid a visible delay in sending that frame to the end user.

Abstract: In a network system in which a request of executing a process is sent from the higher level system to the lower level system, a time period of not executing a requested job is assured in the lower level system while assuring an asynchronism between the both systems and a certainty of the requested job. The higher level system transmits a pair of signals (a preparatory signal and an execution signal) to the lower level system in a predetermined interval after it holds a processing request to be sent to the lower system. The higher level system then resumes transmission of the processing request a predetermined time after transmitting the pair of signals.

Abstract: Arrangements directed to arrangements for queuing/tracking of transaction portions to reduce latency are disclosed. A queue/pointer arrangement to queue first execution information portions and second execution information portions for transactions may comprise a first queue and a second queue. The first queue and the second queue may be adapted to store the first execution information portions and the second execution information portions, respectively, may have a first pointer arrangement and a second pointer arrangement, respectively, and may operate independently of one another. The first execution information portions and corresponding second execution information portions with respect to the first queue and the second queue, respectively may comprise, address portions and full-line portions for the transactions.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: A request interface device and method for operating the device and its components are described. The request interface device comprises a bus interface unit (BIU) and a requesting device. The requesting device generates a transfer request for data or command information, along with state information determining the manner in which the requestor will transfer the data or command information associated with the request once the transfer request is granted. The transfer request and the associated state information are sent to the BIU, freeing the requestor to generate new requests wile the first transfer request is waiting to be granted. The transfer request and associated information is stored in a queue within the BIU while the BIU logic gains access to the host bus.

Abstract: According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed. A data queue coupled to a command queue is arranged to store a time indicating when the data transfer will appear on the data bus between the controller for an already issued request to the target device as well as arranged to store the burst bit and the read/write bit (r/w). The system also includes a collision detector coupled to the data queue and the command queue arranged to detect the possible collisions on the data bus between the issued command that is stored in the command queue and already issued commands that are stored in the data queue. A queues and link controller is coupled to the collision detector and the data queue and the command queue and is arranged to store and reorder commands to be issued wherein the controller calculates the new issue time of commands as well as a time when the data appears on the data bus.

Abstract: A method and device for measuring the response time of a circuit are described in which clocking pulses are applied to the circuit at input pads, the input pads being connected to the circuit by circuitry having substantially the same delays. By adjusting the timing of the later clock pulse relative to the earlier clock pulse until a valid output is just achieved, the response time of the circuit can be measured using a register circuit.

Abstract: A system and method for initializing deterministic source-synchronous transfers between devices in a computer system using one or more ratio bits to indicate a ratio between clocks. In an exemplary computer system, one or more processors are each coupled to a bridge. The one or more ratio bits are used to indicate a ratio between the system clock of a first device, such as a processor, and the system clock of a second device, such as the bridge. Each device may also operate at a multiple of its system clock. Once the one or more ratio bits have been stored, the first device can determine when edges of its operating clock correspond to edges of the operating clock of the second device. The use of the one or more ratio bits may advantageously allow devices in the computer system to operate on different system clocks without dedicated signal lines or pins to indicate the frequencies of those different system clocks.

Abstract: Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.

Abstract: A system is provided to transfer parallel incoming data from an interface device with an external timing domain, for reading in an internal timing domain, without the use of external control signals. System constraints are reduced by permitting an infinite delay to occur in the byte clock timing through the interface device. The system tolerates a specified drift of the byte clock after initialization which may be the result of thermal changes in the interface device, for example. If the specified drift is exceeded, the system is able to reinitialize timing to reestablish the specified byte clock drift, and so continue the transfer of data from the interface device. A method of transferring data using an internal timing domain, from an interface device having an external timing domain, is also provided.

Abstract: A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.

Abstract: A memory system and method of using same are provided. In one embodiment of the present invention, a novel memory operation protocol may be used to facilitate the execution of memory operations in the memory system. These memory operations may include atomic read-modify-write operations that may involve arithmetic and/or logical operations of greater complexity than those that may be carried out in the prior art.

Abstract: A bifurcation circuit uses dynamic asP* protocol. to exchange data among three or more FIFOs. Each FIFO contains a plurality of places containing data and a plurality of paths that exchange data between neighboring places. The bifurcator circuit generally comprises a control FIFO, two subordinate FIFOs and a bifurcation path coupled to all three FIFOs. The bifurcator circuit further comprises a chain of data latches coupled to all three FIFOs at the bifurcation path. A data value carried in the control FIFO determines which of the subordinate FIFOs exchanges data with the control FIFO. Each place in the FIFOs contains a set reset flip-flop in which the state of each place is held by a single wire and stabilized by a keeper. A single transistor sets or resets the state of the place. The pulse that changes the state of the control flip-flops also makes the data latches momentarily transparent. The bifurcator circuit is generally capable of a branch or join operations.

Abstract: An input/output controller interacts with a central processing unit of a computer which communicates with peripheral electronic equipment. The link with the central processor unit is produced with an input serial line and at least one output serial line. It receives instructions of a first type from the central processing unit and instructions of at least a second kind which are stored in the memory external to the central processing unit. These are processed using a sequencer device which allocates time slots to the instructions according to their type. This device is especially useful in the field of avionics and flight management systems.

Abstract: A method and apparatus for prioritizing the use of multifunctional printing system's basic processing resources to permit job streaming. The printing system employs a controller with an improved job contention manager (JCM). A plurality of basic resources of the printing system are provided with a queue. One or more job services, at desired times, signals the JCM to carry out a sub-job of a given job. The signal for each of the sub-jobs includes information about the respective sub-job's, job service and its priority. Responsive to the signal from the job service the JCM adds a corresponding basic resource sub-job to the queues of each basic resource which the sub-job will require to perform the sub-job. A first of the sub-jobs is placed in an “Active” state ready for processing, if the first sub-job is at the top of all of the queues, of all the basic resources, required to perform the first sub-job.

Abstract: The preferred embodiment of the invention has a combination of a detection circuit and executable software. The detection circuit is capable of detecting the removal and replacement of a computer system microprocessor and latching an indication that the microprocessor has been removed, even if that removal has taken place while the computer system is without power. Having latched an indication that the microprocessor has been removed and replaced, the detection circuit asserts appropriate signals to start the microprocessor in a safe mode. Once operating in a safe mode, an executable program polls the latched indication, and if the indication is that the CPU has been removed and replaced, the software is further adapted to prompt a computer system user for a new host bus to CPU core speed ratio and modify registors to indicate a new value, if necessary, that are subsequently used to start the CPU at the correct operational speed.

Abstract: An input device for an information terminal includes an operational experience determining device for determining the operational experience of a user in accordance with the speed of inputting data by the user to a data input screen and a display control device for changing the content on the data input screen in accordance with a result of the determination by the operational experience determining device.

Abstract: A bus interface is provided including a first bus transmission medium adapted for being connected to a control signal source which generates a plurality of sequential control signals. During use, the first bus transmission medium serves to communicate the sequential control signals. Associated with the first bus transmission medium is a second bus transmission medium that is in communication with at least one peripheral device. Such device generates an output signal on the second bus transmission medium upon actuation. Tracking circuitry is connected to the device and remains in communication with the first bus transmission medium. By this interconnection, the tracking circuitry is capable of actuating the device upon the receipt of at least one of the sequential control signals that is associated with the device and is distinguishable by a unique sequential order amongst the remaining sequential control signals.

Abstract: The present invention provides a multi-function buffer system for use in a peripheral storage device system, as well as a peripheral storage device system having a multi-function buffer system. The buffer system comprises a multi-purpose memory component which may be adapted for use as scratchpad and/or instruction storage accessible by a controller processor, as well as for buffering information being transferred between the peripheral storage device and a host computer system.

Abstract: A synchronizing device and a synchronizing method whose constitution is simple and whose operation is easy to be stabilized are provided. A subtracter subtracts a value of a read pointer which calculates number of data read-out from a memory device from a value of a write pointer which calculates number of data written in the memory device to obtain subtraction value, thus causing the subtraction value to be given to a judging unit as detection data remaining quantity. The judging unit outputs comparison result signal while comparing detection data remaining quantity with reference value. A number of data increasing/decreasing unit receives data from a decoder for decoding data of the memory device. The number of data increasing/decreasing unit causes remaining quantity of data of the memory device to be prescribed value with data reading-out speed of the memory device controlled in such a way that it controls quantity of data outputted, while replying to comparison result signal from the judging unit.

Abstract: Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue having a plurality of queue positions. A timestamp logic circuit in communication with the memory controller designates scheduled times for each queue position. The memory controller may schedule a packet for a queue position at a scheduled time. The timestamp logic circuit utilizes a plurality of bubble adders to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet.

Abstract: Computer system performance may be significantly enhanced by optimizing data throughput during input/output (I/O) operations. In turn, data throughput, during an I/O operation, may be optimized by adaptively modifying the I/O strategy at runtime, and/or continuously throughout the I/O operation, regardless of the specific hardware configuration associated with the I/O devices involved with the I/O operation, as well as additional factors that might otherwise impact the efficiency of the I/O operation.

Abstract: A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an I/O subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor executing software instructions. The I/O subsystem includes one or more I/O nodes serially coupled via non-coherent communication links. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). One of the processing nodes includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. One of the I/O nodes is coupled to the processing node including the host bridges. The I/O node coupled to the processing node produces and/or provides transactions having destinations or targets within the processing subsystem to the processing node including the host bridge.

Abstract: A storage apparatus has input means for inputting an input/output execution time prediction request from an external system and determining means for predicting the execution time of the input/output request in response to the input/output execution time prediction request. The storage apparatus predicts the execution time of the input/output request and provides a response to the external system in response to the input/output execution time prediction request input from the external system.

Abstract: A system and method of decoupling timing in a high speed bus system. A master/slave translator is coupled between a master device and a slave device. A pseudo slave of the master/slave translator responds to the master in a first timing protocol. A pseudo master of the master/slave translator masters the slave devices under a different timing protocol. The master/slave translator causes the master to believe its communications with the slave device are occurring under the first protocol.

Abstract: A virtual device driver for processing serial communications in a protected operating system. The virtual device driver adds a time-stamp to each character received at Ring-zero level of the operating system architecture. The time-stamp value is compared to a predetermined maximum acceptable time interval to determine if a valid packet was received.

Abstract: Method for maintaining an execution interval for a task requestor to a DMA. A timer is provided with two counters, one (34) to maintain the execution interval and the second (32) to track the execution time of a task in the DMA. Each task has a predetermined execution time allowance. A task acknowledge (TACK) signal enables the tracking. A task request signal (TREQ) is generated during each execution interval until the execution time allowance is completed. The length of the second counter is less than the first counter. In one embodiment, if the first counter expires before the execution time allowance is completed, a task error signal (TERR) is illustrated.

Abstract: According to the present invention, a method for very fast calculation of the earliest command issue time for a new command issued by a memory controller is disclosed. The memory controller includes N page status registers each of which includes four page timers such that each of the page timers store a period of time between a last issued command to the particular page and a predicted next access to the memory, wherein the next access to the same page can be “close”, “open”, “write” or “read”. An incoming new command is received and it is then determined how long a particularly page access has to wait before the issue. An appropriate contents of a command timing lookup table is selected by the new command. A new time value is written into appropriate page timers that has to be inserted between the new command and a possible next access to the same page.

Abstract: Numerous embodiments of a method and apparatus for dynamic coalescing are disclosed.

Abstract: A stream of data words is sent from a memory thru a controller and an external data buffer to an I/O device by a method which includes the steps of: 1) transferring a segment of the stream of data from the memory into the controller while concurrently sending a subsegment of the segment from the controller thru the data buffer to the I/O device via a transmission burst in which the receipt of individual parts of the subsegment are not acknowledged by the I/O device; 2) receiving a signal in the controller from the I/O device at any time during the sending step, to terminate the transmission burst; 3) subsequently receiving a signal in the controller, from the I/O device, to restart the transmission burst beginning with a selectable part of the last subsegment that was sent; 4) removing from the controller, only the portion of the segment which precedes the selectable part of the subsegment; and, 5) repeating the above steps until the stream of data is received in its entirety by the I/O device.

Abstract: A system and signal processing method, in which at least two processors have prioritized, shared access to one or more devices connected along a bus. In preferred embodiments, a fast processor is connected along a first bus, a slow processor and shared device are connected along a second bus, and a communication device is connected between the buses. The communication device is configured to provide the fast processor continuous access to the shared device (in response to grant of an access request by the fast processor) for a limited time that is longer than the time required for a single word transfer, but the slow processor must contend with the fast processor for access to the shared device each time after the slow processor completes a word transfer. Preferably, the communication device provides the fast processor continuous access to the shared device for up to a maximum number of word transfers in response to grant of one access request by the fast processor.

Abstract: A method and system of fast program downloading to a target system that includes a printed circuit board. A processor is on the printed circuit board and a target interface having electrical contact pads is embedded on the printed circuit board. The processor includes information signals coupled to the electrical contact pads. The dispatcher includes a dispatcher interface coupled to the target system via the target interface, such that dispatcher interface is coupled to the information signals of the processor.

Abstract: A computer system controlling a memory clock signal of a DIMM (dual in-line memory module) socket is described and which includes a processor controlling a 66 MHz or a 100 MHz system bus clock signal to be generated, a DIMM memory module supporting the 66 MHz or the 100 MH system bus clock signal, a clock generator generating the 66 MHz or the 100 MHz system bus clock signal by receiving control of the processor, a clock buffer, a first and a second system controllers. The clock generator and the clock buffer store setting data according to memory data of a memory module from a first system controller. The first and the second system controllers control a memory bus clock signal corresponding to an inserted single-sided type or double-sided type DIMM memory module to be outputted.

Abstract: A method for recording data about internal and external messages in a software system which is, in particular, part of a digital telecommunications switching center. Within a software system which, as a rule, comprises a number of components, the components interchange internal messages with one another and/or receive/transmit external messages to and from the outside world via an interface. Such messages are registered at so-called trace points (TP1, . . . , TPn) defined in the software system, and are transmitted without any delay to a FIFO buffer store (ZS), without any acknowledgment from the receiver, and are stored there until they are read after a request from a data-processing system (PC), which is connected to the software system, for the purpose of processing them further.

Abstract: A processor-based system provides communication among multiple computer devices operating at different frequencies utilizing clock synchronization. Phase relationship is maintained between clock signals running a different frequencies such that a read cycle of a device operated at the faster frequency is initiated when the clock signals are in phase. A write cycle of the faster frequency device is initiated when the clock signals are out of phase. A synchronization signal is generated by sampling the clock signals together to indicate the phase relationship. In addition, a return clock, derived from the faster clock, drives external devices. Information sent from internal devices to external devices are passed through a register driven by the return clock. Timing delays for information presented to the external devices is avoided as the register transmits all information according to the return clock. Return data is clocked into a return register also according to the return clock.

Abstract: A method, which may be embodied upon a computer readable medium and executed by a processor, for dynamically adjusting buffer utilization ratios for a hard disk drive system. The method establishes and dynamically adjusts a host transfer goal, which targets the amount of data transferred between host catch-up conditions for a current command. The actual amount of data transferred between host catch-up conditions is compared against the host transfer goal, and the buffer utilization ratios are adjusted when the actual amount of transferred data does not exceed the transfer goal. The host transfer goal is established by a number of operational characteristics, including drive transfer speed, host transfer speed, and track switch locations.

Abstract: According to the present invention, techniques for re-reordering command and data packets in order to restore an original order of out-of-order memory requests are described. In one embodiment, a method of increasing data bandwidth by reordering incoming memory requests in order to avoid gaps between commands on a command bus and data packets on a data bus while maintaining the original incoming memory request order is disclosed. A best position in a command queue is calculated for each new incoming command by a reordering block coupled to the command queue. Read data is stored in a data queue while the associated incoming commands are stored in their respective original order in a FIFO register included in a re-reordering block. The data is stored in its original order in a data queue while incoming data from the memory is stored in a read-data buffer included in the re-reordering block according to the order stored in the data queue.

Abstract: An improved computer clock circuit capable of automatically detecting the internal clock frequency of a peripheral component installed in a peripheral component interconnect (PCI) slot, and supplying the PCI slot with the a clock signal of a specified frequency. In one embodiment, the clock circuit comprises a reference clock generator having multiple clock frequencies, a phaselocked loop (PLL) based clock driver, and circuitry providing the clock driver with a selection signal indicative of the configuration of a component connected within a PCI slot. The PLL clock driver maintains phase coherency between the input and output signals, thereby reducing setup and hold times within the system and peripheral components. Additionally, the PLL clock driver reduces propagation delays within the clock circuitry, and greatly simplifies implementation of the clock circuit within a given design.

Abstract: A system and method for enhancing the performance of a parallel terminated bus. An implementation includes storing a minimum spacing for each transaction type in a memory, monitoring data transactions, performing a latch back operation if required, and executing a subsequent transaction following a prior transaction using a minimum spacing if the latch back operation does not occur.

Abstract: A control circuit for configuring at least one I/O module connector pin is provided. The circuit includes at least one port controlling a configuration of the at least one pin.

Abstract: A system and method for inputting a set of values, e.g. an operating frequency, using dual-use signal connections. In an exemplary computer system, one or more processors are each coupled to a bridge. The dual-use signal connections are used to input an operating frequency ratio to a processor. The operating frequency ratio may also be input to the bridge. Once the operation of the processor has been initialized, the dual-use signal connections may be used to output operating parameters of the processor. The use of the using dual-use signal connections may advantageously allow for the operating frequency ratio to be input to the processor without dedicated signal lines or pins.

Abstract: A processor coupled by a high speed, wideband data bus to a plurality of slave data processing circuits. The data bus includes an N-bit set of master registers loaded by the processor and M number of slave modules, each slave module having an N-bit slave data register. The processor can sequentially load the master data registers and transfer the data to a selected slave module in a round-robin manner. A high speed transfer of data is thereby achieved.

Abstract: A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.

Abstract: A multiprocessor computer includes a processor disabling scheme which disables a processor that has been designated to boot the computer but fails to boot the computer. For computers having voltage regulator modules (VRMs) to power each processor, a control device directs a VRM associated with the failed boot processor to cease supplying power in response to the processor's failure. For computers without VRMs, a transistor controls the delivery of power from the power supply to each respective processor. If a designated boot processor fails to boot the system, the control device turns off the appropriate transistor to disable the failed processor.

Abstract: A system and method for substituting dynamic pipelines with static queues in a pipelined processor. The system and method are to provide a reduction in power consumption and clock distribution, as well as other advantages.

Abstract: A system provides a general purpose bus with programmable timing capability. As part of a microcontroller, this general purpose bus provides a mechanism for communication between general purpose peripherals connected to the bus and enables external devices to be connected with proper timing to the microcontroller. The general purpose bus controller includes programmable interface timing control logic which allows the bus cycle length for commands from a processor or other bus master to be programmed. Accordingly, memory and I/O read and write commands are customized to suit the timing requirements of peripheral devices connected externally to the microcontroller. A significant variety of peripheral devices may thus be coupled to the microcontroller without requiring additional glue logic. The general purpose bus controller further includes an echo mode which permits accesses to internal peripheral devices to be interpreted by a logic analyzer or other debugging equipment.

Abstract: A method and apparatus for hot swapping and bus extension without data corruption. During the hot swapping of a circuit board in a bus, the bus is extended onto or retracted from the circuit board in a manner which does not corrupt the data on the bus. The extension or retraction of the bus is detected and a bus reset is asserted interrupting and preventing transactions on the bus. The bus reset is asserted for a minimum amount of time to allow the bus to stabilize after the hot swap. A bus extension/retraction detection component and a bus reset component perform these functions.

Abstract: A buffer manager provides address information for reading and writing data to an SDRAM. The address information is translated from a flat memory address space into an SDRAM address space. The buffer manager operates based upon a first clock and the SDRAM operates based upon a second clock. Accordingly, a synchronization circuit synchronizes the data. The translation of address information occurs simultaneously with the synchronization of data.

Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.