Abstract: An electromechanical data storage arrangement is interfaced with a host. The interface may include a conductor that carries read and write gate signals. Another conductor carries both a servo sync mark and an error signal. The storage arrangement includes an external serial interface connected to a host serial interface applying a device identification to a portion of serial control-related data that travels over the interface. A serial router in the storage arrangement uses the device identification to manage the control-related data between the interface and a number of serial devices and associated interfaces within the storage arrangement. The serial router is in selective data communication with each of the device serial interfaces, for using the device identification to direct a host-asserted command to a targeted device where each device is controlled by a different command set such that the system can be customized for different command sets of different devices.

Abstract: TV software can be updated by receiving updated from a USB drive or wirelessly, in either case preferably over a synchronous bus for speedier data transfer.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by a prescribed number of cycles. The select vector is reduced by an amount and is gray encoded to indicate a first time. The receivers are each coupled to the delay-locked loop. Each of the receivers receives the encoded select vector and a corresponding strobe, and locks out reception of die corresponding strobe for a configurable lockout lime following transition of the corresponding strobe. The encoded select vector is employed by a gray code mux therein to determine the configurable lockout time by selecting a delayed version of the corresponding strobe.

Abstract: The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency.

Abstract: A data processing apparatus includes a first memory which comprises a first input/output port and a second input/output port; a second memory which is connected to the first memory and comprises a third input/output port; and a controller for controlling the first and second memories to perform operations of: (a) writing data to the first memory through the first input/output port; (b) reading the data from the first memory through the second input/output port; (c) writing the data read out of the first memory to the second memory through the third input/output port; and (d) reading the data from the second memory through the third input/output port; wherein the operation (a) is performed at a first frequency and the operations (b), (c), (d) are each performed at a second frequency, wherein either: (i) the first frequency is different from the second frequency, or (ii) the first frequency is equal to the second frequency but in each of the operations (b), (c) and (d) the data is different in phase than in the

Abstract: The invention provides a method and apparatus for providing an access layer for web-based applications to access at least one resource of a local host. The interface is removed from the application code and the application code exchanges data with the access layer to access the local resources of the local host. Among other things, the invention allows web-based applications to interact with the local file system, to allow end users to browse directory trees of internal or external storage devices, and to work offline.

Abstract: A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.

Abstract: The present invention is related to an interface design for multimedia data transmitting, which can provide a working interface in a data storing device or a communication device, using the working interface can provide the connecting facility between a multimedia device and computer system and improve the traditional high speed differential signals to portable digital data processing device.

Abstract: A pair of processing modules and methods that enable low latency communications between a data processing system and devices located at a remote graphic user interface across a standard shared network in accordance with the present invention is disclosed. The present invention provides a method for communicating graphics data in a synchronous manner from the data processing system to the user. This method is used in conjunction with a feedback error recovery method to provide lossless, low-latency communications of graphics data across the network.

Abstract: A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general purpose IO block in a heterogeneous configurable integrated circuit (HCIC).

Abstract: This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Abstract: An information processing device includes: an interface to/from which a recording medium is attachable/detachable; a data storage device that stores data; a data extractor that extracts data recorded on the recording medium connected through the interface, with the data maintained in a data configuration of the recording medium; and a controller that controls the data storage device to store the data extracted by the data extractor together with an identifier which specifies the recording medium, with the data maintained in the data configuration extracted.

Abstract: The amount of jitter incurred when reading data written into a FIFO can be reduced by clocking the FIFO with Read Clock pulses at a frequency xfn where x is a whole integer and fn is the frequency at which the memory is clocked to write data. Read Addresses are applied to the FIFO at a frequency on the order of fn to identify successive locations in the memory for reading when the memory is clocked with read clocked pulses to enable reading of samples stored at such successive locations. The duration of at least one successive Read Addresses is altered in response to memory usage status to maintain memory capacity below a prescribed threshold.

Abstract: A method is complementary to processing a retrieve and process pipe specification. The pipe specification is characterized by at least one constituent pipe, each constituent pipe being characterized by at least one of a group consisting of an input node and an output node. The input node is configured to input data, such as a syndication data feed or other data accessible via a web service and the output node is configured to output data, such as a syndication data feed. At least one of the constituent pipes includes a module configured to retrieve data via a web service, such as a source syndication data feed. The wires are configured according to the retrieve and process pipe specification. An amount of time to process the pipe specification is estimated, including an amount of time to retrieve data via the web services as specified in the pipe specification.

Abstract: Full-duplex communication over a communication link between an initiator operating with an initiator clock and a target operating with a target clock involves, in communication from the initiator to the target: storing data from the initiator in a first FIFO memory with the initiator clock, reading data from the initiator stored in the first FIFO memory, wherein reading is with the target clock transmitting the data read from the first FIFO memory over a first mesochronous link, and storing the data transmitted over the first mesochronous link in a buffer whereby the data are made available to the target. Communication from the target to the initiator includes: transmitting data from the target over a second mesochronous link, and storing the data transmitted over the second mesochronous link in a second FIFO memory, wherein storing is with the target clock, whereby the data are made available to the initiator for reading from the second FIFO memory with the initiator clock signal.

Abstract: This invention offers a data communication system that can perform data communication and detection of a data read-in request signal while reducing the number of communication lines to three, and is tolerant of noise. The data communication between a microcomputer and a key scan IC and the detection of the data read-in request signal are performed through a control line, a clock line and a data line. The data communication system is provided with a data line control circuit that controls the data line so that outputting of the data read-in signal RDRQ to the data line is disabled when first command data is inputted to the key scan IC through the data line, and that the outputting of the data read-in request signal RDRQ to the data line is enabled when second command data is inputted from the microcomputer to the key scan IC through the data line.

Abstract: The present invention centralizes the processing the combined horizontal and vertical sync signals in a master device and thereby keeps the interface devices as simple as possible so as to reduce the cost of the interface devices. The interface device mainly only converts the separate horizontal sync signal and vertical sync signal, or the combined horizontal and vertical sync signal to a default polarity. On the other hand, the separation of the combined horizontal and vertical sync signal into individual horizontal and vertical sync signals are all carried out by the master device.

Abstract: A data writing device capable of dynamically switching between a write-through mode and a write-behind mode for writing transaction data into a disk including: a memory with a queue management table for managing a write disk queue and a write memory queue to store the transaction data; means for registering the write memory queue in the table when load exceeds a predetermined threshold value, and for deleting the write memory queue in the table when the load is below the predetermined threshold value; means for receiving the transaction data stored in the write disk queue, and writing the received transaction data into the disk; and means for receiving the transaction data stored in the write disk queue, and writing the received transaction data into a redundant memory.

Abstract: A bus converter is disclosed that converts a signal of a synchronous bus into a signal of an asynchronous bus. The bus converter includes a control signal generation unit that generates n control signals synchronized at different timings of a predetermined synchronization signal, where n is an integer of two or more; and an output unit that outputs the signal of the synchronous bus divided into n signal groups based on a control using the n control signals.

Abstract: In a mobile wireless device, a camera module can be connected directly to a digital baseband processor that does not have a special interface, without the need for an external coprocessor. The data interface of the camera module is directly connected to pins of a general purpose input/output port on the digital baseband processor to enable the baseband processor to capture the synchronous parallel data stream from the camera module. A clock signal from the camera module can be used to trigger DMA transfers of the image data captured by the general purpose input/output port of the baseband processor.

Abstract: A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment and the second bus segment, which is separate from the first bus segment, is operatively coupled to one or more second bus agents. The first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment. The system also includes first electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the first bus segment and to write the messages onto the second bus segment and second electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the second bus segment and to write the messages onto the first bus segment.

Abstract: A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates an interface signal and outputs the generated interface signal to an interface bus; and an internal register in which is set timing information for specifying a timing at which a signal level of the interface signal output from the interface circuit changes. The interface circuit generates the interface signal, a signal level of which changes at a timing according to the timing information set in the internal register.

Abstract: A control device for a USB interface including at least one first terminal for inputting the data to be transmitted and at least one second terminal for the transmission of the packet data on a bus; the packet data include one end-of-packet signal. The USB interface includes one circuit for the data transmission on said at least one second terminal; the USB interface is adapted to receive as an input a signal for the activation of the transmission circuit when data are received from the at least one first terminal and the transmission circuit includes a bias circuit. The control device includes a circuit for the detection of an end-of packet signal on said bus and a control circuit adapted to activate the bias circuit of the transmission circuit if said end-of-packet signal is detected by said detection circuit.

Abstract: A terminal of a plurality of terminals that is located at the farthest position from a host has a return signal generator section, the return signal generator section transmits a return signal at a timing when data transmitted from the host to the terminals arrives at the terminal located at the farthest position, the return signal is returned to the host successively passing through interfaces of the terminals connected to a data bus, and each terminal originates data to be transmitted from the terminal to the host or from the terminal to a particular another terminal in synchronization with the return signal and delivers the data from the terminals to the host or the terminal in synchronization with the return signal.

Abstract: Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Abstract: The present invention relates to a technique to absorb a speed difference between a data transmission/reception unit, included in a host device which has a interface controller, and a data transmission/reception unit with a external device. The host device and the external apparatus are both electronic apparatus, and the interface controller outputs a transfer clock to the external apparatus, and controls the data transfer between the interface controller and the external apparatus, in accordance with a specific interface specification defined based on the transfer clock.

Abstract: A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A reading section reads the accumulated data successively from the FIFO buffer memory at an variable output rate so that the data amount residing in the FIFO buffer memory varies temporally. A detector detects a current data amount residing in the FIFO buffer memory, and a current direction of variation of the data amount residing in the FIFO buffer memory. A loop filter generates control information according to both of the detected current data amount and the detected current direction of variation of the data amount. A controller regulates the output rate according to the control information so as to promptly converge the current data amount residing in the FIFO buffer memory to a target data amount.

Abstract: A data transfer control device includes: a link controller which analyzes a packet received from a host-side data transfer control device through a serial bus; and an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus. A packet transferred from the host-side data transfer control device through the serial bus includes a synchronization signal code field for setting a synchronization signal code. The interface circuit generates synchronization signals FPFRAME and FPLINE included in the interface signals based on the synchronization signal code set in the packet.

Abstract: A host device continuously transmits a same command or a same piece of data to a remote device in serial format. The remote device receives the command or the data, and then determines whether the command or the data has an error. When the command or the data has no error, the remote device transmits a response to the host device. Upon reception of the response, the host device stops the continuous transmission of the command or the data.

Abstract: Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on a signal path by a transmitting component. The one or more null frames transmitted prior to the sync frame results in a settling of the signal path prior to reception of the sync frame, thereby lessening or removing the effects of previously sent data on the sync frame.

Abstract: Techniques for improving the quality or fidelity of a digital signal transmitted via a two-wire bus interconnect utilizing an open-terminal configuration at one or both end devices of the bus interconnect are disclosed. An intermediate two-wire bus is used to connect two open-terminal-based two-wire busses. A bus adapter device is utilized at each end of the intermediate two-wire bus, whereby the bus adapter device communicates signaling on the corresponding open-terminal-based two-wire bus using open-terminal ports and communicates signaling on the intermediate two-wire bus using push-pull ports. The bus adapter device can utilize control logic to implement a state machine or other function to control the interactions between the different two-wire buses. The bus adapter devices may be implemented as interchangeable integrated circuit devices that can change configuration based on connection, thereby permitting their implementation at either end of a bus transmission system.

Abstract: A control circuit for controlling an arc suppression circuit includes a serial communication link communicating a serial signal therethrough. The control circuit includes a microprocessor having a serial input communicating with the serial communication link. The microprocessor generates a control output signal in response to the serial signal. The control circuit further includes the arc suppression circuit having an electrical contact and operating in response to the control output signal to reduce an arc at the electrical contact.

Abstract: A data transmission system where an image providing device and a printer are directly connected by a 1394 serial bus, a command is sent from the image providing device to the printer, then a response to the command is returned from the printer to the image providing device. Image data is sent from the image providing device to the printer based on information included in the response. The printer converts the image data outputted from the image providing device into print data. Thus, printing can be performed without a host computer by directly connecting the image providing device and the printer by the 1394 serial bus or the like.

Abstract: An input/output byte control device using a nonvolatile ferroelectric register can maintain compatibility with various memories by selectively controlling bytes of input/output data. Since bytes of input/output data are selectively activated, the compatibility can be maintained with SRAM (Static Random Access Memory) having wide bytes and flash memory having fixed input/output bytes. Additionally, programs can be changed in a software system using a nonvolatile ferroelectric register.

Abstract: An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link from the controller to each module. Each communication link includes a data out line, a data in line and a clock line, where each clock line is derived from one clock source.

Abstract: A sync circuit of a data transmission interface connected between a first data port and a second data port is provided. The sync circuit includes a first resistor element, a capacitor element, a second resistor element, and an active element. When the signal generated by the first data port is logic 1, the active element is turned off, such that the power source end charges the capacitor element through the first resistor element. Otherwise, when the signal generated by the first data port is logic 0, the active element is turned on, such that the capacitor discharge through the second resistor element, for delaying the data of the first data port for a predetermined time and making the data of the second data port synchronously transmitted on the first data port.

Abstract: A method of performing a burst read access at a memory device using a multiplexed data/address bus and a control signal including transferring a first portion of address information in a first phase via the multiplexed data/address bus to the memory device; transferring second portion of address information in a second phase via a multiplexed data/address bus to the memory device; transferring a series of data words from the memory via the multiplexed data/address bus; toggling the state of the control signal at the memory device as each data word is transferred; and suspending the transfer of the series of data words from the memory via the multiplexed data/address bus and the toggling of the state of the control signal.

Abstract: The invention relates to a communications method of communicating states from an activation unit to a receiver via a communications bus, wherein the state may be activation/deactivation of an activation unit, and wherein the state is communicated to the receiver via a serial data stream timed by a clock signal, said data stream transmitting data packets which comprise an identification part and a data pare wherein: ? the identification part comprises a plurality of bits which identify which activation units the data packet concerns, and ? the data part comprises a plurality of bits which individually identify the state of an activation unit. The invention also relates to a system based on the communications method and comprising an activation unit and a receiver. In addition, the invention relates to an activation unit and a receiver.

Abstract: A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a central processing unit (CPU) configured to output first control signals in response to a first clock signal, a first bus connected to the CPU, a bridge circuit connected to the first bus, a second bus connected to the bridge circuit, a plurality of peripheral circuits connected to the second bus, and a clock monitor connected to the first bus or the second bus and configured to output a register value corresponding to a second clock signal to the bridge circuit. The bridge circuit receives the first control signals, generates second control signals based on the register value, and outputs the second control signals to one of the peripheral circuits via the second bus.

Abstract: A media access controller, which includes an output buffer and a clock controller, is provided. The output buffer includes a first and second clock input. The first clock is configured to control data input into the buffer and the second clock is configured to control data output from the buffer. The clock controller is coupled to the output buffer and configured to regulate a first clock signal input into the first clock input to control the data input into the buffer.

Abstract: Systems and methods for responding to a data transfer are disclosed. One embodiment comprises a method that includes the following steps: determining a sustainable data transfer rate for data transfers to/from an external memory medium, acquiring a data stream, transforming the data stream, and selecting a value for at least one operational parameter associated with acquiring or transforming the data stream in response to the sustainable data transfer rate.

Abstract: Universal network interfaces for a home network connect disparate components to the network, such as relatively complex components (TVs, computers) and relatively simple components (audio boom boxes).

Abstract: A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.

Abstract: A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configure

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.

Abstract: The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring signals. The bus is arranged to operate according to a protocol in which said first station repeatedly sends requests for data to the second station. The protocol comprises a first mode for transferring the requests in a first request format at a first communication speed and at least a second mode for transferring said requests in a second request format at a second speed. The second station is arranged to receive requests in a mode selected from a group of modes comprising said first and second modes, and is arranged to give a first indication to said first station if it is arranged to operate according to the first mode and a second indication if it is arranged to operate according to the second mode. The first station comprises a processor, a controller, and a translator. The processor is operable to generate request properties for requests in the first request format.

Abstract: The present invention provides a memory card for use with an electronic device. The memory card comprises an input/output (I/O) interface for coupling the memory card to the electronic device and a card controller electrically coupled to the I/O interface. In particular, the card controller comprises a plurality of engines configured to operate in different formats. The card controller further comprises a means for detecting the format of the electronic device and generating a response signal containing the format of the electronic device. A micro-controller is electrically coupled to the plurality of engines, wherein the micro-controller activates an appropriate engine from the plurality of engines to transfer data based on the response signal. Furthermore, the memory comprises a memory module electrically coupled to the plurality of engines for storing data. One advantage of the memory card is that it enables a user to store and transfer data in various formats.

Abstract: A transmission method for a serial periphery interface (SPI) serial flash includes the steps of providing a first system clock signal and transmitting a plurality of data strings with each two bits of the data strings transmitted in a period of the first system clock signal. A second system clock signal is generated by the first system clock signal to provide a double frequency to enhance the transmission rate of all the data inputted into or outputted from the SPI serial flash.