Abstract: A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual-mode squelch detectors in a first (handshake) mode of operation. The USB device transmits a device chirp signal to the USB hub. The USB hub responds with a sequence of hub chirp signals. The USB device detects the hub chirp signals and then the USB hub and the USB device establish a communication link in a high-speed mode of communication in accordance with USB 2.0. The dual-mode squelch detectors in the USB hub and the USB device can also be activated in a second (normal) mode of operation.

Abstract: In one embodiment, a circuit includes an input buffer, an output buffer, a counter, an issuing unit, a first controller, a register, and a second controller. The input buffer and the output buffer have a variable storage capacity. The counter cyclically counts from a first value to a second value. The issuing unit issues a write command if a count value of the counter is a third value and issues a read command if the count value is a fourth value. The register stores a first setting value, a second setting value and a third setting value to be capable of changing each of the setting values. The second controller controls the components to set the storage capacity, the second value, and one of the third and fourth values respectively to values corresponding to the first to third setting values.

Abstract: A method and communication system that provide an inexpensive approach that enables the times of events that are detected in IO device to be determined in a higher-level controller. The higher-level controller has a system clock and is connected to an IO link device to which multiple first IO devices are able to be connected. In addition, a second IO device is connected to the IO link device. The clock of the second IO device is synchronized by a synchronization device with the system clock of the higher-level controller. The status data that are provided by at least one of the first IO devices and the current time data that the second IO device supplies are transmitted simultaneously to the IO link device. The IO link device assigns the status data received to the received current time data, then transmits these data to the higher-level controller.

Abstract: A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buffer is configured to buffer data input through a data pad and output the buffered data. The synchronous data input buffer is configured to be synchronous with the internal clock to buffer the buffered data. The semiconductor apparatus is arranged so that the length of a line for transferring the internal clock to the synchronous data input buffer and the length of a line for transferring the buffered data to the synchronous data input buffer are substantially equal to each other.

Abstract: A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony.

Abstract: The semiconductor integrated circuit having a transmitter circuit for transmitting a supplied external data signal DIN. The transmitter circuit includes: a transmitter flip-flop circuit having a reference clock CK as an input for holding the external data signal DIN in synchronization with the reference clock CK; a frequency divider circuit for multiplying the frequency of the reference clock CK by n/m (m and n are integers equal to or more than 2 and m>n); a data signal buffer circuit for transmitting a data signal held by the transmitter flipflop circuit; and a clock buffer circuit for transmitting the output of the frequency divider circuit.

Abstract: A method of transmitting data on a data line between a central control device and a decentralized data processing device. During a normal operation of the system, the central control device periodically sends synchronization pulses to the at least one data processing device via the data line in order to request data packets, and the decentralized data processing device sends the data thereof to be transmitted, as data packets, to the central control device, following the synchronization pulse. The data line is embodied as a data bus. Each of the decentralized data processing devices is configured by the central control device before the first transmission of data packets to the central control device. In order to configure the system, a bi-directional communication is carried out between the central control device and the at least one decentralized data processing device.

Abstract: A pair of processing modules and methods that enable low latency communications between a data processing system and devices located at a remote graphic user interface across a standard shared network in accordance with the present invention is disclosed. In one embodiment, an apparatus for communicating a raster video signal comprises a receiver enabled to receive the raster video signal from a graphics processor and obtain display control parameters of the raster video signal, the display control parameters comprising frequency and resolution information for the raster video signal; a raster encoder, coupled to the receiver, enabled to encode a plurality of scan lines of the raster video signal to generate a plurality of encoded scan lines; and a network controller, coupled to the raster encoder, enabled to transmit the plurality of encoded scan lines and the display control parameters as packets via an IP/Ethernet network.

Abstract: A method according to one embodiment includes receiving a request to perform a backup of data associated with an application running on multiple servers; calculating a time value based on communications with the servers, the time value calculation including at least one of a latency of at least one of the communications, and a difference between a reference time clock value and a time clock value of at least one of the servers; and communicating with I/O Handlers on the servers for initiating a coordinated backup operation on the data at about a same start time. Additional systems, methods, and computer program products are also disclosed.

Abstract: The disclosed system and methods involve controlling the timing and order in which numerous motors and sensors exchange data over a data bus. The method can be used with, for example, motion control, automotive, industrial automation, and medical equipment applications using data buses. As an example of one possible medical equipment application, the method of exchanging data on a bus can be used with a remote catheter guidance system. The disclosed system and methods help optimize data exchange over a bus and avoid collisions by grouping the transmission of sensor readings, by grouping the transmission of motor commands, and by predetermining the order of these groups. Further, the method provides a way of ensuring that incomplete data sets are not exchanged over the bus. The method also provides a way of synchronizing motor actuation based on data transmitted to the data bus.

Abstract: A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.

Abstract: A method and apparatus for synchronizing I/O peripherals with a CPU in an embedded system is discussed. The method involves receiving an address from the CPU in response to a read and/or write access, translating the address received from the CPU to identify a I/O peripheral to be accessed, disabling the operation of the CPU and synchronizing a memory from the CPU clock domain to the clock domain of the identified I/O peripheral. Upon completion of the read/write access, the identified I/O peripheral sends an acknowledgment, the memory is then synchronized from the clock domain of the I/O peripheral to the CPU clock domain and the operation of the CPU is then enabled. In another embodiment, if the acknowledgement from the identified I/O peripheral is not received within a predefined time duration, reserved data is sent to the CPU and the operation/access can be restarted.

Abstract: There is provided a data transfer method in an IEEE1394 system including a band request node and a transfer band management node. The method includes generating, at the band request node, a transfer request that can detect a data amount of transfer data and transmitting the transfer request from the band request node to the transfer band management node, determining, by the transfer band management node, whether a transfer band requested by the transfer request is ensured or not, notifying, from the transfer band management node, the band request node of the determination result, and transferring data from the band request node according to the determination result.

Abstract: This invention offers a data communication system that can perform data communication and detection of a data read-in request signal while reducing the number of communication lines to three, and is tolerant of noise. The data communication between a microcomputer and a key scan IC and the detection of the data read-in request signal are performed through a control line, a clock line and a data line. The data communication system is provided with a data line control circuit that controls the data line so that outputting of the data read-in signal RDRQ to the data line is disabled when first command data is inputted to the key scan IC through the data line, and that the outputting of the data read-in request signal RDRQ to the data line is enabled when second command data is inputted from the microcomputer to the key scan IC through the data line.

Abstract: A control unit is described that has at least one communications interface for the exchange of data with at least one peripheral unit, the communications interface being configured for transmitting synchronization signals to the peripheral unit in a first, synchronous operating mode. The communications interface is configured to change a time interval between two successive synchronization signals.

Abstract: A method of operating an automation system with a plurality of automation devices connected for communication with a central unit is provided. Each automation device handles communication in accordance with a send clock. The central unit stores for each automation device accessible for communication information about the send clock for this device in a database. Further, the central unit handles communication with the automation devices according to their individual send clock.

Abstract: A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

Abstract: An I/O device is provided to accurately synchronize clocks between nodes to have a device driving signal directly made out from the clocks, so that operation timing can be synchronized between the nodes regardless of a processing flicker on a host computer and a delay in a communication channel, and so that sending and receiving of a communication frame between the nodes, updating of contents of the communication frame, etc. can be efficiently performed.

Abstract: A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data register unit in response to the strobe or non-free running clock and to output the data stored, in response to another clock.

Abstract: A communication protocol over the serial bus allows a peripheral device to control the flow of data between a host computer and the peripheral device so as to maintain synchronization to a periodic reference signal. The protocol involves transferring flow control messages between the peripheral device and the host computer, allowing the peripheral device to control how and when the host computer sends the uncompressed audio and video data.

Abstract: In a method and apparatus for saving power in a device coupled to a bus, the device is placed to operate in a power saving mode by powering off a selective portion of the device including a device clock. If data communication over the bus is addressed to the device then the selective portion of the device, including the device clock, is triggered to return to a power on state from the power off state. The data communication is stored in shadow registers using a bus clock while the device clock is transitioning to the power on state. The data communication stored in the shadow registers is transferred to a register map under the control of the device clock operating in the power on state. Upon completion of the transfer of the data communication to the register map, the device is returned to operate in the power saving mode.

Abstract: A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a selected one of the memory die an internal read command responsive to an external read command. The selected memory die is configured to provide read data to the controller in response to the internal read command; wherein latency between receipt by the controller die of the external read command and receipt of the read data from the selected memory die differs for at least two of the memory die when selected as the selected memory die.

Abstract: A method for the synchronization of a radio receiver, comprising an estimation of the moment when a pulse (11, 17) is received (11, 17), performed from the moment when a previous pulse was received. The estimated moment is compared with the real moment when the pulse (21, 27) is received in order to validate an association of pulses with values of a code recorded in the receiver (31, 37). A moment for the beginning of transmission of a symbol is thus deduced, enabling the receiver to be synchronized in relation to the transmitted radio pulse sequence.

Abstract: A pair of processing modules and methods that enable low latency communications between a data processing system and devices located at a remote graphic user interface across a standard shared network in accordance with the present invention is disclosed. The present invention provides a method for communicating graphics data in a synchronous manner from the data processing system to the user. This method is used in conjunction with a feedback error recovery method to provide lossless, low-latency communications of graphics data across the network.

Abstract: A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.

Abstract: A system for providing a secondary processing environment to a computer system having a host processor includes a secondary processor configured to perform a processing service, a policy manager configured to control interaction between the secondary processor and the host processor, a service provider configured to provide the processing service to the computer system and a host-state monitor to monitor state of the host processor, wherein the secondary processor operation is based on the state of the host processor.

Abstract: A method of performing a burst read access at a memory device using a multiplexed data/address bus and a control signal including transferring a first portion of address information in a first phase via the multiplexed data/address bus to the memory device; transferring second portion of address information in a second phase via a multiplexed data/address bus to the memory device; transferring a series of data words from the memory via the multiplexed data/address bus; toggling the state of the control signal at the memory device as each data word is transferred; and suspending the transfer of the series of data words from the memory via the multiplexed data/address bus and the toggling of the state of the control signal.

Abstract: An architecture for control systems including multiple control devices. The control devices include standardized software objects having functions, application programs for engaging these functions and thereby defining the operation of the control devices, and an engine for executing the application programs. The standardized software objects implement different types of internal functions for the control devices and feature reference numbering and function calls shared in common with the other software objects of the same type that may be on different control devices across said system. The software application programs include standardized instructions reflecting the reference numbering and function calls shared across the system by the said software objects whose functions are used in building the functionality of the control devices in the application programs.

Abstract: A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment and the second bus segment, which is separate from the first bus segment, is operatively coupled to one or more second bus agents. The first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment. The system also includes first electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the first bus segment and to write the messages onto the second bus segment and second electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the second bus segment and to write the messages onto the first bus segment.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by a prescribed number of cycles. The select vector is reduced by an amount and is gray encoded to indicate the lockout time. The receivers are each coupled to the delay-locked loop. Each of the receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed by a gray code mux therein to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A memory subsystem configured to perform event-driven training. The memory subsystem includes a memory, a memory controller coupled to the memory, and a monitoring unit coupled to the memory controller. The monitoring unit is configured to monitor at least one parameter of the memory subsystem, determine whether at least one parameter is within a specified range, and provide an indication to the memory controller if at least one parameter is not within the specified range. The memory controller is configured to perform a training procedure responsive to receiving the indication. Performing the training procedure includes the memory controller performing at least one write to memory, at least one read from memory, and adjusting a delay for one or more signals conveyed between the memory controller and the memory.

Abstract: A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buffer is configured to buffer data input through a data pad and output the buffered data. The synchronous data input buffer is configured to be synchronous with the internal clock to buffer the buffered data. The semiconductor apparatus is arranged so that the length of a line for transferring the internal clock to the synchronous data input buffer and the length of a line for transferring the buffered data to the synchronous data input buffer are substantially equal to each other.

Abstract: Synchronization management is provided for a continuous serial data streaming application wherein the serial data stream includes a plurality of consecutive, identical-length segments of consecutive serial data bits. Synchronization management bits are provided in each segment. The synchronization management bits are programmed such that the synchronization management bits contained in first and second adjacent segments of the serial data stream will bear a predetermined relationship to one another. At the receiving end, the synchronization management bits are examined from segment to segment. In this manner, synchronization can be monitored, synchronization loss can be detected, and synchronization recovery can be achieved.

Abstract: One embodiment provides a system including a communications channel, a first channel master, and a second channel master. The first channel master is configured to obtain latency values and maintain a first schedule of data traffic on the communications channel based on the latency values. The second channel master is configured to obtain the latency values and maintain a second schedule of data traffic on the communications channel based on the latency values. The first channel master manages data on the communications channel via the first schedule and the second channel master manages data on the communications channel via the second schedule.

Abstract: A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.

Abstract: A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.

Abstract: A first device transmits messages to a second device. The first device keeps track of messages that have already been transmitted from the first device to the second device, experiences an interruption in transmission of messages at the first device, and resumes the transmission from the first device following the interruption. Resuming the transmission includes transmitting only messages that have not already been completely transmitted from the first device to the second device.

Abstract: A time-triggered communication system in a dual-channel network of singlechannel architecture, wherein in each case one communication controller (2, 6) is assigned to one channel, and two corresponding communication controllers (2, 6) communicate with one another via an inter-channel interface (1a, 1b). Said inter-channel communication contains information about limiting points (G1, G2 . . . G12) of a time path. A limiting point (G1, G2 . . . G12) is, for example, the point in time when a cycle starts. The interchange of limiting points enables the temporal offset of the two channels to be determined as well as a correction value. After every two cycles also the rate error of the local clocks can be ascertained and a suitable correction value determined. The reliability of safety-relevant networks is increased by the time-triggered communication system described hereinabove.

Abstract: A signal generating apparatus, applicable in a universal serial bus (USB) device, includes: a first determining circuit for receiving a data signal to determine if the data signal is generated by the universal serial bus device, and generating a first determined result; a second determining circuit coupled to the first determining circuit for receiving the data signal and the first determined result to determine a transmitting mode corresponding to the data signal according to the first determined result, and generating a second determined result; and a frequency generating circuit coupled to the second determining circuit for generating a first clock signal utilized for synchronizing the data signal according to the second determined result.

Abstract: In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.

Abstract: A method, apparatus and software is disclosed for processing input/output (I/O) requests for a mirrored storage volume in recovery mode in which the processing of normal I/O is optimised using the recovery map for the volume.

Abstract: A communication system carrying out an isochronous transfer, includes a cycle master node and nodes connected with each other through a system bus. The cycle master node sets a cycle time of the isochronous transfer and transfers a cycle start packet onto the system bus for every the cycle time. Each of the nodes transfers an isochronous packet onto the system bus in response to the cycle start packet.

Abstract: Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system.

Abstract: A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by the lockout time. The lockout time is slightly less than a number of cycles of the reference clock. The one or more receivers are each coupled to the delay-locked loop. Each of the one or more receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: A method and system for enabling personal digital assistants (PDAs) and protecting stored private data. Specifically, one embodiment in accordance with the present invention includes a removable expansion card about the size of a postage stamp which plugs into a slot of a personal digital assistant. The removable expansion card, referred to as a personality card, is capable of storing all of a user's private information and data which is used within their personal digital assistant. By removing the personality card from the personal digital assistant, all of the user's private information and data may be removed from the personal digital assistant. Furthermore, the personal digital assistant may also be rendered totally or partially useless once the personality card is removed from it. There are several advantages associated with a personality card system in accordance with the present invention.