Abstract: An asynchronous serial port provides automatic parity generation and detection in frames supporting address bits. In data frames comprising a variable number of data bits, the parity bit is located immediately following the last data bit and before the address bit. Parity generation is performed automatically based only on the preceding data bits. Parity detection allows interrupts to be generated directly from the parity bit received. Further, parity generation and detection is not dependent on the number of bits in the data frame.

Abstract: A data receiver is incorporated in a controller which receives data from memory modules. The data transfer is provided with an S receiver and a D receiver. The S receiver is driven on the basis of first multiphase clocks and receives strobe signals. The D receiver is driven on the basis of outputs from the S receiver, which receives states of the strobe signals at the respective times, and the second multiphase clocks which lag the first multiphase clocks by a predetermined length of time. The D receiver receives data and transfers the same. The S receiver is controlled for burst data transfer such that the S receiver is set in an active state immediately before a strobe signal corresponding to a start item of burst data rises, and is set in an inactive state after a last item of the burst data is received. A multiphase clock generator is provided. The multiphase clock generator generates the first and second multiphase clocks which have predetermined phase differences and are equal in period.

Abstract: Memory modules and a controller are arranged and two clock lines are provided to go and return along the arrangement of the memory modules and the controller. A first basic clock and a second basic clock having twice the cycle period of the first basic clock are transferred over the go portions of the respective clock lines to the memory modules and the controller. After passing through the turnaround point, the first and second basic clocks are transferred as return clocks over the return portions of the clock lines to the memory modules and the controller. The first and second basic go clocks and the first and second basic return clocks are fed into the memory modules and the controller. The input/output operation of data is controlled synchronously with these clocks.

Abstract: A data processing method of recording data on a recording medium mounted on an information recording apparatus. The data processing method includes the steps of dividing, in a disk controller, parallel data constituted by p bits transferred from a high-rank device into data each having q bits, where p and q are numbers; transferring the data each having q bits from the disk controller to an encoder as parallel data constituted by q bits; encoding, in the encoder, the data each having q bits to generate recording signals corresponding to data to be recorded; and recording the recording signals on the recording medium, thereby recording the data to be recorded on the recording medium.

Abstract: A method is provided for I/O data transfer between memory and disk. In one embodiment, an application program generates N data transfer requests. Thereafter, a data transfer list is created that comprises N entries each comprising a file sector descriptor and a buffer address. The application program is suspended in favor of initiating the operating system. Thereafter, N data transfers are performed, each one of which comprises transferring data between a file sector and a buffer identified by the file sector descriptor and a buffer address, respectively, contained in one of the entries of the data transfer list. On completion of N data transfers, the operating system is suspended and the application program is reinitiated.

Abstract: An apparatus including a phase detector to detect a phase difference between an output clock signal and a local reference clock signal comprising a first sampling circuit and a second sampling circuit to cross-sample the output clock signal and the local reference clock signal respectively and a comparator circuit coupled to the two sampling circuits that detects the phase difference.

Abstract: A data recorder for recording data onto a record medium on which a sync signal is inserted at a given interval, has a sequence controller, wherein, after receiving the command from the system controller which triggers an initiation of a recording operation, the sequence controller activates the first encoder in response to a leading end signal of the encoded block from the sync signal set-up section, activates the first encoder and the second encoder in response to a leading end signal of the next encoded block, and activates the first encoder, the second encoder and the data reader in response to a leading end signal of the next following encoded block, and wherein, during the absence of the command from the system controller which triggers an initiation of a recording operation, the sequence controller deactivates the first encoder in response to a leading end signal of an encoded block from the sync signal set-up section, deactivates the first encoder and the second encoder in response to a leading end sig

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: A data transfer device for unidirectional serial data transfer from a transmitting device to a receiving device, in particular from a microcontroller to an output stage IC of a motor vehicle control unit. The data transfer device includes a P/S converter provided in the transmitting device for converting a parallel data stream made available in the transmitting device into a serial data stream with transfer frames of a predefined format and for transmitting the serial data stream to the receiving device over a data transfer channel. The data transfer device also includes an S/P converter provided in the receiving device for converting the transmitted serial data stream back into a parallel data stream, and a clock signal generating device for generating a clock signal and for sending the clock signal to the P/S converter and the S/P converter to perform the conversion operations continuously and in-phase.

Abstract: The present invention provides a new crossbar switch which is implemented by a first plurality of chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. The crossbar switch can be implemented to support only one node, then one chip can be used to route all 64 bits in parallel for 64 bit microprocessors. A second plurality of chips in parallel provides the redundancy necessary for a high availability system.

Abstract: Isochronous information is transferred between an IO device and a first buffer (N) of a plurality of buffers in a system memory. The isochronous information stored in the plurality of buffers is also stored in a memory cache accessible to a system processor. The state of the memory cache is managed according to an isochronous “X-T” contract that is independent of the “X-T” contact with which data are moved between the IO device and system memory. Further, data associated with a given buffer are moved into and out of the memory cache substantially simultaneously with the transfer of isochronous information between the IO device and other buffers in the system memory.

Abstract: A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively couples the controller and the multiple loads. In another embodiment, the invention transfers data between a memory controller and a RAM by coupling the controller and the RAM using a data bus and multiple clock lines. The invention transfers a read/write command from the controller to the RAM and then transfers data associated with the read/write command, clocking the data using one of the clock lines.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: A disk drive array controller and method carries out disk drive data transfers not only concurrently but also synchronously with respect to all of the drives in the array. For synchronous operation, only a single-channel DMA is required to manage the buffer memory. A single, common strobe is coupled to all of the drives for synchronous read and write operations, thereby reducing controller complexity and pin count. A ring-structure drive data bus together with double buffering techniques allows use of a single, common shift clock instead of a series of staggered strobes as required in prior art for multiplexing/demultiplexing buffer memory data, again providing for reduced controller complexity and pin count in a preferred integrated circuit embodiment of the new disk array controller. Methods and circuitry also are disclosed for generating and storing redundant data (e.g. “check” or parity data) “on the fly” during a write operation to a RAID array.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). The data are read out from the memory in an order corresponding to a control signal (WT) in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A process for initializing a serial link between two integrated circuits comprises an initialized input-output port associated with each integrated circuit connected between a parallel bus and a serial link. Each port uses two clocks with different frequencies, a first higher-frequency clock for the serial link, called a transmitting clock, and a second lower-frequency clock for the signals arriving from the parallel bus, called a system clock. The process comprises the following steps: reinitializing the port with isolation of the receiving clock logic; reinitializing the transmitting clock logic; resetting the serial link between two ports; and initializing a two-way serial link by a looped process, either automatic or dependent on a microprocessor.

Abstract: An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead.

Abstract: A mixed-signal processor (MSP) chip with a flexible serial interface which simultaneously accommodates two serial ports on a reduced number of pins. The pin definitions of these serial ports are configured to function well with several different external chips. Any two of these chips, or two of any one of these chips, may be used concurrently by the present MSP. When used with chips that require it, the present MSP chip provides a clock signal to each of these. When used with other chips, the MSP will can receive a clock signal from an external chip, and will then pass this signal through to any chip on the other of the two serial ports.

Abstract: A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

Abstract: A method of transferring image data between an initiator device and a target device using a IEEE 1394 standard bus. The present invention combines management functions, command functions, and isochronous data transfer to achieve the transfer of image data. The present invention discovers a target configuration using IEEE 1394 reads of a target configuration read only memory space. As part of the management function, the present invention uses a modified asynchronous data transfer protocol to establish a connection between the initiator and the target. Next, the present invention uses command functions to begin a job to transfer image data over an isochronous channel. Also, the present invention uses asynchronous data transfer to exchange printer job language commands to end a job.

Abstract: The synchronous serial bus between a main processing unit and a peripheral unit includes a data line and a clock line. Strobe pulses presented by the main processing unit on the data line while it holds the clock line at a given logic level characterise transfer cycles on the bus. The main processing unit can thus run write or read cycles in registers of an interface of the peripheral unit. A direct transfer mode, wherein the strobe pulse is transmitted at the beginning of the cycle without specifying an address, is provided to enable the main processing unit to have a fast access to certain locations previously specified. The data and clock lines of the bus may be shared with those of another synchronous bus.

Abstract: A synchronous DMA burst transfer method is provided for transferring data between a host device and a peripheral drive device connected by an ATA bus. The method provides synchronous data transfer capability in an asynchronous system by having one device in charge of both a strobe signal and a data signal. When a host read or write command is delivered to the peripheral drive device, the peripheral device decides when to start the synchronous DMA burst. For a read command, the peripheral device requests the synchronous DMA burst then drives a data word onto the ATA bus after the host acknowledges that it is ready to begin the burst. After allowing time for the data signal to settle, the peripheral device toggles a strobe signal from a high state to a low state. The host sees the edge of the strobe signal at which time the host latches the data word on the bus. Additional data words can be driven on the bus and the strobe signal can be retoggled to latch the additional data words into the host.

Abstract: A data transfer engine, method and article of manufacture are provided for use in a functional unit of an integrated system for enhanced access and transfer of data over a shared data bus. The data transfer technique comprises pipelining data transfer requests onto the shared bus. The technique involves receiving and storing a first transfer parameter set in a primary parameter register within the data transfer structure, and receiving and storing a second transfer parameter set in a secondary parameter register within the transfer structure. Thereafter, data is transferred using the shared memory bus in response to the first transfer parameter set and the second transfer parameter set without relinquishing access to the shared memory bus between transferring of data in response to the different parameter sets.

Abstract: An integrated circuit includes a central processing unit, a memory controller circuit for interfacing to system memory, and an interconnect bus controller for interfacing to an interconnect bus. The interconnect bus controller gives priority to transfer of asynchronous data during a first transfer mode and priority to transfer of isochronous data during a second transfer mode. A switch selectively couples the CPU, the memory controller circuit and the interconnect bus controller.

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

Abstract: Enhanced is a data processing efficiency of a whole semiconductor integrated circuit. A multiplexer is provided on a main parallel data bus for transferring data between an internal device such as a CPU, a DRAM or the like and an external device. When the CPU cannot accept data from the external device, it sends a busy signal to an interface circuit. The interface circuit receives the busy signal and controls the multiplexer in such a manner that the data to be transmitted to the CPU are transferred to the DRAM. Thus, a data transfer rate of the semiconductor integrated circuit is enhanced.

Abstract: A transmit packet buffer device capable of asynchronous read and write functions is used for receiving frame data from a host and forwarding the data over a network. The device comprises dual-ported memory capable of independent write and read access, a plurality of registers for storing address pointers to locations in the memory, and a logic device coupled to the dual-ported memory and the plurality of registers for controlling downloading data into the memory at a first clock speed, and transmitting data from the memory at a second clock speed. The registers are used to store memory addresses for reference by the logic device, and the data is divided into frames.

Abstract: A method of operation of a synchronous memory device having at least one memory section which includes a plurality of memory locations. The method comprises receiving an external clock signal having a fixed frequency, receiving a read request, including addressing information, synchronously with respect to the external clock signal, initiating an internal memory addressing operation, in response to the read request, and outputting data onto the external bus synchronously with respect to the external clock signal. The synchronous memory device may include interface circuitry, coupled to an external bus, to receive a write request packet synchronously with respect to an external clock. The write request packet may include N bits of information and the external bus includes M number of signal lines wherein N is substantially greater than M.

Abstract: An architecture for the isochronous transfer of information within a computer system in which a first isochronous stream of information is transferred, and asynchronous information is transferred independently from the transfer of the first stream. A translation is performed between the first stream and a second isochronous stream of information, and the second stream transfers information at a rate substantially the same as the rate at which the first stream transfers information. The second stream and the asynchronous information are concurrently transferred. In another embodiment of the present invention, a first isochronous stream of information is transferred, and the first stream is divided into a plurality of first service periods. Each first service period has a first duration and contains a first amount of information. A second isochronous stream of information is transferred independently from the transfer of the first stream.

Abstract: An apparatus includes a game port interface and a bus. The game port interface includes first and second game port portions. The first game port portion is on a first integrated circuit and interfaces to an I/O bus. The second game port portion is on a second integrated circuit and provides I/O terminals to couple the game port interface to a peripheral device. The bus couples the first and second integrated circuits. The bus is for serially transferring game port information between the first and second game port portions.

Abstract: An architecture is provided for isochronous access to memory in a system in which a stream of information may be sent to a memory unit. The stream is divided into a plurality of service periods with a specified maximum amount of information in selected service periods, and selected service periods have a first amount of information associated with asynchronous information and a second amount of information associated with isochronous information. In addition to sending a stream of information, a request for isochronous information from the memory unit may be sent. In this case, a stream of the requested information may be received from a memory unit a predetermined number of service periods after the sending of the request.

Abstract: A clock crossing FIFO capable of functioning regardless of relative clock frequencies on the write and read sides. Toggle signals are utilized to cross the clock boundaries. The number of write counts which have been accrued but not acknowledged by the read side are tracked, and this number is stored as of the issuance of a write toggle. Upon toggle receipt on the read side, this number is latched as a measure of the number of data units which can be read from the FIFO. At the same time, the toggle is returned to the write side for decrementing the number of write counts outstanding by the number conveyed to the read side. Similar circuitry is employed for conveying to the write side circuitry the number of data units which have been read by the read side circuitry. The presently disclosed FIFO and associated circuitry operates independent of relative clock speeds, and the particular size of the FIFO is scalable.

Abstract: A method and apparatus of a synchronizer circuit for transferring signals between two clock domains in which a first synchronizer unit and a second synchronizer unit form a hand-shaking protocol. In particular, an input event from a source clock domain is captured in an input unit and a first signal is asserted indicating that the input signal is to be transferred to a target clock domain. This first signal is synchronized to the clock signal in the target clock domain at the first synchronizer unit, causing assertion of a second signal. The second signal is coupled to an output unit which generates an output event signal for a single clock period.

Abstract: A system for processing audio samples, which compensates for any error between a future state of the system after a delay through a network and the predicted value of the input at that future time. The system synchronizes the motion of an audio transport to the motion of an audio input which has been delayed in processing through the network.

Abstract: A method of operating a synchronous memory device, wherein the memory device includes a plurality of memory cells and a register for storing an identification value which identifies the memory device on a bus. Block size information is provided to the memory device, wherein the block size information specifies an amount of data to be output onto a bus in response to a read request. The read request is issued to the memory device, and includes identification information, wherein in response to the read request, the memory device determines whether the identification information corresponds to the identification value stored in the register. When the identification information corresponds to the identification value, the memory device outputs an amount of data corresponding to the block size information onto the bus synchronously with respect to at least a first external clock. The memory device may further include a programmable register.

Abstract: An apparatus for processing transfer data to be transferred in synchronism with one of an external write signal and an external read signal, includes a plurality of memories for storing the transfer data. A plurality of sync signal generators are provided in association with the memories, to generate one of a sync write signal and a sync read signal, which determine write and read timings for the memories, in response to one of the external write signal and the external read signal and an internal clock having a longer period than the one of said external write signal and the external read signal. A distribution circuit is connected to the plurality of sync signal generators, for receiving one of the external write signal and the external read signal and sequentially distributing the one of the external write signal and the external read signal to the sync signal generators.

Abstract: A time authority is established within a trusted time authority hierarchy which is periodically updated with the current date and time by the time authority. The user trusts the time authority and the associated hierarchy. Servers in the chain of the established authority are authorized to stamp a message with the time and date and encode the message so the recipient knows whether the message has been tampered with since the date stamp was attached. Existing browser security features are used to provide the tamper-proof mechanism. Messages are sent to trusted outgoing mail servers and are time stamped, encoded with the time authority's digital signature for tamper protection, and are also encrypted according to the user's preferences. The message is then routed to the intended recipient whose mail reader receives the message, decodes the time authority's digital signature for tamper detection, and decrypts the message if it has been encrypted.

Abstract: Many digital processors have an asynchronous bus controlled by two control signals. To interface a synchronous memory to an asynchronous bus, interface logic is required. In an interface for transferring data from an asynchronous circuit to a synchronous circuit, data to be written are written in an intermediate register while timing control signals are being synchronized to a system clock by means of flip-flops. Correspondingly, in an interface for transferring data from the synchronous circuit to the asynchronous circuit, a signal indicating a read transaction from the synchronous circuit is synchronized to the system clock by means of a flip-flop circuit.

Abstract: The present invention is directed to a synchronous memory device having a memory cell array divided into a plurality of subarrays, including first and second subarrays each having a plurality of subarray sections. The memory device further includes a device identification register to store an identification code to identify the memory device. A first subarray section in the memory device includes a first internal I/O line to access data from a first memory cell location in the first subarray section and a second internal I/O line to access data from a second memory cell location in the first subarray section. A second subarray section in the memory device includes a first internal I/O line to access data from a third memory cell location in the second subarray section and a second internal I/O line to access data from a fourth memory cell location in the second subarray section.

Abstract: An improved transceiver pair that are tightly integrated into a computer system. The transceiver pair include a base transceiver and a remote transceiver, with a high speed serial connection between them. The base transceiver has a base transmitter with a parallel input port for accepting parallel, encoded data and a serial output port for transmitting a serial, encoded data stream. The remote transceiver has a receiver with a serial input port for receiving the serial, encoded data stream and an audio/video output port for passing deserialized data to an audio and video control unit after decoding. The high speed serial connection links the base serial output port to the remote serial input port. The remote receiver further includes a feedback input port adapted for receiving feedback data forwarded from a sensor. The sensor may respond to palpable, optical or sonic input or to physical contact.

Abstract: A transmitting device and a receiving device are interconnected through two transmission paths, i.e. a data signal line for transmitting serial data, and a delimiting signal line for transmitting a delimiting signal. The delimiting signal causes the receiving device to recognize breaks between bits when the consecutive bits of the transmitted serial data have the same value. The level of the delimiting signal remains unchanged in the event of a change in the logical value of consecutive bits of the transmit data. The level of the delimiting signal is changed when consecutive bits of the transmit data have the same value. The receiving end, receiving the data signal and delimiting signal, reads as digital data the logical value of each bit in the data signal by regarding a point of time of a level change in either one of the data signal and delimiting signal as a break between bits.

Abstract: A data processing apparatus includes control circuitry (15, 73) connectable to a peripheral device (17) for performing an access of the peripheral device, and data processing circuitry (13) connected to the control circuitry. The control circuitry includes synchronizing circuitry (29, 77) for synchronizing the control circuitry with the data processing circuitry after completion of the peripheral access.

Abstract: In a microcontroller, a synchronous serial port is coupled to a DMA unit such that a series of DMA writes to the synchronous serial port can be followed by a series of DMA reads from the synchronous serial port, all without intervention or the execution of the microcontroller.

Abstract: Processing streaming data on demand in a computer system. A service cycle is divided into a first plurality of input/output (I/O) phases for a second plurality of streams of real-time data. For each of the first plurality of I/O phases, a disk job, if any, is scheduled for one of the second plurality of streams of real-time data, and a second plurality of network jobs, each of the disk jobs corresponding with each of the second plurality of streams of real-time data.

Abstract: A disk drive array controller and method carries out disk drive data transfers not only concurrently but also synchronously with respect to all of the drives in the array. For synchronous operation, only a single-channel DMA is required to manage the buffer memory. A single, common strobe is coupled to all of the drives for synchronous read and write operations, thereby reducing controller complexity and pin count. A ring-structure drive data bus together with double suffering techniques allows use of a single, common shift clock instead of a series of staggered strobes a required in prior art for multiplexing/demultiplexing buffer memory data, again providing for reduced controller complexity and pin count in a preferred integrated circuit embodiment of the new disk array controller. Methods and circuitry also are disclosed for generating and storing redundant data (e.g. "check" or parity date) "on the fly" during a write operation to a RAID array.

Abstract: An apparatus for synchronizing operator commands with a failover process in a distributed system having a control workstation and a plurality of nodes. One of the nodes of the distributed system is designated a primary node and one of the nodes is designated a backup node. The backup node includes a backup daemon for performing a failover process if the primary node fails such that the backup node becomes the primary node. Shell scripts send a command string to be synchronized with the operation of the backup daemon from the control workstation to the backup node. The backup daemon is then checked to determine if the backup daemon is sleeping, and, in the event the backup daemon is sleeping, commands derived from the command string are enqueued in a work queue for processing by the backup daemon. The backup daemon is then awakened such that the derived commands in the work queue are processed.

Abstract: A rotating disk data storage device havIng a buffer in the form of a semiconductor memory for temporarily storing data supplied from a host computer prior to transfer to a disk drive. For most efficient data transfer from buffer to disk, the storage device has a microprocessor controller which is preprogrammed to compute the average, or weighted average, of the time intervals at which at least three, preferably eight, latest consecutive data blocks are delivered from the host, the average being updated with the reception of each new data block from the host. The data is transferred from buffer to disk at time intervals each determined by multiplying the latest average time interval by a preselected coefficient. Data transfer from buffer to disk also occurs when the time interval between any two consecutive data blocks exceeds a predetermined limit, or when the amount of data stored in the temporary memory exceeds a predetermined limit.

Abstract: In a synchronous serial transfer apparatus, the number of lines which are necessary for a serial transfer is reduced, and even when a master/slave operation is to be performed, a serial transfer is possible between any communication apparatuses without using communication apparatuses which have different structures from each other such as a master and slave apparatuses and without using a master apparatus. Communication apparatuses (TR1 to TR3) are connected parallel to each other by one communication line (TRL). A potential fixing apparatus (VC), which fixes a potential on the communication line (TRL) to "High" or "Low" when outputs from all communication apparatuses (TR1 to TR3) are in a "High-Z" state, is connected to the communication line (TRL).

Abstract: A data transfer system includes a host which provides a timing signal and data at an output, and a peripheral device which receives the timing signal and data from the host output, and produces an internal timing signal based on detection of a change in either the data or the polarity of the timing signal provided by the host.

Abstract: The present invention is directed to an integrated circuit device having at least one memory section including a plurality of memory cells. The device includes an internal register to store an identification value which identifies the device on a bus. The device further includes interface circuitry, coupled to the bus, to receive identification information and a read request. The interface circuitry includes a plurality of output drivers and comparison circuitry. The output drivers are coupled to the bus to output data on the bus in response to the read request. The data is output synchronously with respect to first and second external clock signals when the comparison circuitry determines the identification information corresponds to the identification value.