Abstract: The present invention is directed to an interface. In an aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end device is coupled to the bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data. The data transfer interface includes an inbound data transfer interface suitable for transferring data and an outbound data transfer interface suitable for transferring data. The inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously.

Abstract: An arbitration circuit adjusts timings of a write request signal from a first external device and a read request signal from a second external device. An RAM performs data write/data read in response to the external write request/read request. A next-state function is provided, which has a function to calculate a write address/read address to be input to the RAM in response to the external write request/read request, and a function to accurately count data stored in a FIFO.

Abstract: A method and a device for controlling data transmission between IDE apparatuses allow an IDE controller of an IDE control device to send read control signal to an IDE apparatus via a set of IDE interfaces and a signal control transmission line and then to send write control signal to another IDE apparatus via another set of IDE interfaces and another signal control transmission line. Thus, the output data from the IDE apparatus through the data transmission line can be accelerated the transmission speed thereof between IDE apparatuses so as to save the time for transmitting data.

Abstract: A sensor concentrating system centralizes communication between multiple parameter sensing devices and an application host. As a peripheral device, the sensor concentrating unit establishes a temporal correspondence between range data acquired from multiple optical range sensors with position data acquired from a shaft encoder. The parameter data are read and sampled according to a user specified criteria such as the time division multiplexing technique. The sampled data is correlated with a data tag generated by the sensor concentrating unit. The correlated data is packeted transmitted from the sensor concentrating unit to a downstream application host for subsequent analysis. The sensor concentrating unit also provides operating parameters for individual parameter sensing devices.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.

Abstract: A flip-flop circuit with embedded scan capabilities uses a skewed latch to pull one end of the flip-flop either up or down while another end of the flip-flop is active. Further, the flip-flop is designed such that a data node and a scan node are coupled to a master stage, which contains the skewed latch. The data node and scan node values are initially generated from different ends of the flip-flop. Based upon clock dependencies and whether the flip-flop is in a normal mode or a scan mode, the master stage passes a value to a slave stage dependent upon the data node and scan node values. Thereafter, the slave stage outputs a result based on the value passed from the master stage.

Abstract: The present invention comprises a dual bank FIFO memory buffer operable to buffer read data from memory and thereby compensate for specific timing problems in certain computerized systems. One embodiment of the invention includes a dual bank FIFO that comprises a first bank of memory elements operable to buffer memory data and a second bank of memory elements operable to buffer memory data. Write control address logic is operable to store selected memory data in memory elements with selected addresses within a bank of memory elements, and write control timing logic is operable to selectively grant write access to the banks of memory elements at predetermined time. Also, read control logic operable to read data stored in the first and second banks.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. In one embodiment a non-volatile synchronous memory device includes an array of memory cells arranged in a plurality of addressable banks. A bank buffer circuit is coupled to each of the banks. Each of the buffers can store data from a row of memory cells contained in a corresponding bank. A method of operating a synchronous flash memory includes storing instruction code in each array block and copying the instruction code from a first array block to a buffer circuit, during a write operation, so that the instruction code can be read from the buffer circuit during the write operation.

Abstract: A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.

Abstract: A timer apparatus which can simultaneously control the operations of a plurality of timers without adjusting the operation of a counter of each timer in a software manner is provided. The same address information is added to an operation command to the counter of each timer (20, 30, 40, . . . , 90), so the operation commands to the counters are simultaneously written into registers synchronously with a clock. Thus, the timing to start or stop the operations of the counters of the timers (20, 30, 40, . . . , 90) can be made to coincide.

Abstract: Embodiments of the invention provide a multi-chip system that includes a first and a second semiconductor memory device. The memory devices are mounted in a single package. The multi-chip system has a continuous burst read mode of operation, in which a read operation can be successively carried out without latency even though an address region moves from the first semiconductor memory device to the second memory device.

Abstract: A system and method for transmitting parallel data from a source to a destination over a plurality of high speed serial lines operates reliably even in the presence of data skew. The high speed data transmission system includes a protocol generator, a de-skew circuit, and a plurality of high speed serial lines coupled between the protocol generator and the de-skew circuit. Respective serial representations of parallel data words are transmitted to the destination over a plurality of serial data lines, and a clock signal is transmitted to the destination over a clock line in parallel with the serial data lines. The clock signal has at least one data bit of each parallel data word encoded thereon. The de-skew circuit aligns regenerated parallel data words using the respective data bits encoded on the clock signal to eliminate skew among the data bits, and regenerates the parallel data from the aligned parallel data words.

Abstract: A system transfers a data stream including data packets separated by non-packet words from a first clock domain to a second clock domain. It includes an elasticity buffer into which the data stream is written in a cyclic sequence under the control of the clock frequency in the first clock domain and from which the data stream is read out in a cyclic sequence under the control of the clock frequency in the second domain. The two sequences are monitored to provide an anticipatory signal indicating that the reading sequence approaches proximity to the writing sequence. A non-packet word is inserted into the data stream in the first domain. In the second clock domain the existence of the inserted non-packet word is detected and the buffer is caused to advance the reading cycle thereby to discard the said inserted non-packet word.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. In one embodiment a non-volatile synchronous memory device includes an array of memory cells arranged in a plurality of addressable banks. A bank buffer circuit is coupled to each of the banks. Each of the buffers can store data from a row of memory cells contained in a corresponding bank. A method of operating a synchronous flash memory includes storing instruction code in each array block and copying the instruction code from a first array block to a buffer circuit, during a write operation, so that the instruction code can be read from the buffer circuit during the write operation.

Abstract: One or more queues store data information such as packets or data flows for later transmission to downstream communication devices. A real-time clock tracks current time and an advancement of a moving time reference, which is displaced with respect to the current time of the clock by an offset value. Thus, as current time advances, the moving time reference also advances in time. Upon servicing a queue, a time stamp associated with the serviced queue is also advanced in time. To monitor a rate of outputting data from the one or more queues, a processor device at least occasionally adjusts the offset value so that the moving time reference and values of the time stamps advance in relation to each other. Consequently, by tracking a relative time difference between current time of the real-time clock and a relative advancement of time stamps, a rate of outputting data information from the queue is monitored over time.

Abstract: A latency-independent interface between hardware components, such as a hard disk controller (HDC) and a read/write (R/W) channel or a read channel (RDC) supports high read and write latencies of greater than one sector. Such an interface also supports a split sector format and multiple mark format. In addition to read and write clock signals, the interface comprises a data gate signal that controls the transfer of data between the the HDC and R/W channel, and a media gate signal that controls transfer of mode selection information from the HDC to the R/W channel and also controls the transfer of data between the R/W channel and a disk. The media. gate signal replaces the conventional read and write gate control signals. A buffer attention signal is also provided.

Abstract: A memory card cooperating with a network interface for receiving data entry and update signals from a database manager via a switch fabric and with a bus interface for outputting data on a system bus disposed in a system shelf, which shelf forms at least a portion of a telecommunications node having a distributed scalable database system. The memory card is operable to contain at least a portion of the distributed database in a high speed, high density memory block disposed thereon, which memory block is coupled to a network interface controller via a first memory interface and to a bus interface controller via a second memory interface. An arbiter is coupled to the first and second memory interfaces for arbitrating data input operations and data output operations with respect to the memory block.

Abstract: A device for interfacing asynchronous data, and more particularly, a device for interfacing asynchronous data using a first-in-first-out (FIFO) for preventing cutoff in data transfer by transferring the asynchronous data in accordance with a data transfer information signal while best satisfying a transfer request from a host between two devices that transfer the bi-directional asynchronous data. The provided device prevents control problems caused by the asynchronous data, so that the selected data is precisely and stably transferred even if the transfer speed is increased to equal that of an inner system clock. In addition, the output speed of a flag signal is faster than that of an existing method in which read and write addresses are compared, so that the remaining amount of data in the FIFO is precisely measured. As a result, asynchronous data is stably interfaced at a high speed.

Abstract: The immediate grant bus arbiter of this invention is a part in the implementation of a multiple transaction bus system. A bus bridge provides a means to connect two separate busses together and secure data integrity. The bus bridge is defined with clear master-slave protocol. The bus bridge normally involves the use of two arbiters. The arbiter on the primary bus needs to operate differently from the arbiter on the secondary bus due to real system time constraints. This invention defines a bus arbiter that allows for a dominant bus master to receive an immediate grant of control on the bus. This immediate grant bus arbiter never relinquishes the bus if another lower priority master makes a bus request. This makes predictable real time data transfer possible.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.

Abstract: A data collision detector receives a reflection of a signal from a network and compares the reflection to a representation of a previously stored reflection. Based on the comparison, the data collision detector generates an indication as to whether or not a data collision has occurred.

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

Abstract: A method and device for the exchange of data in messages between at least two users which are connected by a bus system and have separate time bases, the messages containing the data being transmitted by the users via the bus system; and a first user, in a function as timer, controls the messages as a function of time in such a way that it repeatedly transmits a reference message, which contains time information regarding the time base of the first user, via the bus at a specifiable time interval; the at least second user forms its own time information, using its time base, as a function of the time information of the first user; a correction value is ascertained from the two pieces of time information; and the second user adapts its time information and/or its time base as a function of the correction value.

Abstract: A system and method for performing data transfers within a computer system is provided The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.

Abstract: The device and method that receives a signal from a first interface operating at a data rate. An extraction component extracts information from the signal to produce an information signal having a frequency distinct from the data rate of the first interface. A first receive clock component receives a first clock signal that has a frequency equal to a frequency of a second interface. A synchronizer component synchronizes the information signal through utilization of the first clock signal to the frequency of the second interface.

Abstract: A robust state machine is provided for controlling a slave interface to an I2C-bus. The state machine is configured to enforce the slave-device-protocol of the I2C specification, and to provide recovery from anomalous master-device behavior. In accordance with this invention, the state transitions of the state machine at the slave-device are controlled by the master-device's control of the SCL line of the I2C-bus, except if a START condition is detected. The state machine is configured to asynchronously respond to a START condition on the I2C-bus, regardless of its current state, to force the state machine to a known state. In the known state following the START condition, the slave-device terminates any transmissions to the I2C-bus, thereby minimizing subsequent interference on the bus.

Abstract: In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.

Abstract: A CPU system employs a general-purpose peripheral LSI circuit and a high-speed memory for the peripheral LSI circuit. A selector determines whether access from a CPU is directed to an internal circuit of the peripheral LSI circuit or an SDRAM. If the access is directed to the SDRAM, the selector stores a bus signal in a timing adjusting circuit and then reads the stored bus signal at a rate that is at least twice the rate at which the bus signal has been stored. An SDRAM interface accesses the SDRAM with the read bus signal. The internal circuit accesses the SDRAM while bus arbitration is being carried out between the internal circuit and the SDRAM interface.

Abstract: A USB device centric agent is associated with an operating system. The agent software is only required to be loaded once and then it will function with multiple compatible USB devices. A standard interface is established between the device agent and any compatible USB device. This enables any compatible USB device to control the agent which in turn controls the host computer. This is opposite the standard practice where the host controls the USB device.

Abstract: A method and system for browsing a distributed database. Storage is allocated in a computer for a file, wherein the file is used for storing references to data in the distributed database for retrieval at a later time. A reference to data in the distributed database is added to the file in response to a user input from a user using the computer to browse the distributed database. The data is retrieved from the distributed database using references to the data stored within the file in response to a selected event.

Abstract: A computer system has a communication link that includes a control signal and data lines. A first control packet having a-plurality of bytes is transferred over the data lines from a first to a second node on the communication link. The control line is asserted to indicate transfer of a control packet. After transfer of the first control packet, a first portion of a multi-byte data packet associated with the first control packet is transferred with the control line deasserted. During transfer of the data packet the control line is asserted and transfer of the data packet is suspended. A second control packet is then transferred over the data lines. Subsequent to transferring the second control packet, the remainder of the data packet is transferred with the control line deasserted.

Abstract: Memory modules and a controller are arranged and two clock lines are provided to go and return along the arrangement of the memory modules and the controller. A first basic clock and a second basic clock having twice the cycle period of the first basic clock are transferred over the go portions of the respective clock lines to the memory modules and the controller. After passing through the turnaround point, the first and second basic clocks are transferred as return clocks over the return portions of the clock lines to the memory modules and the controller. The first and second basic go clocks and the first and second basic return clocks are fed into the memory modules and the controller. The input/output operation of data is controlled synchronously with these clocks.

Abstract: A method and system for adjusting the bandwidth allocated for isochronous data traffic on an interconnected data bus is disclosed. The present system uses an isochronous resource manager (IRM) to sense a bandwidth change request from a talker. The IRM instigates a bandwidth adjustment associated with the bandwidth change request to one or more bus bridge portals.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data storage registers on the data communication connections during a predetermined number of consecutive clock cycles by adjusting a burst length of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Abstract: A memory control unit has been developed. The control unit includes a command “spin wheel” which schedules the order of read and write commands to the memory. It also includes a read “spin wheel” which ensures proper timing of the read commands and a write “spin wheel” which ensures proper timing of the write commands.

Abstract: A method and system for managing I/O resources for communications between a host and a target device through at least one adapter, involves setting a local resource associated with each adapter. If a target device cannot accept an I/O request, the local resource associated with each adapter is set to the number of I/O resources currently used by each adapter associated therewith. The host is configured to issue no more than the local resource number of I/O requests to any individual adapter. The local resources may be periodically rebalanced to account for changes in system needs.

Abstract: A data processing apparatus and a data processing method easily realizable of a transparent processing of a high-speed serial data. The data processing apparatus (1) including a serial data conversion section for converting serial data to predetermined set of parallel data; a transparent data information detection section (10) for detecting information concerning transparent data, from the parallel data; an effective byte number operation section for operating an effective byte number of the parallel data; a transparent data conversion section (20) for converting transparent data of the parallel data, and moving predetermined data after the transparent data forward, in the parallel data; an address control section (304) for determining addresses at which the parallel data are rearranged; and a data array section (30) for moving predetermined data to one predetermined set of parallel data from another predetermined set of parallel data.

Abstract: A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing node's memory, wherein the non-coherent write transaction is a posted write transaction.

Abstract: A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a memory array. In addition, the multiple transfers are performed during one bus cycle and the number of transfers may be selectable. FIFO control circuitry limits the number of data elements transferred in response to the state of the memory array including almost empty or almost full.

Abstract: A method and system for increasing read and write performance of flash-based storage systems, by using RAM buffers with multiple accesses. The increase of read and write performance of flash-based storage system is achieved by performing “from RAM” and “to RAM” transfer operations simultaneously. According to the preferred embodiment of the present invention, the invention provides a system for enabling simultaneous data transfer from a host interface to flash media and from flash media to a host interface. It also provides for a system for synchronizing memory-to-host and flash-to-memory transfers, during the host read operation. There is further provided a system of synchronizing host-to-memory and memory-to-flash transfers, during the host write operation.

Abstract: The present invention provides for a dual sequencer for use in a peripheral storage device system, as well as a new protocol for data retrieval/storage in peripheral storage device systems. The system provides for more efficient media storage/retrieval and addresses the issue of channel latencies in media storage/retrieval systems.

Abstract: The data processor 1 converts the serial data in the STM-16 to parallel data that is based on four bytes (32 bits). The transparence data detector 20 detects the position of the data (transparence data) as a candidate for transparence processing in the parallel data and the transparence data sampling section 30 converts the transparence data based on the detected position and rearranges the processed data in each parallel data block (hereinafter referred to as a block). then, the data arrangement section 40 sequentially inserts empty byte data in each block to the preceding block to rearrange parallel data. Thus, the data processor 1 can perform transparence processing easily via a relatively low-speed general-purpose device.

Abstract: Techniques for converting input data from a multiplicity of sources that are mutually asynchronous, to a single, common synchronous format for local processing by an information processor. Logical operations are described which control first-in-first-out (“FIFO”) buffers to align all inputs to a predetermined point in the data flow or processing sequence, and which maintain clock-by-clock alignment of the input data sequences for an indefinite period of time thereafter.

Abstract: A system and method for transferring a data stream between devices having different clock domains. The method initiates a serial data stream between a transmitter and a receiver. The transmitter operates according to a first clock having a first clock rate, and the receiver operates according to a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. A first state is provided over a serial line between the transmitter and the receiver One or more start bits are provided over the serial line. The start bits indicate a second state different from the first state. One or more ratio bits are provided over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The start bits are received. Using a transition between the first state and the second state evident in receiving each of the start bits, the ratio bits are received.

Abstract: An improved modem architecture and associated method are disclosed that integrate modem functionality and line-side isolation functionality while also providing a modem interface that allows command and data mode control.

Abstract: A tracking bin split technique includes: receiving an externally generated board clock and selectively generating a reference clock in phase with the externally generated board clock at a frequency equal to that of the externally generated board clock multiplied by M, wherein M is an integer equal to or greater than one; receiving the reference clock output by the clock generator and generating an output clock with a phase locked loop in phase with the reference clock and having a frequency which is an integral multiple of that of the reference clock; and receiving the output clock generated by the phase locked loop and generating a feedback clock for the phase locked loop in phase with the output clock and at a frequency equal to that of the output clock divided by 2N, wherein 2N is an even integer equal to or greater than two.

Abstract: Systems and methods for enabling data transfers over communications links having a plurality of lanes, wherein the lanes may have different transmission lengths (times.) In one embodiment, a plurality of buffers are each coupled to corresponding transmission lanes in a communications link. Each buffer is configured to reset corresponding read and write pointers to predetermined initial positions after a reset event. The pointers are kept in these positions until a test sequence symbol which is transmitted across the corresponding lane is received. When the test sequence symbol is received, the buffer begins to advance the associated write pointer with each received piece of data. After all of the buffers have received corresponding test sequence symbols, data is read out of the buffers, and the read pointers are advanced accordingly.

Abstract: Incoming serial data which is received M bits at a time where M=N, N+1 or N−1 and N is greater than 1 is synchronized to a local clock by receiving a first M bits of data, storing the first M bits, receiving M additional bits, storing the M additional bits, repetitively receiving and storing until at least a predetermined number R of bits have been stored, where R=(M*X)+1 where X is an integer greater than one. When this occurs, the first R bits are output and any remaining S bits in excess of R are stored and additional groups of M bits added, with the process continuing until all of a packet has been received. With this arrangement, the R bits may be output at a rate which is a fraction of the serial bit rate.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: A clock module operates in conjunction with the generation of the bus-clock signal to provide a combination of module-clocks that can be relied upon to provide an adequate safety margin for data transfers among processing modules at the speed of the bus-clock. In a preferred embodiment, a system-clock generates the bus-clock and a sample-clock, the sample-clock having a predetermined phase relationship with respect to the bus-clock. Base-clocks at each of the frequencies required for each processing module are generated in the conventional manner, and, in accordance with this invention, are sampled by the sample-clock to produce sampled module-clocks that are provided to each corresponding processing module. By sampling each base-clock with a sample-clock that has a corresponding predetermined phase relationship with respect to the bus-clock, each module-clock will have a predetermined phase relationship with respect to the bus-clock.