Width Conversion Patents (Class 710/66)
  • Patent number: 10846124
    Abstract: Embodiments of the present disclosure disclose a communication method, apparatus and system for a virtual machine and a host machine. An embodiment of the communication method for a virtual machine and a host machine includes: polling a first command completion identifier queue set in a shared memory; comparing, in response to detecting an update of the first command completion identifier queue, the first command completion identifier queue with a second command completion identifier queue stored in the virtual machine to determine an identifier of a currently completed command; and updating the second command completion identifier queue based on the identifier of the currently completed command.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 24, 2020
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Xun Ni, Yongji Xie, Yu Zhang
  • Patent number: 10769094
    Abstract: In example implementations, a method to change a data transfer configuration of a data cable is provided. The method includes receiving a selection of a data transfer configuration option from a plurality of different data transfer configuration options of a data cable that has data lanes to transfer video data and non-video data. A reported number of supported resolutions or refresh rates is modified in accordance with the data transfer configuration option that is selected. The reported number of supported resolutions or refresh rates that is modified is then transmitted to a computing device connected to a display device via the data cable to transmit data via the data cable in accordance with the data transfer configuration option that is selected.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: September 8, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: John W. Frederick, Tim Guynes, Wen-Shih Chen
  • Patent number: 10749672
    Abstract: A path for transmitting encrypted data is completely separated from a path for transmitting unencrypted data. To this end, a virtual secure memory is created on an address space. If a central processing unit (CPU) writes data in the virtual secure memory, hardware stores the data in a specific area of a dynamic random access memory (DRAM) after automatically encrypting the data. In the case where the CPU intents to read data, the hardware sends the data to the CPU after automatically decrypting the data read from a specific area of the DRAM.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heonsoo Lee, Jaechul Park, Jonghoon Shin, Youngjin Chung, Hong-Mook Choi
  • Patent number: 10733127
    Abstract: A data transmission apparatus that transmits transmission data from a first memory to a second memory through a communication channel, the first memory storing data in units of a first data block of a first data size, and the communication channel having a width of a second data size, includes: a storage that stores the transmission data read from the first memory; and a transmission controller that transmits the transmission data stored in the storage from the first memory to the second memory in units of an integral multiple of the second data size, such that data transmission from the first memory to the second memory is efficiently performed.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 4, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiko Suzuki, Shinya Miyata
  • Patent number: 10331579
    Abstract: A Universal Serial Bus (USB) system supporting Display Alternate Mode functionality on a USB Type-C adapter is disclosed. In one aspect, a display controller in a display source device can detect a display sink device attached to a display connector of a USB Type-C split adapter and communicate a display data signal to at least three preconfigured display data pins without negotiating a pin assignment with the attached display sink device. In another aspect, the display source device can provide the display data signal to the preconfigured display data pins independent of attachment of the display sink device. By skipping the pin assignment negotiation or providing the display data signal regardless of attachment of the display sink device, it is possible to support Alternate Modes functionality without requiring a Power Delivery (PD) circuit, thus helping to reduce cost, power consumption, and implementation complexity of the display source device.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Amit Gupta, Michael Leung
  • Patent number: 10062422
    Abstract: An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: August 28, 2018
    Assignee: Sonics, Inc.
    Inventors: Drew E. Wingard, Chien-Chun Chou, Stephen W. Hamilton, Ian Andrew Swarbrick, Vida Vakilotojar
  • Patent number: 9529878
    Abstract: A system and method can support master negotiation in a network environment. A subnet manager (SM) can perform subnet discovery on a subnet in the network environment via a subnet manager (SM) in the subnet, wherein the subnet includes a plurality of SMs. Furthermore, the SM can communicate with the other SMs in the subnet to check for a number of known secret keys, and select a SM from the plurality of SMs as a master SM, wherein the master SM has the highest number of known keys.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: December 27, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Bjørn Dag Johnsen, Line Holen, Dag Georg Moxnes
  • Patent number: 9348783
    Abstract: Apparatus and method emulating a parallel interface to effect parallel data transfer from serial flash memory are provided. A field-programmable gate array (FPGA) may be coupled to a processor via a data bus. A serial flash memory may be coupled to the FPGA via a serial interface. The FPGA may be programmed to emulate a parallel interface by converting a serial data stream of boot code or operating software received from the serial flash memory to a parallel data stream to effect parallel data transfer over the data bus to the processor. The FPGA may be responsive to respective logic signals set by the processor to start access to the serial flash memory by pointing to at least one predefined location corresponding to at least one starting address of data to be transferred to the processor without using a plurality of address lines to access the serial flash memory.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 24, 2016
    Assignee: LOCKHEED MARTIN CORPORATION
    Inventors: Linette L. Kelly, Carter Burks, Steven J. Melendez
  • Patent number: 9077469
    Abstract: The present invention discloses an adapting apparatus and method, the apparatus comprises: an adapter pool, wherein the adapter pool is located between an optical data unit (ODUk) layer and an optical channel (OCh) layer, and the adapter pool comprises one or more adapters which are respectively connected to an OCh layer link and an ODUK layer link; the information that the adapter pool used for managing comprises: information for indicating connectivity of the adapter with the OCh layer link and with the ODUk layer link, and information for indicating an adapter capability of the adapter. The adapting information between MRNs can be described more accurately through the present invention, and the correctness of the route calculation results is guaranteed.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: July 7, 2015
    Assignee: ZTE CORPORATION
    Inventor: Gang Xie
  • Patent number: 9021162
    Abstract: A data processing apparatus may include a data conversion unit for, when converting a plurality of sequentially input data into conversion data of the same bit number as a data bus having a prescribed bit number and sequentially transferring the conversion data. The data conversion unit may include a first data generation unit, a second data generation unit for generating second data obtained by allocating a prescribed second number of input data in the input data not allocated to the first data, to the second bit range and a data coupling unit for coupling the first data and the second data to generate the conversion data having the bit number of the bus width of the data bus.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 28, 2015
    Assignee: Olympus Corporation
    Inventors: Ryusuke Tsuchida, Akira Ueno, Masami Shimamura, Yoshinobu Tanaka, Takashi Yanada, Tomoyuki Sengoku
  • Patent number: 8984203
    Abstract: First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: March 17, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Baojing Liu, Matt Davidson, Aruna Gutta
  • Patent number: 8966145
    Abstract: A data processing apparatus may include: a data conversion unit configured to designate one-transfer data as one transfer unit and designate a predetermined number of transfer units as one conversion unit when a plurality of input data sequentially input is converted into transfer data of which the number of bits is the same as that of a data bus having a predetermined number of bits, and the transfer data is sequentially transferred, and arrange the input data in the transfer data within the conversion unit. The data conversion unit may include: a data generation unit, a first data arrangement change unit, and a first data selection unit configured to sequentially select the changed data in which the position of the input data is changed by the first data arrangement change unit and output the selected changed data as the transfer data in the data conversion unit.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: February 24, 2015
    Assignee: Olympus Corporation
    Inventors: Ryusuke Tsuchida, Akira Ueno, Masami Shimamura, Yoshinobu Tanaka, Takashi Yanada, Tomoyuki Sengoku
  • Patent number: 8806093
    Abstract: To address the need for efficient and reliable testing of integrated devices, system on chips, and computers, deterministic behavior for an interface is accomplished by fixing variation in latency associated with receiver and transmitter data stream. The interface may be a serial interface that is PCIe compliant and corrects latency variations in the receiver that consequently results in deterministic transmit data. Consequently, the data received and/or transmitted is predictable with respect to time and facilitates testing and validation of the devices and logic associated with the interface.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: August 12, 2014
    Assignee: Intel Corporation
    Inventors: Bibbin Chacko, Guadalupe J. Garcia, Saurabh Upadhyay
  • Publication number: 20140223044
    Abstract: Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.
    Type: Application
    Filed: April 4, 2014
    Publication date: August 7, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Harold B. Noyes
  • Patent number: 8769239
    Abstract: Systems and methods for re-mapping memory transactions are described. In an embodiment, a method includes receiving a memory request from a hardware subsystem to a memory, replacing a first identifier with a modified identifier in the memory request, and transmitting the memory request to the memory through a processor complex. The method further includes receiving a response from the memory, determining that the response corresponds to the memory request, replacing the modified identifier with the first identifier in the response, and transmitting the response to the hardware subsystem. In some embodiments, a system may be implemented as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 1, 2014
    Assignee: Apple Inc.
    Inventors: Deniz Balkan, Gurjeet S. Saund
  • Patent number: 8732363
    Abstract: A data processing apparatus may include a data conversion unit that arranges the input data in each transfer data in the conversion unit using one transfer data as one transfer unit and a predetermined number of transfer units as one conversion unit when converting a plurality of input data input sequentially into transfer data having a bit number identical to a predetermined bit number of a data bus and sequentially transferring the converted transfer data. The data conversion unit may include a data generation unit and a first data arrangement changing unit. The first data arrangement changing unit may include a bit change number calculating unit, a bit change number analysis unit, a first data sorting unit, and a data coupling unit.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: May 20, 2014
    Assignee: Olympus Corporation
    Inventors: Masami Shimamura, Akira Ueno, Yoshinobu Tanaka, Takashi Yanada, Ryusuke Tsuchida, Tomoyuki Sengoku
  • Patent number: 8719471
    Abstract: Apparatus and methods are provided for alleviating processing requirements of a central computer in a vessel. Each apparatus is placed in close proximity to one or more pieces of electronic equipment implementing a legacy interface. The apparatus processes data to and from the electronic equipment, including converting data to formats consistent with the formats used by the intended recipient.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: May 6, 2014
    Assignee: Advanced Fusion Technologies
    Inventors: James Fleming, David McKean
  • Patent number: 8713224
    Abstract: A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: April 29, 2014
    Assignee: Marvell International Ltd.
    Inventors: Theodore C. White, William W. Dennin, Angel G. Perozo
  • Patent number: 8713223
    Abstract: Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • Patent number: 8713239
    Abstract: A host controller is suitable for transferring data in transactions, each transaction being described by a transfer descriptor, and the transactions include split transactions. The transfer descriptor for a split transaction includes a bit which may be set to indicate whether the split transaction is a start split or a complete split transaction, and, once a transaction comprising split transactions has been started by a first split transaction, subsequent split transactions are generated automatically until the transaction is complete.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: April 29, 2014
    Assignee: NXP B.V.
    Inventors: Yeow Khai Chang, Weng Fei Moo
  • Patent number: 8706978
    Abstract: A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiyuki Tanaka
  • Patent number: 8706930
    Abstract: A KVM switch includes: a first input portion and a second input portion that inputs a plurality of video signals from the first and the second information processing apparatus, respectively; a converting portion that converts the video signals input from the first or second input portion into a plurality of pieces of image data which are capable of being displayed on a remote terminal; a transmitting and receiving portion that transmits the pieces of converted image data to the remote terminal, and receives various requests from the remote terminal; and a switching portion that switches the video signals input from the first input portion to the video signals input from the second input portion when the transmitting and receiving portion receives a switching request for switching from a first information processing apparatus to a second information processing apparatus from the remote terminal.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Component Limited
    Inventors: Kenichi Fujita, Yu Sato, Naoyuki Nagao
  • Patent number: 8683094
    Abstract: A method for enhancing data transmission efficiency in a data transmission system having a host, a subsystem and a transmission interface, utilized for the host to transmit and receive a data from a memory of the subsystem via the transmission interface includes steps of the host outputting a query command to the subsystem via the transmission interface for querying available memory utilization of the subsystem; the subsystem outputting a return message to the host via the transmission interface for indicating the available memory utilization according to the query command; and controlling data transmission from the host to the subsystem according to the return message.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: March 25, 2014
    Assignee: Ralink Technology, Corp.
    Inventors: Ching-Hwa Yu, Chen-Hai Yu
  • Patent number: 8677078
    Abstract: A device for managing multiple instructions to access multiple wide registers may include logic to receive the multiple instructions to access one of the multiple wide registers, associate each received instruction with a corresponding one of multiple buffer memories, and allow simultaneous processing of the multiple instructions associated with each of the multiple buffer memories, where the multiple instructions are processed such that data is transferred between the multiple buffer memories and the multiple wide registers in one operation.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: March 18, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Karthikeyan Veerabadran, David J. Ofelt
  • Patent number: 8615611
    Abstract: Devices and methods for communicating DisplayPort information and non-DisplayPort information over a DisplayPort cable are provided. In some embodiments, an integration device includes a main link switching circuit configured to selectively couple lanes of the DisplayPort main link to a DisplayPort source when configured to operate in a first mode, and to a non-DisplayPort source when configured to operate in a second mode. In some embodiments, the integration device may be configured to hot swap between the first mode and the second mode after an initial connection has been established.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 24, 2013
    Assignee: Icron Technologies Corporation
    Inventor: Aaron T. J. Hall
  • Patent number: 8601187
    Abstract: A serial interface circuit which can adapt to various frame formats to reduce the load on a CPU. The interface circuit includes a rewritable control register used for programmably specifying a field structure to be targeted for processing out of structures of fields preceding a data field of a frame as defined by a communication protocol. The interface circuit analyzes the field structure preceding the data field according to a setting of the control register. When a destination of a received frame is determined to match an expected value, the interface circuit issues a request for the CPU to process the data field information. After a setting is made on the control register, the serial interface circuit can adapt to various formats of frames as defined by a communication protocol according to the information held there, and can also analyze a destination.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: December 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshio Otashiro, Takuya Ikeguchi
  • Patent number: 8572424
    Abstract: A semiconductor device that can transmit data in wide bus width regardless of the width of an external data bus connected thereto. In a semiconductor device on the data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L(=m/n) bits. At this time an output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. In a semiconductor device on the data input side, a data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: October 29, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Miki Yanagawa
  • Patent number: 8572300
    Abstract: A physical coding sublayer includes a first channel configured to receive a first encoded data stream from a physical media attachment layer and to provide a first decoded data stream to a media access layer. The first channel includes a first circuit configured to detect synchronization headers in the first encoded data stream received from the physical media attachment layer, a decoding circuit configured to decode the encoded data stream and to adjust a width of the received data from a first width to a second width based on a signal identifying the synchronization headers received from the first circuit, and a first single configured to compensate for clock differences between the physical media attachment layer and the media access layer to which the first buffer provides the first decoded data stream.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chi Wu, Meng-Chin Tsai, Liang-Hung Chen, Jung-Chi Huang
  • Patent number: 8555053
    Abstract: Embodiments provide systems and methods for adjusting to drive specific criteria. Data blocks sent to a drive may be padded to a constant size over a period to ensure optimal drive performance. Systems for padding data blocks to a constant size over a period may include padding logic which may pad data blocks addressed to a drive to a constant size over a period. The padding logic may be contained in an appliance located upstream of the drive in a network. The appliance may be operable to intercept data blocks addressed to the drive over a period, pad the data blocks to a constant size and forward the data blocks to the drive such that the drive receives data blocks of a constant size over a period.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: October 8, 2013
    Assignee: Crossroads Systems, Inc.
    Inventors: Michael Joseph Vitalo, Michael Baines Gosha
  • Patent number: 8539133
    Abstract: An embedded system includes an ARM processor and a number of b-bit peripheral processors connected to the ARM processor through a converting chip. The ARM processor includes pins P0˜Pa-1 divided into teams T1˜TN, each of which includes b pins, a and b are integral multiple of 8, wherein a=N×b. The number of the peripheral processors is N and each team corresponds to one peripheral processor. The converting chip reads an a-bit data from the ARM processor, converts the data into a plurality of b-bit data, and transfers each b-bit data to a peripheral processor, where the number of the b-bit data is N. The converting chip further reads one b-bit data from each peripheral processor in sequence, converts the read plurality of b-bit data into an a-bit data, and transfers the a-bit data to the ARM processor.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: September 17, 2013
    Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Ren-Wen Huang
  • Patent number: 8527075
    Abstract: An apparatus and method for processing signals are disclosed. The apparatus may include an oversampling circuit configured to receive a plurality of audio signal samples, the oversampling circuit being further configured to replicate each of the audio signal samples n times, wherein n is variable.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: September 3, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: David Jonathan Julian, Harinath Garudadri, Somdeb Majumdar
  • Patent number: 8504745
    Abstract: A method of determining a shift pattern for generating an output data stream comprising output data words having a data width N from input data words having a data width M is disclosed. The method comprises receiving an input data stream comprising words having the data width M; determining a ratio based upon the data width N and the data width M; determining an initial shift value; generating subsequent shift values of the shift pattern based upon the initial shift value and the ratio based upon the data width N and the data width M, and transforming the input data stream to the output data stream by shifting input data words of the input data stream according to the shift pattern using a barrel shifter or a multiplexer network. A circuit for generating an output data stream comprising output data words having a width N from input data words having a width M is also disclosed.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: August 6, 2013
    Assignee: Xilinx, Inc.
    Inventors: Curtis L. Fischaber, Shaun R. Grosser
  • Patent number: 8463962
    Abstract: According to an example embodiment of the present invention, a method is implemented for transmitting data between a Media Access Control Layer (MAC) (100) and a Physical Layer (PHY) (150) using an internal data bus for transmitting a set of internal symbols between the MAC (100) and PHY (150). A subset of internal symbols does not have a corresponding PHY symbol. An external data bus carries data symbols. An external interface (102, 118) provides command information on one or more dedicated command lines and provides the data symbols. An encoder (108, 110) encodes the provided command information into one or more of the subset of internal symbols. An internal interface (106, 107, 109, 111) transmits the one or more of the subset of internal symbols and the data symbols between the MAC (100) and PHY (150) using the internal data bus.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: June 11, 2013
    Assignee: NXP B.V.
    Inventor: Sharad Murari
  • Patent number: 8452903
    Abstract: Embodiments disclosed herein provide for capability identification for accessories coupled with a mobile computing device. During capability identification an accessory can request capability information from a mobile computing device. In some embodiments, the accessory can specifically request capability information associated with a specific lingo. In response, the mobile computing device can respond with a message that indicates the capabilities of the mobile computing device that are supported. In some embodiments, the capabilities can be those capabilities associated with the specified lingo. In some embodiments, if the mobile computing device does not support a lingo, then the mobile computing device can respond to the request from the accessory with a negative acknowledgement.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: May 28, 2013
    Assignee: Apple Inc.
    Inventors: Lawrence G. Bolton, Shailesh Rathi, Sylvain R. Y. Louboutin
  • Patent number: 8443129
    Abstract: A data bus interface channel controller circuit for an N-bit data bus is described. A FIFO command queue is coupled to receive and buffer one or more commands formatted for M-bit transactions. A FIFO data queue is coupled to receive and buffer N-bit formatted data packets. A first translation circuit is coupled to the FIFO command queue and configured to translate the each commands into a selected one of a plurality of transaction formats. A transmission control circuit is coupled and configured to receive and transmit commands removed from the FIFO command queue. The transmission control circuit is configured to track a number of outstanding transmitted commands and, in response to receiving a command having a transaction format different from the previously received command, delay transmission of commands on the N-bit data bus until the number of outstanding transmitted commands equals zero.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: May 14, 2013
    Assignee: Xilinx, Inc.
    Inventors: James J. Murray, Ting Lu
  • Patent number: 8443124
    Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: May 14, 2013
    Assignee: Broadcom Corporation
    Inventors: Kevin T. Chan, Michael Q. Le
  • Patent number: 8433839
    Abstract: A connector assembly includes first to fifth connectors, two PCIe slots, and an adapter board. When the first connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at the pins of the third connector are transmitted to the second group of pins of the first PCIe slot through the fourth connector, the fifth connector, and the first connector in series. When the second connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at pins of the third connector are transmitted to the fourth group of pins of the second PCIe slot through the fourth connector, the fifth connector, and the second connector in series.
    Type: Grant
    Filed: October 16, 2011
    Date of Patent: April 30, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Zheng-Heng Sun
  • Patent number: 8407378
    Abstract: Several methods and a system to implement data compression inline with an eight byte data path are disclosed. In one embodiment, a method includes acquiring a data from a host. In addition, the method includes applying an eight byte data path to the data. The method also includes compressing the data inline. The method may further include writing the data in a memory through a memory controller using a RAID engine. The method may also include manipulating the data through the RAID engine. In addition, the method may include reading the data through a Serial Attached SCSI (SAS) core. The method may further include writing the data to a non-volatile storage. The method may include applying a compression technique based on a data history. The method may also include maintaining a consistent order of a sequence of the data during a data compression operation and a decompression operation.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: March 26, 2013
    Assignee: LSI Corporation
    Inventor: Rajendra Sadanand Marulkar
  • Patent number: 8397035
    Abstract: A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiyuki Tanaka
  • Patent number: 8392674
    Abstract: Methods and apparatus are provided for allowing a component such as a processor on a programmable chip efficient access to properly transformed data an embedded memory. Circuitry is provided with the read data port associated with an embedded memory. The circuitry can be used to perform both static bit width configuration of an embedded memory as well as perform data transformation or data alignment of embedded memory read data. The circuitry can allow efficient data transformations including selection of half words and bytes as well as perform sign extension and zero extension of memory read data.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: March 5, 2013
    Assignee: Altera Corporation
    Inventor: James L. Ball
  • Publication number: 20120324130
    Abstract: Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.
    Type: Application
    Filed: August 30, 2012
    Publication date: December 20, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Harold B. Noyes
  • Patent number: 8260987
    Abstract: Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: September 4, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • Patent number: 8239603
    Abstract: A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: August 7, 2012
    Assignee: Standard Microsystems Corporation
    Inventors: Drew J. Dutton, Alan D. Berenbaum, Raphael Weiss
  • Patent number: 8239590
    Abstract: An embodiment of a technique to transfer data between two different interfaces is disclosed. The embodiment of the technique includes: manipulating data arriving at a first data interface with a first word width into data with a second word width; transferring the manipulated data to a second data interface having the second word width; and selecting one of a plurality of different word widths for one of the first or second word widths.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: August 7, 2012
    Assignee: Xilinx, Inc.
    Inventors: Wayne E. Wennekamp, Adam Elkins, Schuyler E. Shimanek, Steven E. McNeil
  • Patent number: 8166220
    Abstract: A dual-interface connector for providing an interface to a storage device and an interface to a host and for connecting between a storage device and a host includes a storage device interface, for connecting with a storage device, and a host interface, for connecting with a host. A controller is operable in at least two distinct modes of operation. In a first mode of operation, the controller enables a session to be opened, by the host, between the storage device and the host when the storage device is connected to the storage device interface and the host is connected to the host interface. In a second mode of operation, the controller is operative, if an open session exists between the storage device and the host, to maintain the open session between the storage device and the host even after the storage device is disconnected from the storage device interface.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: April 24, 2012
    Assignee: Sandisk IL Ltd.
    Inventors: Shai Ben-Yacov, Itzhak Pomerantz, Judah Gamliel Hahn
  • Patent number: 8166217
    Abstract: A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Theodore C. White, William W. Dennin, Angel G. Perozo
  • Patent number: 8131897
    Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a first processor configured to exchange data with a first data length format, a second processor configured to exchange data with a second data length format and a shared memory configured to store data, the shared memory being shared by the first and second processors, the shared memory further configured to receive a read command from at least one of the first and second processors and to output data in response to the read command based on which of the first and second data length formats is used by the processor issuing the read command.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: March 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Young Kim, Mi-Jo Kim, Jung-Soo Ryoo
  • Patent number: 8122170
    Abstract: A method for processing keystrokes is described herein. A first keystroke representing a symbol for a first operating system may be received on a first computer. The first keystroke may be translated to a second keystroke representing the symbol for a second operating system on a second computer. The second operating system is different from the first operating system. The second keystroke may be sent to the second computer.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: February 21, 2012
    Assignee: Microsoft Corporation
    Inventors: Jingxia Xing, Shengyong Li, Dinghao Zeng, Jun Li
  • Patent number: 8112563
    Abstract: An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The diagnostic data are transmitted via a first transmission channel and the load control data and the pilot data are transmitted via a second transmission channel.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: February 7, 2012
    Assignees: Infineon Technologies AG, Robert Bosch GmbH
    Inventors: Jens Barrenscheen, Peter Rohm, Angela Rohm, legal representative, Hannes Estl, Axel Aue, Jens Graf, Herman Roozenbeek
  • Patent number: 8073999
    Abstract: A system controller is presented that controls an output format of data according to a data congestion status of the data and then outputs the data over an output bus. Specifically, if there is data congestion, the system controller changes the format of the data to a format that matches a bus width of the output bus before outputting the data over the output bus. To give a specific example, the system controller changes the format of the data input over an input bus in an input format of 4 B to an output format of 5 B before outputting the data over the output bus. If there is no data congestion, the system controller outputs the data over the output bus without changing the input format.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: December 6, 2011
    Assignee: Fujitsu Limited
    Inventor: Masahiro Mishima