Abstract: Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input port of a memory having an input width and output port having an output width which is different than the input width. A plurality of data words are received at the input of the memory, wherein each data word has a width corresponding to the input width. The order of the plurality of input data words is rearranged; and an output word based upon the rearranged data words and having a width corresponding to the output width is generated. Various circuits and algorithms for implementing the methods are also disclosed.

Abstract: A disclosed image forming apparatus includes an image processing device including plural image processing units; a control device configured to control the plural image processing units; and a connection unit configured to connect the image processing device to the control device. Each of the plural image processing units is connected to the control device by one of plural channels; the image processing device is connected to the control device by a first bus including the channels; and the connection unit is provided on the first bus so that the image processing device is connected to the control device by a single connection unit.

Abstract: A network system connects with processes P1 to P5 that can mutually send and receive a broadcast message specified with no destination and a message specified with a specific process portion and change their states to parent or child processes. For example, process P1 is a parent process and processes P2 to P4 are child processes. When processes P1 to P4 constitute a group, each of child processes P2 to P4 stores parent process P1. Parent process P1 stores each of child processes P2 to P4 that store itself (P1). When process P5 in another group is connected, parent process P1 exchanges a message with process P5 for negotiation to determine either to be a parent process and change the other to a child process.

Abstract: The present invention variably controls the packet size that is used within a storage device in accordance with the communication environment outside the storage device. The storage device comprises a CHA that controls data transfers with a host and a DKA that controls data transfers with a disk drive. The upper level I/F judgment unit of the CHA judges the type and communication band of the communication protocol used by the host and the packet size setting unit sets the optimum packet size on the basis of the type of communication protocol thus identified, and so forth. Likewise, the DKA sets the optimum packet size on the basis of the type and data processing speed of the disk drive that is used. As a result, data can be shifted rapidly to a packet in exchanges between the host and cache memory and between the disk drive and cache memory, whereby the data transfer efficiency can be improved.

Abstract: When needing to make write accesses to both upper and lower sides of a counter in a timer, a CPU accesses the lower side last, and accesses the lower side first when needing to make read accesses thereto. The timer stores data of the data bus in the write buffer at the write access to the upper side, and writes the data of the data bus to the lower side and writes the data of the write buffer to the upper side at the write access to the lower side. At the read access to the lower side of the counter, the timer reads the data of the lower side for output to the data bus and reads the data of the upper side for storage in the read buffer. At the read access to the upper side, it outputs data of the read buffer to the data bus.

Abstract: A system-on-chip (100) includes a 16-bit DSP (102), a 16-bit data bus (202) coupled to the DSP, at least one 32-bit-only peripheral (110), a 32-bit data bus (212) coupled to the peripheral, and a bridge (108), including a write merge system (200), coupled between the 16-bit and 32-bit buses. A method of the write merge system includes pre-storing addresses of peripherals in a memory map structure (220 and 221), receiving 16-bit data and a write transaction from the DSP for modifying sixteen bits of a 32-bit data location of the peripheral; reading 32-bit contents of the data location of the peripheral; multiplexing the received 16-bit data with the read 32-bit contents; and writing a new 32-bit word, including the modified sixteen bits and an unmodified sixteen bits, to the data location of the peripheral, without any intervention from the DSP subsequent to receiving the write transaction.

Abstract: A method for communicating between a first bus and a second bus is disclosed. The method generally includes the steps of (A) recognizing a read operation code in a read frame (i) received from the first bus and (ii) communicated with a first-bus protocol, (B) initiating a read transaction on the second bus using a second-bus protocol different than the first-bus protocol, wherein the initiating occurs earlier than a turn around time in the first-bus protocol that provides a plurality of bit times to respond to the read operation code and (C) transmitting read data received from the second bus on the first bus immediately after the turn around time.

Abstract: A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device. The input buffer is operably coupled to store at least one data block of incoming data. The serializing module serializes the data block as it is retrieved from the input buffer to produce a serial stream of data. The programmable logic device receives the serial stream of data and distributes it to one or more of the at least one deserializing modules. The at least one deserializing module converts the serial stream back into the data block. The recaptured data block is then provided to the corresponding output buffer, which stores the recaptured data.

Abstract: Methods and Apparatuses are provided for automatically converting a word length of sample data being transmitted over a serial link. A serial interface transmits and/or receives one or more data words comprising digital signals, a bit clock synchronizes transmission of individual bits, and a word clock is used to group the bits into sample words. A desired word length is determined based on the relationship between the bit clock and the word clock during the transmission or reception of a data word. Based on the desired word length, the sample data is either truncated or padded, and an appropriate amount of dither is added to the sample words to reduce the distortion and quantization artifacts introduced by the word length conversion.

Abstract: An apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus is described. Setting configuration bits allows the interface apparatus to be programmed to operate as a transmitter or a receiver with selectable device interface modes. When operating as a transmitter, the interface apparatus combines and compresses the system data bus, clocks, and control signals to match the available width of the parallel data bus. When operating as a receiver, the interface receives signals from the parallel data bus and restores the original signals which were combined and compressed. The device interface modes are selectable to be compatible in different device and circuit configurations.

Abstract: A data aligner aligns a data segment having a granularity of less than a width of an internal data path. The data aligner aligns a fragment of data for alignment with a current segment or delay the fragment to combine with a next segment for alignment of data. A buffer receives the aligned data from the data aligner for interim storage and subsequent output onto an internal data path.

Abstract: A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference.

Abstract: Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes a link bridge that includes upstream (located closest to the CPU) configuration registers that are within the first control circuit and downstream ((located farthest from the CPU) configuration registers within the second control circuit. A link header, which includes upstream data for the first control circuit and down stream data for the second control circuit, is used to initialize the link. The upstream and downstream data may include information specifying the size of the communication link.

Abstract: A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ones of a first rising edge and a first falling edge of the clock, respectively, to generate two plurality of instances of sampled data having a first width. The plurality of instances of sampled data is then sampled at a second rising edge of the clock and parallelized to generate a second plurality of instances of parallel data having a second width greater than the first width. The parallel data may then be processed to for example generate statistics to monitor link integrity, prior to being transmitted. A 10 Gbps data transmission speed may be maintained using the IEEE 802.3ae-specified media independent interface clock.

Abstract: An appliance includes a physical interface for communication according to a broad protocol and two functional components. The first functional component communicates via the physical interface. The second functional component includes a functional module adapted to communicate according to a narrow protocol and an emulation module that transforms between the two protocols so that the two functional components can communicate with each other using the physical interface.

Abstract: A voice signal is transmitted in an MOST network on a single channel. The width of the transmitted voice data words is preferably up to 14 bits, and each voice data word is transmitted into successive clock periods of the MOST network, in a byte that includes seven bits of the voice data word and one identifier bit.

Abstract: A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a packet data transfer circuit that uses a fragment storage buffer to align and/or merge data being transferred to or from memory on a plurality of channels. In a packet reception embodiment, a data shifter and fragment store buffer are used to align received packet data to any required offset. The aligned data may and then be written to the system bus or combined with data fragments from prior data cycles before being written to the system bus. When packet data is being transferred to memory on a plurality of channels, the fragment storage may be channelized using register files or flip-flops to store intermediate values of packets and states for each channel.

Abstract: Buffer control means and output control means are included within a buffering apparatus. Data longer than the width of data bus is read by single access from buffer means. Rather than signal line control for each bus width, signal line control for each data group is performed by a method wherein address administration means holds address information in relationship with each group of a series of data written in the buffer means and data is output from the buffer means.

Abstract: A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.

Abstract: An integrated circuit includes M first terminals and N second terminals, where M and N are positive integers, and where M>N>1. The circuit further includes a converter which receives M base-A-level input signals from the M first terminals, respectively, encodes each of AM values represented by the M base-A-level input signals as a different base-K value represented by N base-K-level output signals, A and K are positive integers, and where K>A>1. The converter then outputs the N base-K-level output signals to the N second terminals, respectively.

Abstract: A method and apparatus for transferring data between storage systems including a first disk system for receiving first data in a variable length data format from a host, storing the first data and sending the first data over an I/O channel for data in the variable length data format, a second storage system for receiving the first data from the first storage system, converting the first data from the first storage system to second data in a fixed block data format and sending the second data over an I/O channel for data in the fixed block data format, and a third storage system for receiving the second data from the second storage system, converting the second data from the second storage system back to the first data and storing the first data.

Abstract: A method and apparatus are provided for implementing data mapping using a shuffle algorithm. An output shuffler and an input shuffler convert a physical data group to a plurality of data subgroups. The physical data group includes a plurality of bits and each subgroup includes a subplurality of bits. The output shuffler performs an output shuffle sequence for providing a predefined output pattern of ordered subplurality data bits. The predefined output pattern of ordered subplurality data bits is applied to the input shuffler. The input shuffler performs a reverse shuffle sequence. For each shuffle transfer a number of first header bytes of a packet are located at a first one of a plurality of physical layer links. Both the output shuffler and the input shuffler are implemented with minimized logic required to keep a largest multiplexer as a 4-to-1 multiplexer, resulting in minimal area and power being used for implementing the shuffle sequence and reverse shuffle sequence.

Abstract: A data bus width conversion apparatus is provided for receiving N-bit data from a first device having a first bus width and outputting the N-bit data to a second device having a second bus width. The first device divides the N-bit data into a plurality of bit data groups and the plurality of bit data groups are transferred to the apparatus. The apparatus comprises a setting section for setting the total number of transfer operations required for the first device to transfer the plurality of bit data groups, and for setting a division pattern of the N-bit data for dividing the N-bit data into the plurality of bit data groups, a receiving section, and an output section for producing the N-bit data from the received data indicated by each of the plurality of bit data groups and outputting the produced N-bit data to the second device.

Abstract: In a data processor including a master circuit that issues an access request and slave circuits that perform processing in response to the access request received from the master circuit, the disclosed invention enables the master circuit to access all data areas of the slave circuits even if the master circuit does not have an access command in data size suitable for accessing the slave circuit. An access size control unit that can convert access size input from the master circuit to data size in which the slave circuit accepts access is installed between the master circuit and the slave circuit. The access size control unit retains at least one address for access size setting. As the master circuit accesses the appropriate address for access size setting, the access size conversion procedure can be carried out.

Abstract: Data is stored in multiple formats based on the nature of the data and the characteristics of the possible output devices to minimize processing requirements and processing time while maximizing output quality. A data set is broken into objects and further into units so that each unit within an object contains a similar data type. Units that require less processing power for presentation are stored in a device-independent format. Units that require more processing power for presentation are stored in device-dependent form at determined by the presentation parameters of an attached peripheral presentation device. At presentation time a document database, or storage area, assembles the document from the units determined by the presentation device. The document is composed of data that is specific for the presentation device or data that is device independent.

Abstract: In an arrangement in which a CPU transmits data such as audio data through a 32-bit data bus, a format conversion device and a format conversion program are a are newly prepared. Further, input data having a first bit-width (32 bit width) is converted to output data having a second bit-width (24 bit width) in accordance with a predetermined system so that the efficiency of use of the bus at the time of transmitting data is improved; thus, it becomes possible to reduce a data memory area required for multi-media processes.

Abstract: A memory device is so adapted that data processing time is not prolonged even when there is little bus width. A DRAM is connected to first to third buffer circuits by buses, which have a bus width of 128 bits, via a selector. The first to third buffer circuits are connected to a circuit such as a signal processing circuit by buses having a bit width of 32 bits. Since part of the circuitry is connected by buses having a bit width of 32 bits, the wiring is simple. By executing various processing in parallel, it is possible to prevent prolongation of the time required to record image data on a memory card.

Abstract: The present invention relates to the reduction of artifacts introduced by sending data at a higher rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract: Once attached to a slot of a personal digital assistant, a card module executes an application-specific program and transmits a result obtained thereby to the personal digital assistant. The thus received execution result is outputted from an output part. Accordingly, the output part can be provided for shared use among several card modules for output of the execution result.

Abstract: A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ones of a first rising edge and a first falling edge of the clock, respectively, to generate two plurality of instances of sampled data having a first width. The plurality of instances of sampled data is then sampled at a second rising edge of the clock and parallelized to generate a second plurality of instances of parallel data having a second width greater than the first width. The parallel data may then be processed to for example generate statistics to monitor link integrity, prior to being transmitted. A 10 Gbps data transmission speed may be maintained using the IEEE 802.3ae-specified media independent interface clock.

Abstract: A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Abstract: Once attached to a slot of a personal digital assistant, a card module executes an application-specific program and transmits a result obtained thereby to the personal digital assistant. The thus received execution result is outputted from an output part. Accordingly, the output part can be provided for shared use among several card modules for output of the execution result.

Abstract: A compression system is arranged to use software and/or hardware accelerated compression techniques to increase compression speeds and enhance overall data throughput. A logic circuit is arranged to: receive a data stream from a flow control processor, buffer the data stream, select a hardware compressor (e.g., an ASIC), and forward the data to the selected hardware compressor. Each hardware compressor performs compression on the data (e.g., LZ77), and sends the compressed data back to the logic circuit. The logic circuit receives the compressed data, converts the data to another compressed format (e.g., GZIP), and forwards the converted and compressed data back to the flow control processor. History associated with the data stream can be stored in memory by the flow control processor, or in the logic circuit.

Abstract: A data transfer control device and an electronic instrument which can implement a process to be made on data transmitted and received through a high speed bus on a circuit operating at a low frequency. The data transfer control device has a conversion circuit which converts K-bit width data transferred at a frequency FC1 (in USB 2.0 HS mode) through a bus into data having an L-bit width (L>K) by rearranging, and a processing circuit which receives the L-bit width data from the conversion circuit and carries out a K-bit based process on an L-bit basis at a frequency FC2 lower than FC1. This enables to perform the K-bit based process at the low frequency FC2. Configuration on a transmission end can be implemented in the same manner. The transfer data in the USB 2.0 HS mode is processed on the L-bit basis while the transfer data in the FS mode is processed on the K-bit basis. The present invention is applicable also to the process on data transferred through a bus under the IEEE1394 or SCSI.

Abstract: An external bus controller which is configured such that, when an external device having a data width smaller than that of an external bus is connected to the external bus, the signal lines of the external bus can be freely selected. This external bus controller includes a first exchange, which converts the data width of input/output data so as to compensate for differences between the data width of the internal bus and the data width of an external device, and a second exchange, which exchanges signal lines between the first exchange and the used signal lines. The signal lines to be used are set for each external device using configuration pins or similar means.

Abstract: The present invention provides an apparatus and method for selecting bus-width formats. In an exemplary preferred embodiment of the invention, the circuit includes a bus controller configured to provide a first bus-width control signal to select a first bus-width. The circuit also includes a bus controller extension circuit configured to force the first bus-width control signal to a predetermined level when the bus controller is applied to a bus with a second bus controller that is incompatible with the first bus-width. Advantages of the invention include controlling a number of data bits to be transferred between a PCI device and a data bus that does not violate PCI specifications. Other advantages include a programmability of the PCI device to adapt to legacy systems as PCI technology progresses.

Abstract: A method and a related apparatus for controlling a transmission interface between a computer system and an external device is disclosed. The external device includes a bridge circuit for controlling the transmission interface of the external device, a driver circuit for controlling the external device according to outputs of the bridge circuit, and a memory connected to the driver circuit for storing transmission interface data. Before the computer system obtains the transmission interface data, the bridge circuit transmits a control command to the driver circuit such that the driver circuit retrieves the transmission interface data stored in the memory, and transmits the transmission interface data to the computer system such that the computer system can properly transmit data to the bridge circuit according to the transmission interface data.

Abstract: A system and method that converts a series of input data words at a first data width to a series of output data words at a smaller data width. In order to achieve 10-Gigabit Ethernet over an optical network, data must be converted from 66-bit words to 64-bit words (the smaller data width) at a faster clock rate, such that the concatenation of the series of input data is equivalent to the concatenation of the series of output data. This is accomplished by shifting the input data such that it is either prefixed by zeros, suffixed by zeros, or both, depending on the stage of the progression of the series. The shifted data is then split up, with a portion of the data going into a delay register and another portion of the data either being output directly or combined with data previously stored in the delay register.

Abstract: A data transfer control device and an electronic instrument which can implement a process to be made on data transmitted and received through a high speed bus on a circuit operating at a low frequency. The data transfer control device has a conversion circuit which converts K-bit width data transferred at a frequency FC1 (in USB 2.0 HS mode) through a bus into data having an L-bit width (L>K) by rearranging, and a processing circuit which receives the L-bit width data from the conversion circuit and carries out a K-bit based process on an L-bit basis at a frequency FC2 lower than FC1. This enables to perform the K-bit based process at the low frequency FC2. Configuration on a transmission end can be implemented in the same manner. The transfer data in the USB 2.0 HS mode is processed on the L-bit basis while the transfer data in the FS mode is processed on the K-bit basis. The present invention is applicable also to the process on data transferred through a bus under the IEEE1394 or SCSI.

Abstract: A head and tail caching system. The system includes a tail FIFO memory having a tail input to receive incoming data. A memory is included that is operable to store data that is output from the tail FIFO and output the stored data at a memory output. A multiplexer is included having first and second multiplexer inputs coupled to the tail FIFO and the memory, respectively. The multiplexer has a control input to select one of the multiplexer inputs to coupled to a multiplexer output. A head FIFO memory receives data from the multiplexer output, and outputs the data on an output data path. A controller is operable to transfer one or more blocks data having a selected block size from the tail FIFO to the memory and from the memory to the head FIFO, to achieve a selected efficiency level.

Abstract: In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.

Abstract: A network system connects with a number of individual processes that can mutually send and receive a broadcast message specified with no destination and a message specified with a specific process and that can change their states to parent or child processes. When a first process is a parent process and second through fourth processes are child processes, the four processes constitute a group, in which each of child processes stores the parent process, and the parent process stores each of child processes that store the parent process itself. When a new process that is in another group is connected to this group, the parent process exchanges a message with the new process for negotiation to determine either whether to be a parent process or to change to a child process.

Abstract: A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ones of a first rising edge and a first falling edge of the clock, respectively, to generate two plurality of instances of sampled data having a first width. The plurality of instances of sampled data is then sampled at a second rising edge of the clock and parallelized to generate a second plurality of instances of parallel data having a second width greater than the first width. The parallel data may then be processed to for example generate statistics to monitor link integrity, prior to being transmitted. A 10 Gbps data transmission speed may be maintained using the IEEE 802.3ae-specified media independent interface clock.

Abstract: A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The interface includes: a global memory; a plurality of front-end directors coupled between the global memory and the host computer/server; and, a plurality of back-end directors coupled between the global memory and the bank of disk drives. Each one of the first directors and each one of the second directors has a data pipe. Each one of such front-end directors passes front-end data between the global memory and the host computer through the data pipe therein and each one of the second directors passing back-end data between the global memory and the bank of disk drives through the data pipe therein.

Abstract: A system and method for transmitting parallel data from a source to a destination over a plurality of high speed serial lines operates reliably even in the presence of data skew. The high speed data transmission system includes a protocol generator, a de-skew circuit, and a plurality of high speed serial lines coupled between the protocol generator and the de-skew circuit. Respective serial representations of parallel data words are transmitted to the destination over a plurality of serial data lines, and a clock signal is transmitted to the destination over a clock line in parallel with the serial data lines. The clock signal has at least one data bit of each parallel data word encoded thereon. The de-skew circuit aligns regenerated parallel data words using the respective data bits encoded on the clock signal to eliminate skew among the data bits, and regenerates the parallel data from the aligned parallel data words.

Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: A translation system and method for translating file systems between nodes having heterogeneous file systems are provided. The translation system includes a consumer node having a first file system and a driver for supplementing requests from the first file system to a storage device. Also included in the translation system is an input/output (I/O) node which implements a second file system. The I/O node is connected to the storage device and is in communication with the consumer node over a transport. The I/O node includes a translator layer designed to map the supplemented requests from the first file system to the second file system and back to the first file system.

Abstract: The apparatus and method for transferring audio data to a data recorder adopting a personal computer bus to receive audio data enters into data communication mode over a bus without conducting preparation steps for transferring data when a record request is received. The preparation steps include occupying the bus and issuing packet commands. Real-time data such as an audio signal are transferred with no delay to a general optical disk driver satisfying the personal computer (PC) bus interfacing requirement. This allows adoption of a general disk driver for data recording instead of an exclusive audio disk driver, thereby reducing manufacturing cost of a digital audio recorder and enabling the disk driver installed in a digital audio recorder to be used in other devices such as a PC.

Abstract: A system and method for data processing includes packing multiple signed data elements per register into a processor's registers using the rules set forth herein, and simultaneously operating on the elements in a register in a single cycle using the same operand. The elements can be independent of each other, and the sizes of the elements in a register can differ from each other. Moreover, a relatively large element can be split across multiple registers. In an exemplary application, a data stream representing two images can be simultaneously processed using the same number of registers as have been required to process a single image. Or, a single image can be processed approaching N-times faster, where N is the number of elements per register. In any case, the present invention results in a significant increase in processing efficiency.

Abstract: A separator pad for stacked containers is composed of a spunbonded central fabric of polypropylene having a basis weight of 6 to 11 oz. per square yard and outer flat layers of polypropylene.